JP5782166B2 - 裏面モールド構成(bsmc)の使用によるパッケージの反りおよび接続の信頼性を向上させるためのプロセス - Google Patents
裏面モールド構成(bsmc)の使用によるパッケージの反りおよび接続の信頼性を向上させるためのプロセス Download PDFInfo
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- H01L2224/8119—Arrangement of the bump connectors prior to mounting
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- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
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- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Description
本出願は、2010年5月20日に出願されたBCHIRらによる「Process for Improving Package Warpage and Connection Reliability through Use of a Backside Mold Configuration (BSMC)」という名称の米国仮特許出願第61/346,725号の利益を主張する。
104 パッケージング接続部
112 ダイ
114 パッケージング接続部
300 パッケージング基板
302 導電ライン
304 パッケージング接続部
306 モールド材料
308 絶縁体
312 ダイ
314 パッケージング接続部
316 アンダーフィル
318 モールド材料
320 誘電体
330 基材
340 開口
350 パッケージング接続部
390 パッケージングされた集積回路
500 パッケージング基板
502 導電ライン
504 パッケージング接続部
506 モールド材料
508 絶縁体
512 ダイ
514 パッケージング接続部
516 アンダーフィル
518 モールド材料
520 誘電体
530 基材
550 パッケージング接続部
560 開口
600 ワイヤレス通信システム
620 遠隔ユニット
625A ICデバイス
625B ICデバイス
625C ICデバイス
630 遠隔ユニット
640 基地局
650 遠隔ユニット
680 順方向リンク信号
690 逆方向リンク信号
700 設計用ワークステーション
701 ハードディスク
703 ドライブ装置
704 記憶媒体
710 回路
712 半導体コンポーネント
Claims (11)
- パッケージング基板と、
前記パッケージング基板の第1の側面上の誘電体と、
前記誘電体上に直接配置される第1のモールド材料と、
前記第1のモールド材料および前記誘電体を介して前記パッケージング基板の前記第1の側面上のコンタクトパッドに結合される第1のパッケージング接続部と、
前記パッケージング基板の前記第1の側面の反対側の前記パッケージング基板の第2の側面上に配置される第2のモールド材料と、
前記第2のモールド材料によって囲まれ、前記パッケージング基板に結合されるダイと、
を含み、
前記第1のモールド材料の開口の径が、前記誘電体の開口の径以上である装置。 - 前記第1のモールド材料が前記第1のパッケージング接続部を囲む、請求項1に記載の装置。
- 前記誘電体がはんだレジストを含み、
前記第1のモールド材料は、前記装置が前記第1のモールド材料と前記はんだレジストとの間に介在層を有さないように、前記はんだレジストと直接接触している、請求項1に記載の装置。 - 前記ダイがベアダイを含む、請求項1に記載の装置。
- パッケージングされた集積回路が、前記パッケージングされた集積回路に電気的に結合された前記第1のパッケージング接続部を含む、請求項1に記載の装置。
- 携帯電話、セットトップボックス、音楽プレーヤ、ビデオプレーヤ、エンターテインメントユニット、ナビゲーションデバイス、コンピュータ、ハンドヘルドパーソナル通信システム(PCS)ユニット、ポータブルデータユニット、および/または固定ロケーションデータユニットに組み込まれる、請求項1に記載の装置。
- 前記第1のモールド材料および前記誘電体を介して前記パッケージング基板の前記第1の側面上のコンタクトパッドに結合される第2のパッケージング接続部をさらに含み、前記第1のモールド材料および前記誘電体が、前記第1のパッケージング接続部と前記第2のパッケージング接続部との間に配置され、前記第1のパッケージング接続部と前記第2のパッケージング接続部とを囲む、請求項1に記載の装置。
- パッケージング基板と、
前記パッケージング基板の第1の側面上の誘電体と、
前記誘電体を介して前記パッケージング基板の前記第1の側面上のコンタクトパッドに結合される第1のパッケージング接続部と、
前記パッケージング基板の前記第1の側面上のパッケージング接続部の信頼性のための手段であって、前記第1のパッケージング接続部を囲み、前記誘電体上に直接配置される、前記パッケージング接続部の信頼性の手段と、
ダイと前記パッケージング基板との間の接続の信頼性のための手段であって、前記ダイが前記パッケージング基板の前記第1の側面の反対側の前記パッケージング基板の第2の側面上の接続の信頼性の手段によって囲まれる、手段と、
を含み、
前記パッケージング基板の前記第1の側面上のパッケージング接続部の前記信頼性のための手段の開口の径が、前記誘電体の開口の径以上である装置。 - 前記誘電体がはんだレジストを含み、
前記パッケージング基板の前記第1の側面上の前記パッケージング接続部の信頼性のための手段は、前記装置が前記パッケージング基板の前記第1の側面上の前記パッケージング接続部の信頼性のための手段と前記はんだレジストとの間に介在層を有さないように、前記はんだレジストと直接接触している、請求項8に記載の装置。 - 携帯電話、セットトップボックス、音楽プレーヤ、ビデオプレーヤ、エンターテインメントユニット、ナビゲーションデバイス、コンピュータ、ハンドヘルドパーソナル通信システム(PCS)ユニット、ポータブルデータユニット、および/または固定ロケーションデータユニットに組み込まれる、請求項8に記載の装置。
- 前記誘電体を介して前記パッケージング基板の前記第1の側面上のコンタクトパッドに結合される第2のパッケージング接続部をさらに含み、前記パッケージング接続部の信頼性の手段および前記誘電体が、前記第1のパッケージング接続部と前記第2のパッケージング接続部との間に配置され、前記第1のパッケージング接続部と前記第2のパッケージング接続部とを囲む、請求項8に記載の装置。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US34672510P | 2010-05-20 | 2010-05-20 | |
US61/346,725 | 2010-05-20 | ||
US12/882,525 | 2010-09-15 | ||
US12/882,525 US8742603B2 (en) | 2010-05-20 | 2010-09-15 | Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC) |
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Application Number | Title | Priority Date | Filing Date |
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JP2013510368A Division JP2013530523A (ja) | 2010-05-20 | 2011-05-19 | 裏面モールド構成(bsmc)の使用によるパッケージの反りおよび接続の信頼性を向上させるためのプロセス |
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JP2015086593A Division JP2015144317A (ja) | 2010-05-20 | 2015-04-21 | 裏面モールド構成(bsmc)の使用によるパッケージの反りおよび接続の信頼性を向上させるためのプロセス |
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JP2014187399A JP2014187399A (ja) | 2014-10-02 |
JP5782166B2 true JP5782166B2 (ja) | 2015-09-24 |
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JP2013510368A Pending JP2013530523A (ja) | 2010-05-20 | 2011-05-19 | 裏面モールド構成(bsmc)の使用によるパッケージの反りおよび接続の信頼性を向上させるためのプロセス |
JP2014137591A Expired - Fee Related JP5782166B2 (ja) | 2010-05-20 | 2014-07-03 | 裏面モールド構成(bsmc)の使用によるパッケージの反りおよび接続の信頼性を向上させるためのプロセス |
JP2015086593A Pending JP2015144317A (ja) | 2010-05-20 | 2015-04-21 | 裏面モールド構成(bsmc)の使用によるパッケージの反りおよび接続の信頼性を向上させるためのプロセス |
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US (2) | US8742603B2 (ja) |
EP (1) | EP2572372B1 (ja) |
JP (3) | JP2013530523A (ja) |
KR (1) | KR101485752B1 (ja) |
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KR102466431B1 (ko) * | 2019-07-05 | 2022-11-11 | 나노-디멘션 테크놀로지스, 엘티디. | 적층 제조 전자 부품에 대한 표면-상보형 유전체 마스크, 제조 방법 및 그 용도 |
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-
2010
- 2010-09-15 US US12/882,525 patent/US8742603B2/en active Active
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2011
- 2011-05-19 EP EP11725236.1A patent/EP2572372B1/en active Active
- 2011-05-19 JP JP2013510368A patent/JP2013530523A/ja active Pending
- 2011-05-19 WO PCT/US2011/037211 patent/WO2011146751A1/en active Application Filing
- 2011-05-19 CN CN201180023796.7A patent/CN102906866B/zh active Active
- 2011-05-19 KR KR20127033334A patent/KR101485752B1/ko not_active IP Right Cessation
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2014
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- 2014-07-03 JP JP2014137591A patent/JP5782166B2/ja not_active Expired - Fee Related
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KR101485752B1 (ko) | 2015-01-21 |
US20150221528A9 (en) | 2015-08-06 |
CN102906866B (zh) | 2015-12-02 |
CN102906866A (zh) | 2013-01-30 |
US20110285026A1 (en) | 2011-11-24 |
US8742603B2 (en) | 2014-06-03 |
KR20130031845A (ko) | 2013-03-29 |
US20140227835A1 (en) | 2014-08-14 |
EP2572372B1 (en) | 2020-09-02 |
JP2014187399A (ja) | 2014-10-02 |
WO2011146751A1 (en) | 2011-11-24 |
JP2013530523A (ja) | 2013-07-25 |
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JP2015144317A (ja) | 2015-08-06 |
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