JP5579108B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5579108B2 JP5579108B2 JP2011058140A JP2011058140A JP5579108B2 JP 5579108 B2 JP5579108 B2 JP 5579108B2 JP 2011058140 A JP2011058140 A JP 2011058140A JP 2011058140 A JP2011058140 A JP 2011058140A JP 5579108 B2 JP5579108 B2 JP 5579108B2
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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Description
図1は、第1の実施の形態にかかる半導体装置の構成例を示すブロック図である。半導体装置100は、SATAインタフェース(ATA I/F)2などのメモリ接続インタフェースを介してパーソナルコンピュータあるいはCPUコアなどのホスト装置(以下、ホストと略す)1と接続され、ホスト1の外部メモリとして機能する。ホスト1としては、パーソナルコンピュータのCPU、スチルカメラ、ビデオカメラなどの撮像装置のCPUなどがあげられる。また、半導体装置100は、RS232Cインタフェース(RS232C I/F)などの通信インタフェース3を介して、デバッグ用機器200との間でデータを送受信することができる。
図11は、第2の実施の形態にかかる半導体装置が備える基板の層構成を示す図である。本実施の形態では、基板8の第8層の外側に、9層目の層として最外層を設けている。そして、最外層の全域を銅箔で覆ってシールド層としている。このように、最外層の全域を銅箔で覆うことで、半導体装置からのノイズの漏れをより確実に防ぐことができる。なお、9層目よりも内側の層の全域を銅箔で覆ってシールド層としてもよい。
図12は、第3の実施の形態にかかる半導体装置の搬送方法に用いる保持部材の外観斜視図である。図13は、図12に示す保持部材が箱に収納された状態を示す断面図である。本実施の形態では、半導体装置100を保持部材50で梱包して搬送する。保持部材50は、経時変化による基板8の反りを抑制する。
Claims (5)
- 配線パターンが形成された多層基板と、
前記多層基板の上層側表面層に設けられた不揮発性半導体記憶素子と、
前記不揮発性半導体記憶素子の表面を露出させつつ、前記不揮発性半導体記憶素子同士の隙間と、前記不揮発性半導体記憶素子と前記多層基板との隙間に充填された接着部と、を備え、
前記多層基板の下層側内層に形成された前記配線パターンのうち、前記不揮発性半導体記憶素子同士の隙間に対向する部分の少なくとも一部にスリットが形成されている半導体装置。 - 前記多層基板は、平面視において略長方形形状を呈し、前記不揮発性半導体記憶素子は、前記多層基板の上層側表面層に長手方向に沿って並んでいる請求項1に記載の半導体装置。
- 前記配線パターンは、下層側内層の略全域に形成され、プレーン層を構成する請求項1に記載の半導体装置。
- 前記接着部は、前記不揮発性半導体記憶素子同士の隙間のみにおいてその表面が露出していることを特徴とする請求項1に記載の半導体装置。
- 前記接着部は、前記不揮発性半導体記憶素子同士を引き寄せる方向に応力を発生させる請求項1に記載の半導体装置。
Priority Applications (23)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011058140A JP5579108B2 (ja) | 2011-03-16 | 2011-03-16 | 半導体装置 |
TW109125654A TWI733539B (zh) | 2011-03-16 | 2012-02-23 | 半導體裝置 |
TW106141659A TWI660485B (zh) | 2011-03-16 | 2012-02-23 | Semiconductor device |
TW101106090A TWI505439B (zh) | 2011-03-16 | 2012-02-23 | 半導體記憶體系統 |
TW105131158A TWI613789B (zh) | 2011-03-16 | 2012-02-23 | 半導體裝置及記憶體系統 |
TW104125728A TWI560847B (en) | 2011-03-16 | 2012-02-23 | Semiconductor devices and memory system |
TW111103509A TWI831121B (zh) | 2011-03-16 | 2012-02-23 | 半導體裝置 |
TW108112947A TWI700809B (zh) | 2011-03-16 | 2012-02-23 | 半導體裝置 |
TW110123423A TWI758200B (zh) | 2011-03-16 | 2012-02-23 | 半導體裝置及配線基板 |
CN201910505029.8A CN110246825B (zh) | 2011-03-16 | 2012-03-01 | 半导体装置和系统 |
CN2012100522252A CN102682842A (zh) | 2011-03-16 | 2012-03-01 | 半导体存储器系统 |
CN202310754750.7A CN116666351A (zh) | 2011-03-16 | 2012-03-01 | 半导体装置和系统 |
CN201610585991.3A CN105957855B (zh) | 2011-03-16 | 2012-03-01 | 半导体装置和存储器系统 |
US13/418,619 US8873265B2 (en) | 2011-03-16 | 2012-03-13 | Semiconductor memory system |
US14/324,683 US9312215B2 (en) | 2011-03-16 | 2014-07-07 | Semiconductor memory system |
US14/511,676 US9437533B2 (en) | 2011-03-16 | 2014-10-10 | Semiconductor memory system |
US15/254,825 US9754632B2 (en) | 2011-03-16 | 2016-09-01 | Semiconductor memory system |
US15/378,947 US9859264B2 (en) | 2011-03-16 | 2016-12-14 | Semiconductor memory system |
US15/822,039 US10388640B2 (en) | 2011-03-16 | 2017-11-24 | Semiconductor memory system |
US16/502,288 US10607979B2 (en) | 2011-03-16 | 2019-07-03 | Semiconductor memory system |
US16/800,398 US11063031B2 (en) | 2011-03-16 | 2020-02-25 | Semiconductor memory system |
US17/342,748 US11705444B2 (en) | 2011-03-16 | 2021-06-09 | Semiconductor memory system |
US18/203,693 US20230307433A1 (en) | 2011-03-16 | 2023-05-31 | Semiconductor memory system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011058140A JP5579108B2 (ja) | 2011-03-16 | 2011-03-16 | 半導体装置 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013146692A Division JP5458206B2 (ja) | 2013-07-12 | 2013-07-12 | 半導体装置 |
JP2014134709A Division JP5869058B2 (ja) | 2014-06-30 | 2014-06-30 | 半導体装置およびシステム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012195440A JP2012195440A (ja) | 2012-10-11 |
JP5579108B2 true JP5579108B2 (ja) | 2014-08-27 |
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Application Number | Title | Priority Date | Filing Date |
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JP2011058140A Active JP5579108B2 (ja) | 2011-03-16 | 2011-03-16 | 半導体装置 |
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US (10) | US8873265B2 (ja) |
JP (1) | JP5579108B2 (ja) |
CN (4) | CN116666351A (ja) |
TW (7) | TWI758200B (ja) |
Families Citing this family (15)
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JP5579108B2 (ja) | 2011-03-16 | 2014-08-27 | 株式会社東芝 | 半導体装置 |
US9668345B2 (en) * | 2012-03-30 | 2017-05-30 | Hitachi Chemical Company, Ltd. | Multilayer wiring board with metal foil wiring layer, wire wiring layer, and interlayer conduction hole |
JP6039318B2 (ja) * | 2012-08-31 | 2016-12-07 | 矢崎総業株式会社 | プリント配線基板 |
JP5458206B2 (ja) * | 2013-07-12 | 2014-04-02 | 株式会社東芝 | 半導体装置 |
JP5583262B2 (ja) * | 2013-11-25 | 2014-09-03 | 株式会社東芝 | 半導体装置およびシステム |
US9818682B2 (en) * | 2014-12-03 | 2017-11-14 | International Business Machines Corporation | Laminate substrates having radial cut metallic planes |
CN106663660B (zh) * | 2014-12-24 | 2019-11-05 | 瑞萨电子株式会社 | 半导体装置 |
KR102373543B1 (ko) * | 2015-04-08 | 2022-03-11 | 삼성전자주식회사 | 멀티칩 패키지에서 온도 편차를 이용하여 동작 제어하는 방법 및 장치 |
JP2017009725A (ja) * | 2015-06-19 | 2017-01-12 | ソニー株式会社 | 表示装置 |
JP6270805B2 (ja) * | 2015-12-24 | 2018-01-31 | 東芝メモリ株式会社 | 半導体装置およびシステム |
US10149377B2 (en) | 2016-06-24 | 2018-12-04 | Invensas Corporation | Stacked transmission line |
JP2020017133A (ja) * | 2018-07-26 | 2020-01-30 | キオクシア株式会社 | ストレージ装置及び制御方法 |
CN113966647A (zh) * | 2019-06-28 | 2022-01-21 | 3M创新有限公司 | 多层电路板 |
CN111935902A (zh) * | 2020-09-23 | 2020-11-13 | 歌尔股份有限公司 | 印制电路板 |
US11412610B2 (en) * | 2020-11-04 | 2022-08-09 | Juniper Networks, Inc | Apparatus, system, and method for mitigating the swiss cheese effect in high-current circuit boards |
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