JP5570953B2 - 不揮発性半導体記憶装置および不揮発性半導体記憶装置の製造方法 - Google Patents
不揮発性半導体記憶装置および不揮発性半導体記憶装置の製造方法 Download PDFInfo
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Description
図1は、第1実施形態に係る不揮発性半導体記憶装置のメモリセルの概略構成を示す斜視図である。
図1において、半導体基板1には、ビット線方向DBにトレンチ2が形成され、半導体基板1に形成されるメモリセルのアクティブエリアが分離されている。なお、メモリセルにおけるアクティブエリアは、メモリセルに設けられたメモリトランジスタのチャネル領域および直列に接続されたメモリセル間の領域(例えばソース/ドレイン領域)を言う。また、半導体基板1の材質としては、例えば、Si、Ge、SiGe、SiC、SiSn、PbS、GaAs、InP、GaP、GaN、GaInAsPまたはZnSeなどから選択することができる。
図2は、第2実施形態に係る不揮発性半導体記憶装置のメモリセルアレイの概略構成を示す回路図である。
図2において、メモリセル部R1には、セルトランジスタMTがロウ方向およびカラム方向にマトリックス状に配置されている。そして、複数のセルトランジスタMTが直列に接続され、この直列回路の両端にセレクトトランジスタSTが接続されることでNANDストリングNSが構成されている。また、カラム方向にはビット線BLが配置され、ロウ方向にはワード線WLおよびセレクトゲート電極SGが配置されている。
図3において、ビット線方向DBにはトレンチTCが形成され、アクティブエリアAAはトレンチTCにて分離されている。また、ワード線方向DWには、ワード線WLおよびセレクトゲート電極SGが形成されている。そして、セレクトゲート電極SG間には、ビットコンタクト部R3が設けられ、ビットコンタクト部R3のアクティブエリアAA上には、ビットコンタクトBCが形成されている。また、ワード線引き出し部R2のアクティブエリアAA上には、メモリセル部R1から引き出されたワード線WLのコンタクトをとるワードコンタクトWCが設けられるとともに、メモリセル部R1から引き出されたセレクトゲート電極SGのコンタクトをとるセレクトゲートコンタクトSCが設けられている。
図4〜図26は、第3実施形態に係る不揮発性半導体記憶装置の製造方法を示す断面図である。なお、図4(b)〜図12(b)、図15(c)、図17(c)、図19(b)〜図26(b)は図3のA−A線で切断した断面図、図4(a)〜図12(a)、図16(c)、図18(c)は図3のA´−A´線で切断した断面図、図13(a)〜図15(a)、図17(a)、図19(c)〜図26(c)は図3のB−B線で切断した断面図、図13(b)、図16(a)、図18(a)は図3のB´−B´線で切断した断面図、図14(b)、図15(b)、図17(b)、図19(d)〜図26(d)は図3のC−C線で切断した断面図、図16(b)、図18(b)は図3のC´−C´線で切断した断面図、図15(d)、図17(d)、図19(a)〜図26(a)は図3のD−D線で切断した断面図、図16(d)、図18(d)は図3のD´−D´線で切断した断面図である。
図27は、第4実施形態に係る不揮発性半導体記憶装置の製造方法を示す断面図である。なお、図27(a)は図3のD−D線で切断した断面図、図27(b)は図3のA−A線で切断した断面図、図27(c)は図3のB−B線で切断した断面図、図27(d)は図3のC−C線で切断した断面図である。
Claims (7)
- 半導体基板と、
第1方向に延び、前記第1方向と交差する第2方向に互いに隣接するアクティブエリアに前記半導体基板を分割するトレンチと、
前記第2方向に延びる制御ゲート電極と、
前記第2方向に延び、前記制御ゲート電極のひとつに隣接するセレクトゲート電極と、
前記制御ゲート電極と前記半導体基板との間に配置された電荷蓄積層と、
前記セレクトゲート電極を含み、メモリセルのひとつとビット線との間に接続されたセレクトトランジスタと、
前記第1方向に延びるようにして前記トレンチ内に形成され、前記第2方向に隣接する電荷蓄積層間に配置されるとともに、前記セレクトゲート電極下に延びる空隙と、
前記セレクトゲート電極下に延びる空隙に隣接するようにして前記セレクトゲート電極下の前記トレンチ内に設けられた埋め込み絶縁膜とを備えることを特徴とする不揮発性半導体記憶装置。 - 前記制御ゲート電極のゲート長をL、前記トレンチ上の電極間絶縁膜の下面から前記電荷蓄積層上の前記電極間絶縁膜の上面までの高さをXとすると、前記トレンチ上の前記電極間絶縁膜の上面から見た時の前記空隙の深さDは、X+L/2≦D<2X+Lという条件を満たすことを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記空隙は、前記電荷蓄積層の下面よりも深い位置まで至っていることを特徴とする請求項1または2に記載の不揮発性半導体記憶装置。
- 前記メモリセルから引き出されたワード線が配置されたワード線引き出し部をさらに備え、
前記ワード線引き出し部のアクティブエリアを分離するトレンチ上では前記埋め込み絶縁膜と前記電極間絶縁膜が接していることを特徴とする請求項1から3のいずれか1項に記載の不揮発性半導体記憶装置。 - ビットコンタクトが形成されるビットコンタクト部をさらに備え、
前記ビットコンタクト部のアクティブエリアを分離するトレンチ内に形成された空隙を埋め戻す埋め戻し絶縁膜をさらに備えることを特徴とする請求項1から4のいずれか1項に記載の不揮発性半導体記憶装置。 - 半導体基板上にトンネル絶縁膜を介して浮遊ゲート電極材を成膜する工程と、
前記浮遊ゲート電極材および前記トンネル絶縁膜を介して前記半導体基板にトレンチをビット線方向に形成する工程と、
前記トレンチ内に埋め込み絶縁膜を形成する工程と、
前記埋め込み絶縁膜および前記浮遊ゲート電極材上に電極間絶縁膜を形成する工程と、
前記電極間絶縁膜上に制御ゲート電極材を成膜する工程と、
前記制御ゲート電極材、前記電極間絶縁膜および前記浮遊ゲート電極材をパターニングすることにより、メモリセルごとに分離された浮遊ゲート電極を形成するとともに、前記浮遊ゲート電極上に配置された制御ゲート電極をワード線方向に形成する工程と、
前記トレンチ内に埋め込まれた埋め込み絶縁膜の少なくとも一部を除去することで、前記ワード線下に潜るようにして前記トレンチに沿って配置された空隙を、前記ワード線方向に隣接する前記電荷蓄積層間に形成する工程とを備え、
前記トレンチ内に埋め込まれた埋め込み絶縁膜の少なくとも一部を除去する時に、前記メモリセルから引き出されたワード線が配置されるワード線引き出し部をレジストで覆うことを特徴とする不揮発性半導体記憶装置の製造方法。 - 半導体基板上にトンネル絶縁膜を介して浮遊ゲート電極材を成膜する工程と、
前記浮遊ゲート電極材および前記トンネル絶縁膜を介して前記半導体基板にトレンチをビット線方向に形成する工程と、
前記トレンチ内に埋め込み絶縁膜を形成する工程と、
前記埋め込み絶縁膜および前記浮遊ゲート電極材上に電極間絶縁膜を形成する工程と、
前記電極間絶縁膜上に制御ゲート電極材を成膜する工程と、
前記制御ゲート電極材、前記電極間絶縁膜および前記浮遊ゲート電極材をパターニングすることにより、メモリセルごとに分離された浮遊ゲート電極を形成するとともに、前記浮遊ゲート電極上に配置された制御ゲート電極をワード線方向に形成する工程と、
前記トレンチ内に埋め込まれた埋め込み絶縁膜の少なくとも一部を除去することで、前記ワード線下に潜るようにして前記トレンチに沿って配置された空隙を、前記ワード線方向に隣接する前記電荷蓄積層間に形成する工程と、
前記トレンチ内に埋め込まれた埋め込み絶縁膜の少なくとも一部を除去した後、ビットコンタクトが形成されるビットコンタクト部のアクティブエリアを分離するトレンチ内に形成された空隙を埋め戻し絶縁膜にて埋め戻す工程とを備えることを特徴とする不揮発性半導体記憶装置の製造方法。
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US13/237,425 US9293547B2 (en) | 2010-11-18 | 2011-09-20 | NAND EEPROM with perpendicular sets of air gaps and method for manufacturing NAND EEPROM with perpendicular sets of air gaps |
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