JP4956500B2 - 半導体記憶装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 76
- 238000004519 manufacturing process Methods 0.000 title claims description 11
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- 229920001709 polysilazane Polymers 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 46
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- 238000005530 etching Methods 0.000 claims description 23
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- 229910052581 Si3N4 Inorganic materials 0.000 description 32
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
- 229910052814 silicon oxide Inorganic materials 0.000 description 19
- 238000001039 wet etching Methods 0.000 description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 230000003071 parasitic effect Effects 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
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- 230000008878 coupling Effects 0.000 description 7
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
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- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- MFHHXXRRFHXQJZ-UHFFFAOYSA-N NONON Chemical compound NONON MFHHXXRRFHXQJZ-UHFFFAOYSA-N 0.000 description 4
- 239000005001 laminate film Substances 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
第1及び第2の実施形態ではPSZ膜111、211が全て除去され空洞部109、209が形成される例を述べた。しかし、ウェットエッチングの選択比の関係から、図22(a)、(b)に示すようにPSZ膜111、211が空洞部109、209の底部に一部残存することも起こり得る。例えばインターポリ絶縁膜105、205にウェットエッチングにおけるダメージが入らないように、エッチング時間を短くした場合等である。
102 不純物拡散層
103 トンネル絶縁膜
104 浮遊ゲート電極
105 インターポリ絶縁膜
106 制御ゲート電極
107 素子分離領域
108 絶縁膜
109 空洞部
113 層間絶縁膜
Claims (8)
- 半導体基板と、
前記半導体基板上に第1の方向に沿って所定間隔を空けて形成された複数のトンネル絶縁膜と、
それぞれ前記複数のトンネル絶縁膜上に形成された複数の電荷蓄積層と、
前記トンネル絶縁膜間の前記半導体基板表面部に前記第1の方向に直交する第2の方向に沿って形成され、絶縁膜と、前記絶縁膜上に形成され上面が前記電荷蓄積層の上面より低く、かつ前記トンネル絶縁膜の上面より高く、底面が前記トンネル絶縁膜の下面より低い空洞部と、を有する素子分離領域と、
前記電荷蓄積層の上面及び側面と、前記空洞部を覆い、前記第1の方向に沿って帯状に形成され、前記素子分離領域と接するインターポリ絶縁膜と、
前記インターポリ絶縁膜上に形成された制御ゲート電極と、
を備えることを特徴とする半導体記憶装置。 - 半導体基板と、
前記半導体基板上に第1の方向に沿って所定間隔を空けて形成された複数のトンネル絶縁膜と、
それぞれ前記複数のトンネル絶縁膜上に形成された複数の電荷蓄積層と、
前記トンネル絶縁膜間の前記半導体基板表面部に前記第1の方向に直交する第2の方向に沿って設けられた溝の底面及び側面と、前記電荷蓄積層の側面とに形成され、空洞部を含む絶縁膜を有する素子分離領域と、
前記電荷蓄積層の上面及び側面と、前記素子分離領域の上面とを覆い、前記第1の方向に沿って帯状に形成され、前記絶縁膜に接するインターポリ絶縁膜と、
前記インターポリ絶縁膜上に形成された制御ゲート電極と、
を備え、
前記空洞部の上面は前記電荷蓄積層の上面より低く前記トンネル絶縁膜の上面より高く、前記空洞部の底面は前記トンネル絶縁膜の下面よりも低いことを特徴とする半導体記憶装置。 - 前記素子分離領域の上面は前記トンネル絶縁膜の上面より高いことを特徴とする請求項1に記載の半導体記憶装置。
- 前記空洞部の底部にポリシラザン膜をさらに備えることを特徴とする請求項1乃至3のいずれかに記載の半導体記憶装置。
- 隣接する電荷蓄積層間に前記第2の方向に沿って設けられた層間絶縁膜をさらに備え、
前記層間絶縁膜と前記半導体基板との間に空隙が形成されていることを特徴とする請求項1乃至4のいずれかに記載の半導体記憶装置。 - 前記第2の方向において、前記トンネル絶縁膜を挟むように前記半導体基板の表面部分に不純物拡散層が形成され、
前記トンネル絶縁膜、前記電荷蓄積層、前記インターポリ絶縁膜及び前記制御ゲート電極を有するメモリセルトランジスタが前記不純物拡散層を共有するように配置されていることを特徴とする請求項1乃至5のいずれかに記載の半導体記憶装置。 - 半導体基板上に第1の絶縁膜を形成し、
前記第1の絶縁膜上に電荷蓄積層となる第1の電極層を形成し、
所定間隔を空けて第1の方向に沿って前記第1の電極層、前記トンネル絶縁膜及び前記半導体基板をエッチングして複数の第1の溝を形成し、
前記第1の溝内に上面が前記トンネル絶縁膜の上面より高く、かつ前記第1の電極層の上面より低くなるように第2の絶縁膜を埋め込み、
前記第1の溝内の前記絶縁膜上に、上面が前記第1の電極層の上面より低く、下面が前記トンネル絶縁膜よりも低くなるように犠牲膜を形成し、
前記第1の電極層の上面及び側面と、前記犠牲膜の上面とを覆うように第3の絶縁膜を形成し、
前記第3の絶縁膜上に制御ゲート電極となる第2の電極層を形成し、
所定間隔を空けて前記第1の方向に直交する第2の方向に沿って複数のワードラインを加工して前記半導体基板及び前記犠牲膜の表面を露出し、
前記犠牲膜の少なくとも一部を除去することにより空洞部を形成し、
前記ワードライン間に第4の絶縁膜を形成することを特徴とする半導体記憶装置の製造方法。 - 半導体基板上に第1の絶縁膜を形成し、
前記第1の絶縁膜上に電荷蓄積層となる第1の電極層を形成し、
所定間隔を空けて第1の方向に沿って前記第1の電極層、前記トンネル絶縁膜及び前記半導体基板をエッチングして複数の第1の溝を形成し、
前記第1の溝の側壁部及び底部に、内壁の底部が前記トンネル絶縁膜の下面よりも低いU字型の第2の絶縁膜を形成し、
前記U字型の内壁部に犠牲膜を形成し、
前記第1の電極層の上面、側面、前記第2の絶縁膜の上面、及び前記犠牲膜の上面を覆うように第3の絶縁膜を形成し、
前記第3の絶縁膜上に制御ゲート電極となる第2の電極層を形成し、
所定間隔を空けて前記第1の方向に直交する第2の方向に沿って複数のワードラインを加工して前記半導体基板及び前記犠牲膜の表面を露出し、
前記犠牲膜の少なくとも一部を除去することにより空洞部を形成し、
前記ワードライン間に第4の絶縁膜を形成することを特徴とする半導体記憶装置の製造方法。
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JP2008188916A JP4956500B2 (ja) | 2008-07-22 | 2008-07-22 | 半導体記憶装置及びその製造方法 |
US12/506,566 US8022464B2 (en) | 2008-07-22 | 2009-07-21 | Semiconductor memory device and manufacturing method thereof |
US13/211,394 US8158479B2 (en) | 2008-07-22 | 2011-08-17 | Semiconductor memory device and manufacturing method thereof |
US13/412,802 US8581325B2 (en) | 2008-07-22 | 2012-03-06 | Semiconductor memory device and manufacturing method thereof |
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