JP5568573B2 - メモリデバイス内の漏洩電流の低減 - Google Patents

メモリデバイス内の漏洩電流の低減 Download PDF

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Publication number
JP5568573B2
JP5568573B2 JP2011548404A JP2011548404A JP5568573B2 JP 5568573 B2 JP5568573 B2 JP 5568573B2 JP 2011548404 A JP2011548404 A JP 2011548404A JP 2011548404 A JP2011548404 A JP 2011548404A JP 5568573 B2 JP5568573 B2 JP 5568573B2
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Japan
Prior art keywords
sleep mode
logic gate
memory device
memory
precharge
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Japanese (ja)
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JP2012517069A (ja
Inventor
ナン・チェン
メディ・ハミディ・サニ
リツ・チャバ
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2011548404A 2009-02-02 2010-02-02 メモリデバイス内の漏洩電流の低減 Active JP5568573B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/364,105 2009-02-02
US12/364,105 US9916904B2 (en) 2009-02-02 2009-02-02 Reducing leakage current in a memory device
PCT/US2010/022896 WO2010088674A1 (en) 2009-02-02 2010-02-02 Reducing leakage current in a memory device

Publications (2)

Publication Number Publication Date
JP2012517069A JP2012517069A (ja) 2012-07-26
JP5568573B2 true JP5568573B2 (ja) 2014-08-06

Family

ID=42060591

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011548404A Active JP5568573B2 (ja) 2009-02-02 2010-02-02 メモリデバイス内の漏洩電流の低減

Country Status (8)

Country Link
US (1) US9916904B2 (zh)
EP (2) EP2392011A1 (zh)
JP (1) JP5568573B2 (zh)
KR (2) KR101470945B1 (zh)
CN (1) CN102292777B (zh)
BR (1) BRPI1007326A2 (zh)
TW (1) TW201042652A (zh)
WO (1) WO2010088674A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9865330B2 (en) * 2010-11-04 2018-01-09 Qualcomm Incorporated Stable SRAM bitcell design utilizing independent gate FinFET
JP5645708B2 (ja) * 2011-02-24 2014-12-24 株式会社日立製作所 半導体装置
KR102046483B1 (ko) 2013-08-07 2019-11-21 삼성디스플레이 주식회사 게이트 구동 회로 및 이를 구비한 표시 장치
US9087579B1 (en) * 2014-01-06 2015-07-21 Qualcomm Incorporated Sense amplifiers employing control circuitry for decoupling resistive memory sense inputs during state sensing to prevent current back injection, and related methods and systems
US9685224B2 (en) * 2014-10-17 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Memory with bit line control
EP3384422B1 (en) * 2015-12-02 2021-02-24 Cryptography Research, Inc. Freeze logic
CN114003079B (zh) * 2020-07-28 2023-08-08 瑞昱半导体股份有限公司 应用在多个电源域的电路
KR102397611B1 (ko) 2021-12-07 2022-05-16 김홍섭 압전소자를 적용한 소형 풍력 발전 및 모니터링 시스템

Family Cites Families (27)

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Publication number Priority date Publication date Assignee Title
US5184202A (en) * 1983-07-27 1993-02-02 Hitachi, Ltd. Semiconductor integrated circuit device
JPH073862B2 (ja) * 1983-07-27 1995-01-18 株式会社日立製作所 半導体記憶装置
JPS61258395A (ja) 1985-05-13 1986-11-15 Hitachi Vlsi Eng Corp 半導体記憶装置
JPH0668916B2 (ja) 1985-07-18 1994-08-31 日本電信電話株式会社 信号検出回路
JPH06295581A (ja) 1993-04-06 1994-10-21 Hitachi Ltd 複合型半導体メモリモジュール
KR0166505B1 (ko) * 1995-08-18 1999-02-01 김주용 분리된 다수의 내부 전원전압을 사용하는 디램 및 감지증폭기 어레이
JPH1116384A (ja) 1997-06-26 1999-01-22 Fujitsu Ltd 半導体集積回路
JPH11219589A (ja) 1998-02-03 1999-08-10 Mitsubishi Electric Corp スタティック型半導体記憶装置
JP2000285676A (ja) 1999-03-26 2000-10-13 Fujitsu Ltd オーバードライブ方式のセンスアンプを有するメモリデバイス
JP3709302B2 (ja) 1999-05-31 2005-10-26 株式会社日立製作所 半導体記憶装置及びそれを用いたセンサ
JP4707244B2 (ja) * 2000-03-30 2011-06-22 ルネサスエレクトロニクス株式会社 半導体記憶装置および半導体装置
JP2002100190A (ja) 2000-09-26 2002-04-05 Nippon Telegr & Teleph Corp <Ntt> メモリ回路
US6549450B1 (en) 2000-11-08 2003-04-15 Ibm Corporation Method and system for improving the performance on SOI memory arrays in an SRAM architecture system
JP2004259362A (ja) 2003-02-26 2004-09-16 Renesas Technology Corp 半導体記憶装置
JP2004355760A (ja) 2003-05-30 2004-12-16 Renesas Technology Corp データ記憶回路
US7248522B2 (en) 2003-09-04 2007-07-24 United Memories, Inc. Sense amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM)
US6925025B2 (en) * 2003-11-05 2005-08-02 Texas Instruments Incorporated SRAM device and a method of powering-down the same
US6922370B2 (en) * 2003-12-11 2005-07-26 Texas Instruments Incorporated High performance SRAM device and method of powering-down the same
US7042779B2 (en) * 2004-01-23 2006-05-09 Agere Systems Inc. Method and apparatus for reducing leakage current in a read only memory device using pre-charged sub-arrays
CN1914690A (zh) 2004-01-28 2007-02-14 皇家飞利浦电子股份有限公司 具有rom矩阵的集成电路器件
KR100546415B1 (ko) 2004-06-25 2006-01-26 삼성전자주식회사 메모리 장치의 파워 노이즈를 방지하는 직렬 웨이크 업 회로
KR100567528B1 (ko) * 2004-12-30 2006-04-03 주식회사 하이닉스반도체 슈도 에스램의 프리차지 제어 회로
JP2006216184A (ja) 2005-02-04 2006-08-17 Oki Electric Ind Co Ltd 半導体記憶装置
US7372746B2 (en) 2005-08-17 2008-05-13 Micron Technology, Inc. Low voltage sensing scheme having reduced active power down standby current
US7492648B2 (en) 2006-03-24 2009-02-17 Infineon Technologies Ag Reducing leakage current in memory device using bitline isolation
US7289373B1 (en) 2006-06-06 2007-10-30 Arm Limited High performance memory device
US20080285367A1 (en) * 2007-05-18 2008-11-20 Chang Ho Jung Method and apparatus for reducing leakage current in memory arrays

Also Published As

Publication number Publication date
CN102292777B (zh) 2014-12-24
BRPI1007326A2 (pt) 2018-03-27
KR20140047152A (ko) 2014-04-21
US9916904B2 (en) 2018-03-13
US20100195366A1 (en) 2010-08-05
EP2392011A1 (en) 2011-12-07
WO2010088674A1 (en) 2010-08-05
KR101470945B1 (ko) 2014-12-09
TW201042652A (en) 2010-12-01
JP2012517069A (ja) 2012-07-26
CN102292777A (zh) 2011-12-21
EP3193336A1 (en) 2017-07-19
KR20110122720A (ko) 2011-11-10

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