JP5645708B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5645708B2 JP5645708B2 JP2011037776A JP2011037776A JP5645708B2 JP 5645708 B2 JP5645708 B2 JP 5645708B2 JP 2011037776 A JP2011037776 A JP 2011037776A JP 2011037776 A JP2011037776 A JP 2011037776A JP 5645708 B2 JP5645708 B2 JP 5645708B2
- Authority
- JP
- Japan
- Prior art keywords
- power
- memory array
- power supply
- peripheral circuit
- switch group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
Claims (2)
- SRAMのメモリセルが複数配置されているメモリアレイと、
前記メモリアレイへのデータの書き込みおよび前記メモリアレイからのデータの読み出しを行う第1の周辺回路と、
前記メモリアレイおよび前記第1の周辺回路と電源線との接続を遮断する第1および第2のスイッチ群とを含むレイアウトの単位がその内部に複数配置されており、
前記レイアウトの単位の繰り返しの配置延在方向は前記メモリアレイ中のビット線の配線方向であり、
前記メモリアレイ中の前記ビット線が複数本で繰り返し単位となっており、その繰り返し単位ごとに前記スイッチ群が配置されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記レイアウトの単位の前記ビット線の配線の方向の一端に前記第1のスイッチ群が配置され、かつ、その他端に前記第2のスイッチ群が配置されていることを特徴とする半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011037776A JP5645708B2 (ja) | 2011-02-24 | 2011-02-24 | 半導体装置 |
US13/349,447 US8638593B2 (en) | 2011-02-24 | 2012-01-12 | Semiconductor device |
KR1020120004294A KR101311084B1 (ko) | 2011-02-24 | 2012-01-13 | 반도체 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011037776A JP5645708B2 (ja) | 2011-02-24 | 2011-02-24 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012175012A JP2012175012A (ja) | 2012-09-10 |
JP5645708B2 true JP5645708B2 (ja) | 2014-12-24 |
Family
ID=46718904
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011037776A Expired - Fee Related JP5645708B2 (ja) | 2011-02-24 | 2011-02-24 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8638593B2 (ja) |
JP (1) | JP5645708B2 (ja) |
KR (1) | KR101311084B1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6244842B2 (ja) * | 2013-11-14 | 2017-12-13 | 富士通株式会社 | 半導体集積回路の製造方法 |
JP2016092536A (ja) * | 2014-10-31 | 2016-05-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2016162303A (ja) * | 2015-03-03 | 2016-09-05 | 株式会社東芝 | 無線通信装置 |
CN107077885B (zh) | 2015-03-31 | 2021-03-12 | 瑞萨电子株式会社 | 半导体器件 |
US10163494B1 (en) * | 2017-05-31 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device and fabrication method thereof |
JP2018060592A (ja) * | 2017-12-25 | 2018-04-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10564692B2 (en) | 2018-03-27 | 2020-02-18 | Windbond Electronics Corp. | Memory device and power reduction method of the same memory device |
JP6779960B2 (ja) * | 2018-11-07 | 2020-11-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0756885B2 (ja) * | 1988-12-27 | 1995-06-14 | 日本電気株式会社 | 半導体メモリ |
JP2717738B2 (ja) * | 1991-06-20 | 1998-02-25 | 三菱電機株式会社 | 半導体記憶装置 |
JPH05259832A (ja) * | 1992-01-13 | 1993-10-08 | Hitachi Ltd | ホールド型ラッチ回路、及び半導体記憶装置 |
JP2001101893A (ja) | 1999-09-29 | 2001-04-13 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
JP2002368135A (ja) * | 2001-06-12 | 2002-12-20 | Hitachi Ltd | 半導体記憶装置 |
JP2003132683A (ja) * | 2001-10-23 | 2003-05-09 | Hitachi Ltd | 半導体装置 |
US7673119B2 (en) * | 2005-05-13 | 2010-03-02 | Texas Instruments Incorporated | VLIW optional fetch packet header extends instruction set space |
JP4936749B2 (ja) | 2006-03-13 | 2012-05-23 | 株式会社東芝 | 半導体記憶装置 |
JP2008047190A (ja) | 2006-08-11 | 2008-02-28 | Toshiba Corp | 半導体装置 |
US7512030B2 (en) * | 2006-08-29 | 2009-03-31 | Texas Instruments Incorporated | Memory with low power mode for WRITE |
US8213511B2 (en) * | 2007-04-30 | 2012-07-03 | Texas Instruments Incorporated | Video encoder software architecture for VLIW cores incorporating inter prediction and intra prediction |
JP2010140563A (ja) | 2008-12-12 | 2010-06-24 | Toshiba Corp | 半導体集積回路 |
US9916904B2 (en) * | 2009-02-02 | 2018-03-13 | Qualcomm Incorporated | Reducing leakage current in a memory device |
JP5317900B2 (ja) * | 2009-09-14 | 2013-10-16 | ルネサスエレクトロニクス株式会社 | 半導体集積回路およびその動作方法 |
JP2010282721A (ja) | 2010-08-09 | 2010-12-16 | Renesas Electronics Corp | 半導体装置 |
-
2011
- 2011-02-24 JP JP2011037776A patent/JP5645708B2/ja not_active Expired - Fee Related
-
2012
- 2012-01-12 US US13/349,447 patent/US8638593B2/en not_active Expired - Fee Related
- 2012-01-13 KR KR1020120004294A patent/KR101311084B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US8638593B2 (en) | 2014-01-28 |
KR101311084B1 (ko) | 2013-09-25 |
KR20120097317A (ko) | 2012-09-03 |
US20120218812A1 (en) | 2012-08-30 |
JP2012175012A (ja) | 2012-09-10 |
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