JP5383049B2 - 垂直方向のチャンネルを有するアクセス素子、これを含む半導体装置、及びアクセス素子の形成方法 - Google Patents
垂直方向のチャンネルを有するアクセス素子、これを含む半導体装置、及びアクセス素子の形成方法 Download PDFInfo
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Description
102 垂直ピラー
106 ゲート絶縁パターン
130 下部ソース/ドレイン領域
140 上部ソース/ドレイン領域
145 コンタクトパッド
170 ビットライン
180 ワードライン
190 アクセス素子
Claims (20)
- 下部ソース/ドレイン領域と上部ソース/ドレイン領域を分離する垂直方向のチャンネルと、
前記チャンネル上に具備されるゲート絶縁パターンと、
前記ゲート絶縁パターンを横切って前記チャンネルを連結する一体型ゲート電極/連結ラインと、を含み、
前記一体型ゲート電極/連結ラインは前記ゲート絶縁パターンと隣接するように具備され、前記下部ソース/ドレイン領域の一部と少なくともオーバーレイ(overlay)されるディセンディングリップ領域(descending lip portion)を含み、
埋め込みビットライン構造はオフセットステップ領域(offset step region)を含み、
前記下部ソース/ドレイン領域は、第1ソース/ドレイン領域及び第2ソース/ドレイン領域を含むマルチレベルソース/ドレイン領域であり、前記第1ソース/ドレイン領域は前記オフセットステップ領域の上部領域に配置され、前記第2ソース/ドレイン領域は前記オフセットステップ領域の下部領域に配置されている
ことを特徴とするアクセス素子。 - 前記絶縁膜パターンは下部側面領域を含み、前記下部側面領域は前記チャンネルから延長され、前記下部ソース/ドレイン領域から前記ディセンディングリップ領域を分離している
ことを特徴とする請求項1記載のアクセス素子。 - 前記一体型ゲート電極/連結ラインは一体型ゲート電極/ワードラインであり、前記下部ソース/ドレイン領域は埋め込みビットライン構造(buried bit line structure)内に配置されている
ことを特徴とする請求項1記載のアクセス素子。 - 前記下部ソース/ドレイン領域は第1ソース/ドレイン領域及び第2ソース/ドレインを含み、前記第1ソース/ドレインは前記チャンネルを少なくとも一部取り囲む周辺領域に配置され、前記第2ソース/ドレイン領域は前記埋め込みビットラインの長手方向に延長する側面領域に配置されている
ことを特徴とする請求項3記載のアクセス素子。 - 前記上部ソース/ドレイン領域と電気的に連結されたコンタクトパッドを更に含む
ことを特徴とする請求項4記載のアクセス素子。 - 前記チャンネルはシリコン物質の垂直ピラーを含み、前記コンタクトパッドは前記シリコン物質からエピタキシャル成長させたシリコンコンタクトパッドである
ことを特徴とする請求項5記載のアクセス素子。 - 前記一体型ゲート電極/連結ラインは一体型ゲート電極/ワードラインであり、前記下部ソース/ドレイン領域は埋め込みビットライン内に配置され、
前記一体型ゲート電極/ワードライン、前記チャンネル、前記下部ソース/ドレイン及び前記上部ソース/ドレインは、メモリセル内電界効果トランジスタ(FET)として結合され駆動する
ことを特徴とする請求項1記載のアクセス素子。 - 前記一体型ゲート電極/連結ラインは、前記チャンネルの少なくとも一部を完全に取り囲む
ことを特徴とする請求項1記載のアクセス素子。 - 基板上に隣接するように配置され、下部ソース/ドレイン領域及び上部ソース/ドレイン領域を分離する垂直方向のチャンネル及び前記チャンネル上に形成されるゲート絶縁パターンを含む第1アクセス素子及び第2アクセス素子と、
前記基板上に配置され、前記第1及び第2アクセス素子を分離する第1層間絶縁膜と、
前記第1層間絶縁膜上に具備され、前記第1及び第2アクセス素子のチャンネルを連結する一体型ゲート電極/連結ラインと、を含み、
前記一体型ゲート電極/連結ラインはディセンディングリップ領域を含み、前記ディセンディングリップ領域は前記第1又は第2アクセス素子のゲート絶縁パターンと隣接するように配置され前記第1又は第2アクセス素子の結合された前記下部ソース/ドレイン領域の少なくとも一部とオーバーレイされ、
前記下部ソース/ドレイン領域は、第1ソース/ドレイン領域及び第2ソース/ドレイン領域を含むマルチレベルソース/ドレイン領域であり、前記第1ソース/ドレイン領域は埋め込みビットライン構造が有するオフセットステップ領域の上部領域に形成され、前記第2ソース/ドレイン領域は前記オフセットステップ領域の下部領域に形成されている
ことを特徴とする半導体素子。 - 前記ゲート絶縁パターンは前記チャンネルから延長し、前記下部ソース/ドレイン領域から前記一体型ゲート電極/連結ラインのディセンディングリップ領域を分離する下部側面領域を含む
ことを特徴とする請求項9記載の半導体素子。 - 前記半導体素子は半導体メモリ素子であり、前記一体型ゲート電極/連結ラインは一体型ゲート電極/ワードラインであり、それぞれの前記下部ソース/ドレイン領域はそれぞれの埋め込みビットライン構造内に配置される
ことを特徴とする請求項9記載の半導体素子。 - それぞれの前記下部ソース/ドレイン領域は第1ソース/ドレイン領域及び第2ソース/ドレイン領域を含み、前記第1ソース/ドレイン領域は前記チャンネルを少なくとも一部取り囲む周辺領域に形成され、前記第2ソース/ドレイン領域は埋め込みビットラインの長手方向に延長される側面領域に形成されている
ことを特徴とする請求項9記載の半導体素子。 - 前記それぞれの一体型ゲート電極/連結ラインはゲート電極/ワードラインであり、それぞれの前記下部ソース/ドレインは埋め込みビットライン構造内に配置され、前記第1及び第2アクセス素子は各メモリセルの電界効果トランジスタとして動作する
ことを特徴とする請求項9記載の半導体素子。 - 前記半導体素子は、DRAM、SRAM、PRAM、NOR型フラッシュメモリ、及びNAND型フラッシュメモリで構成されたグループから選択された1つである
ことを特徴とする請求項13記載の半導体素子。 - メモリの作動を制御するために前記メモリと連結されるメモリコントローラを含み、
前記メモリはメモリセル領域を含み、前記メモリセル領域はメモリセルアレイを含み、前記アレイ内のそれぞれのメモリセルはアクセス要素及び保存要素を含み、それぞれの前記アクセス要素は、下部ソース/ドレイン領域及び上部ソース/ドレイン領域を分離する垂直方向のチャンネル、前記チャンネル上に配置されるゲート絶縁パターン及び前記ゲート絶縁パターンを横切って前記チャンネルを連結する一体型ゲート電極/ワードラインを含み、前記一体型ゲート電極/ワードラインは前記ゲート絶縁パターンと隣接するように具備され前記下部ソース/ドレイン領域に少なくとも一部オーバーレイされたディセンディングリップ領域を含み、
前記下部ソース/ドレイン領域は、第1ソース/ドレイン領域及び第2ソース/ドレイン領域を含むマルチレベルソース/ドレイン領域であり、前記第1ソース/ドレイン領域は埋め込みビットライン構造が有するオフセットステップ領域の上部領域に形成され、前記第2ソース/ドレイン領域は前記オフセットステップ領域の下部領域に形成されている
ことを特徴とするメモリシステム。 - 前記ゲート絶縁パターンは下部側面領域を含み、前記下部側面領域は前記チャンネルから延長され、前記下部ソース/ドレイン領域から前記一体型ゲート電極/ワードラインのディセンディングリップ領域を分離している
ことを特徴とする請求項15記載のメモリシステム。 - 前記下部ソース/ドレイン領域は、オフセットステップ領域を含む埋め込みビットライン構造内に配置されている
ことを特徴とする請求項15記載のメモリシステム。 - 第一層間絶縁膜上に形成された前記一体型ゲート電極/連結ラインは、
前記ゲート絶縁パターンに直接当接配置された垂直端と前記チャンネルから離間して前記下部ソース/ドレイン領域の少なくとも一部と重畳されるように前記垂直端から延伸された下部横方向端とを備える前記ディセンディングリップ領域と、前記チャンネルから離間するように前記ディセンディングリップ領域から横方向に延伸されて前記第一層間絶縁膜上に配置された平坦な横方向表面を有する横方向部分と、を備え、
前記下部ソース/ドレイン領域の上部面は、前記第一層間絶縁膜の上部面よりも低い ことを特徴とする請求項1に記載のアクセス素子。 - 第一層間絶縁膜上に形成された前記一体型ゲート電極/連結ラインは、
前記ゲート絶縁パターンに直接当接配置された垂直端と前記チャンネルから離間して前記下部ソース/ドレイン領域の少なくとも一部と重畳されるように前記垂直端から延伸された下部横方向端とを備える前記ディセンディングリップ領域と、前記チャンネルから離間するように前記ディセンディングリップ領域から横方向に延伸されて前記第一層間絶縁膜上に配置された平坦な横方向表面を有する横方向部分と、を備え、
前記下部ソース/ドレイン領域の上部面は、前記第一層間絶縁膜の上部面よりも低い
ことを特徴とする請求項9に記載の半導体素子。 - 第一層間絶縁膜上に形成された前記一体型ゲート電極/ワードラインは、
前記ゲート絶縁パターンに直接当接配置された垂直端と前記チャンネルから離間して前記下部ソース/ドレイン領域の少なくとも一部と重畳されるように前記垂直端から延伸された下部横方向端とを備える前記ディセンディングリップ領域と、前記チャンネルから離間するように前記ディセンディングリップ領域から横方向に延伸されて前記第一層間絶縁膜上に配置された平坦な横方向表面を有する横方向部分と、を備え、
前記下部ソース/ドレイン領域の上部面は、前記第一層間絶縁膜の上部面よりも低い ことを特徴とする請求項15記載のメモリシステム。
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US8058683B2 (en) | 2011-11-15 |
CN101226960A (zh) | 2008-07-23 |
US20080173936A1 (en) | 2008-07-24 |
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