JP5355380B2 - 多層配線基板 - Google Patents

多層配線基板 Download PDF

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Publication number
JP5355380B2
JP5355380B2 JP2009294435A JP2009294435A JP5355380B2 JP 5355380 B2 JP5355380 B2 JP 5355380B2 JP 2009294435 A JP2009294435 A JP 2009294435A JP 2009294435 A JP2009294435 A JP 2009294435A JP 5355380 B2 JP5355380 B2 JP 5355380B2
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JP
Japan
Prior art keywords
land
wiring
diameter side
wiring layer
size
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009294435A
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English (en)
Japanese (ja)
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JP2011134957A (ja
JP2011134957A5 (https=
Inventor
山田　　智子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009294435A priority Critical patent/JP5355380B2/ja
Priority to US12/975,703 priority patent/US8952270B2/en
Publication of JP2011134957A publication Critical patent/JP2011134957A/ja
Publication of JP2011134957A5 publication Critical patent/JP2011134957A5/ja
Application granted granted Critical
Publication of JP5355380B2 publication Critical patent/JP5355380B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0352—Differences between the conductors of different layers of a multilayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2009294435A 2009-12-25 2009-12-25 多層配線基板 Active JP5355380B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009294435A JP5355380B2 (ja) 2009-12-25 2009-12-25 多層配線基板
US12/975,703 US8952270B2 (en) 2009-12-25 2010-12-22 Multilayer wiring board having lands with tapered side surfaces

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009294435A JP5355380B2 (ja) 2009-12-25 2009-12-25 多層配線基板

Publications (3)

Publication Number Publication Date
JP2011134957A JP2011134957A (ja) 2011-07-07
JP2011134957A5 JP2011134957A5 (https=) 2012-12-13
JP5355380B2 true JP5355380B2 (ja) 2013-11-27

Family

ID=44186077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009294435A Active JP5355380B2 (ja) 2009-12-25 2009-12-25 多層配線基板

Country Status (2)

Country Link
US (1) US8952270B2 (https=)
JP (1) JP5355380B2 (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014075515A (ja) * 2012-10-05 2014-04-24 Shinko Electric Ind Co Ltd 配線基板及び配線基板の製造方法
JP2014120651A (ja) * 2012-12-18 2014-06-30 Toppan Printing Co Ltd 積層配線板及びその製造方法
JP2014127623A (ja) 2012-12-27 2014-07-07 Shinko Electric Ind Co Ltd 配線基板及び配線基板の製造方法
US9275925B2 (en) 2013-03-12 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved interconnect structure
JP2015082524A (ja) * 2013-10-21 2015-04-27 ソニー株式会社 配線基板、半導体装置
KR102472945B1 (ko) * 2015-04-23 2022-12-01 삼성전기주식회사 인쇄회로기판, 반도체 패키지 및 그 제조방법
US9659853B2 (en) 2015-04-24 2017-05-23 Advanced Semiconductor Engineering, Inc. Double side via last method for double embedded patterned substrate
JP6816964B2 (ja) 2016-03-10 2021-01-20 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP6615701B2 (ja) 2016-06-24 2019-12-04 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
KR102530322B1 (ko) * 2018-12-18 2023-05-10 삼성전자주식회사 반도체 패키지
JP7512594B2 (ja) 2020-01-10 2024-07-09 Ｔｏｐｐａｎホールディングス株式会社 回路基板
CN114080088B (zh) * 2020-08-10 2024-05-31 鹏鼎控股(深圳)股份有限公司 电路板及其制备方法
JP2022054538A (ja) 2020-09-28 2022-04-07 凸版印刷株式会社 配線基板

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5199163A (en) * 1992-06-01 1993-04-06 International Business Machines Corporation Metal transfer layers for parallel processing
JPH08116174A (ja) * 1994-08-25 1996-05-07 Matsushita Electric Ind Co Ltd 回路形成基板およびその製造方法
JP3112059B2 (ja) * 1995-07-05 2000-11-27 株式会社日立製作所 薄膜多層配線基板及びその製法
EP0948247B1 (en) * 1998-04-01 2005-08-31 Mitsui Mining & Smelting Co., Ltd. Method For Making A Multi-Layer Printed Wiring Board
US6810583B2 (en) * 2001-08-07 2004-11-02 International Business Machines Corporation Coupling of conductive vias to complex power-signal substructures
JP2003158379A (ja) 2001-11-19 2003-05-30 Kyocera Corp 多層配線基板
JP2003298240A (ja) * 2002-04-05 2003-10-17 Sohwa Corporation 多層回路基板
JP2005072328A (ja) 2003-08-26 2005-03-17 Kyocera Corp 多層配線基板
JP4551730B2 (ja) * 2004-10-15 2010-09-29 イビデン株式会社 多層コア基板及びその製造方法
JP5407667B2 (ja) * 2008-11-05 2014-02-05 株式会社村田製作所 半導体装置

Also Published As

Publication number Publication date
JP2011134957A (ja) 2011-07-07
US20110155442A1 (en) 2011-06-30
US8952270B2 (en) 2015-02-10

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