JP4551730B2 - 多層コア基板及びその製造方法 - Google Patents
多層コア基板及びその製造方法 Download PDFInfo
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Description
前記第1絶縁層の前記第1導体層側から徐々に径が小さくなりながら前記グランド層の導体部分と電気的に絶縁した状態で前記第1絶縁層、前記グランド層の非導体部分及び前記中央絶縁層を厚さ方向に貫通して前記電源層の導体部分に達するテーパ状の第1ビアホール導体と、
前記第2絶縁層の前記第2導体層側から前記第2絶縁層を厚さ方向に貫通して前記電源層の導体部分に達する第2ビアホール導体と、
前記第2絶縁層の前記第2導体層側から徐々に径が小さくなりながら前記電源層の導体部分と電気的に絶縁した状態で前記第2絶縁層、前記電源層の非導体部分及び前記中央絶縁層を厚さ方向に貫通して前記グランド層の導体部分に達するテーパ状の第3ビアホール導体と、
前記第1絶縁層の前記第1導体層側から前記第1絶縁層を厚さ方向に貫通して前記グランド層の導体部分に達する第4ビアホール導体と、
を備え、
前記第1ビアホール導体と前記第4ビアホール導体は交互に並設され、前記第2ビアホール導体と前記第3ビアホール導体も交互に並設された領域を有するものである。
(a)中央絶縁層の表裏両面にそれぞれ設けられた導体厚膜をパターン形成することにより導体部分とホール部分とを有するグランド層及び電源層とする工程と、
(b)絶縁材により前記グランド層のホール部分を充填して非導体部分を形成しつつ該絶縁材により前記グランド層の全体を覆って第1絶縁層を形成する一方、絶縁材により前記電源層のホール部分を充填して非導体部分を形成しつつ該絶縁材により前記電源層の全体を覆って第2絶縁層を形成する工程と、
(c)前記第1絶縁層の外面から徐々に径を小さくしながら前記グランド層の導体部分を露出させずに前記電源層の導体部分に達するように前記第1絶縁層、前記グランド層の非導体部分及び前記中央絶縁層をレーザを利用して貫通させることにより第1ビアホールを形成し、前記第2絶縁層の外面から前記電源層の導体部分に達するように前記第2絶縁層をレーザを利用して貫通させることにより第2ビアホールを形成し、前記第2絶縁層の外面から徐々に径を小さくしながら前記電源層の導体部分を露出させずに前記グランド層の導体部分に達するように前記第2絶縁層、前記電源層の非導体部分及び前記中央絶縁層をレーザを利用して貫通させることにより第3ビアホールを前記第2ビアホールと交互に並ぶように形成し、前記第1絶縁層の外面から前記グランド層層の導体部分に達するように前記第1絶縁層をレーザを利用して貫通させることにより第4ビアホールを前記第1ビアホールと交互に並ぶように形成する工程と、
(d)前記第1〜第4ビアホールの少なくとも内壁を導体で被覆して第1〜第4ビアホール導体とする工程と、
(e)前記第1絶縁層の外面に前記第1及び第4ビアホール導体のそれぞれと電気的に接続される第1導体層を形成すると共に前記第2絶縁層の外面に前記第2及び第3ビアホール導体のそれぞれと電気的に接続される第2導体層を形成する工程と、
を含むものである。
まず、上述した実施形態の製造方法手順に準じて、実験例1〜5の多層コア基板10を作製した。具体的には、実験例1〜5の多層コア基板10は、図14に示すように、中央絶縁層22、グランド層40及び電源層42の厚さが100μm、第1及び第3ビアホール導体51,53の高さが230μm、第1及び第2絶縁層24,26の厚さが30μm、第2及び第4ビアホール導体52,54の高さが30μm、第1ビアホール導体51と第4ビアホール導体54とのビアホール間ピッチP及び第2ビアホール導体52と第3ビアホール導体53とのビアホール間ピッチPが175μmとなるようにし、グランド層40の導体部分40aと非導体部分40bの寸法及び電源層42の導体部分42aと非導体部分42bの寸法は共通とし、第1及び第3ビアホール導体51,53のボトム径d1,d3を表1に示す値を持つものとした。
まず、上述した実施形態の製造方法手順に準じて、実験例6〜14の多層コア基板10を作製した。具体的には、実験例6〜14の多層コア基板10は、図14に示すように、中央絶縁層22、グランド層40及び電源層42の厚さが100μm、第1ビアホール導体51及び第3ビアホール導体53の高さが230μm、第1及び第2絶縁層24,26の厚さが30μm、第2及び第4ビアホール導体52,54の高さが30μmとなるようにし、グランド層40の導体部分40aの寸法及び電源層42の導体部分42aの寸法は共通とし、第1ビアホール導体51と第4ビアホール導体54とのビアホール間ピッチP及び第2ビアホール導体52と第3ビアホール導体53とのビアホール間ピッチPや第1及び第3ビアホール導体51,53のボトム径d1,d3を表1に示す値を持つものとした。なお、第1ビアホール導体51とグランド層40の導体部分40aとのクリアランス及び第3ビアホール導体53と電源層42の導体部分42aとのクリアランスは、少なくとも15μmは必要なため、ここでは20μmに統一した。
Claims (7)
- 中央絶縁層の表裏両面にそれぞれ導体部分と非導体部分とを有するグランド層及び電源層が設けられ、前記グランド層と該グランド層に対向して配置された第1導体層との間に第1絶縁層が設けられ、前記電源層と該電源層に対向して配置された第2導体層との間に第2絶縁層が設けられた多層コア基板であって、
前記第1絶縁層の前記第1導体層側から徐々に径が小さくなりながら前記グランド層の導体部分と電気的に絶縁した状態で前記第1絶縁層、前記グランド層の非導体部分及び前記中央絶縁層を厚さ方向に貫通して前記電源層の導体部分に達するテーパ状の第1ビアホール導体と、
前記第2絶縁層の前記第2導体層側から前記第2絶縁層を厚さ方向に貫通して前記電源層の導体部分に達する第2ビアホール導体と、
前記第2絶縁層の前記第2導体層側から徐々に径が小さくなりながら前記電源層の導体部分と電気的に絶縁した状態で前記第2絶縁層、前記電源層の非導体部分及び前記中央絶縁層を厚さ方向に貫通して前記グランド層の導体部分に達するテーパ状の第3ビアホール導体と、
前記第1絶縁層の前記第1導体層側から前記第1絶縁層を厚さ方向に貫通して前記グランド層の導体部分に達する第4ビアホール導体と、
を備え、
前記第1ビアホール導体と前記第4ビアホール導体とが交互に並設されると共に前記第2ビアホール導体と前記第3ビアホール導体とが交互に並設された領域を有し、
前記グランド層の導体部分のうち前記第1ビアホール導体と対向する面は、前記第1ビアホール導体と略同じテーパ角をもつテーパ面であり、前記電源層の導体部分のうち前記第3ビアホール導体と対向する面は、前記第3ビアホール導体と略同じテーパ角をもつテーパ面である、
多層コア基板。 - 前記第1導体層及び前記第2導体層のいずれか一方は、フリップチップ実装されるICチップの複数の電源端子及びグランド端子に対向する位置に設けられたパッド群を含んでなる、請求項1に記載の多層コア基板。
- 前記第1ビアホール導体及び前記第3ビアホール導体は、小径のボトム径dと大径のトップ径Dとの比d/Dが0.1≦d/D≦0.9となるように設計されている、請求項1又は2に記載の多層コア基板。
- 前記グランド層及び前記電源層は、前記第1導体層及び前記第2導体層に比べて厚く形成されている、請求項1〜3のいずれかに記載の多層コア基板。
- 前記第1〜第4ビアホール導体のビアホールは、レーザ加工によって形成されている、請求項1〜4のいずれかに記載の多層コア基板。
- 前記グランド層の導体部分のうち前記第1ビアホール導体と対向する面及び前記第1ビアホール導体のうち前記グランド層の導体部分に対向する面の少なくとも一方に凹凸が形成され、前記電源層の導体部分のうち前記第3ビアホール導体と対向する面及び前記第3ビアホール導体のうち前記電源層の導体部分に対向する面の少なくとも一方に凹凸が形成されている、請求項1〜5のいずれかに記載の多層コア基板。
- (a)中央絶縁層の表裏両面にそれぞれ設けられた導体厚膜をパターン形成することにより導体部分とホール部分とを有するグランド層及び電源層とする工程と、
(b)絶縁材により前記グランド層のホール部分を充填して非導体部分を形成しつつ該絶縁材により前記グランド層の全体を覆って第1絶縁層を形成する一方、絶縁材により前記電源層のホール部分を充填して非導体部分を形成しつつ該絶縁材により前記電源層の全体を覆って第2絶縁層を形成する工程と、
(c)前記第1絶縁層の外面から徐々に径を小さくしながら前記グランド層の導体部分を露出させずに前記電源層の導体部分に達するように前記第1絶縁層、前記グランド層の非導体部分及び前記中央絶縁層をレーザを利用して貫通させることにより第1ビアホールを形成し、前記第2絶縁層の外面から前記電源層の導体部分に達するように前記第2絶縁層をレーザを利用して貫通させることにより第2ビアホールを形成し、前記第2絶縁層の外面から徐々に径を小さくしながら前記電源層の導体部分を露出させずに前記グランド層の導体部分に達するように前記第2絶縁層、前記電源層の非導体部分及び前記中央絶縁層をレーザを利用して貫通させることにより第3ビアホールを前記第2ビアホールと交互に並ぶように形成し、前記第1絶縁層の外面から前記グランド層層の導体部分に達するように前記第1絶縁層をレーザを利用して貫通させることにより第4ビアホールを前記第1ビアホールと交互に並ぶように形成する工程と、
(d)前記第1〜第4ビアホールの少なくとも内壁を導体で被覆して第1〜第4ビアホール導体とする工程と、
(e)前記第1絶縁層の外面に前記第1及び第4ビアホール導体のそれぞれと電気的に接続される第1導体層を形成すると共に前記第2絶縁層の外面に前記第2及び第3ビアホール導体のそれぞれと電気的に接続される第2導体層を形成する工程と、
を含み、
前記工程(a)では、前記グランド層のホール部分のうち前記第1ビアホール導体と対向する面を、前記第1ビアホール導体と略同じテーパ角をもつテーパ面となるように形成し、前記電源層のホール部分のうち前記第3ビアホール導体と対向する面を、前記第3ビアホール導体と略同じテーパ角をもつテーパ面となるように形成する、
多層コア基板の製造方法。
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US6972382B2 (en) * | 2003-07-24 | 2005-12-06 | Motorola, Inc. | Inverted microvia structure and method of manufacture |
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2004
- 2004-10-15 JP JP2004301385A patent/JP4551730B2/ja not_active Expired - Fee Related
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2005
- 2005-10-11 US US11/246,157 patent/US7378602B2/en active Active
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2007
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JPS61114596A (ja) * | 1984-11-09 | 1986-06-02 | 日本電気株式会社 | 多層プリント配線板 |
JPH04340795A (ja) * | 1991-05-17 | 1992-11-27 | Mitsubishi Electric Corp | プリント配線板 |
JP2004006971A (ja) * | 1994-08-25 | 2004-01-08 | Matsushita Electric Ind Co Ltd | 回路形成基板 |
JP2000068648A (ja) * | 1998-08-19 | 2000-03-03 | Hitachi Aic Inc | 多層印刷配線基板の製造方法 |
US6548767B1 (en) * | 1999-12-16 | 2003-04-15 | Lg Electronics, Inc. | Multi-layer printed circuit board having via holes formed from both sides thereof |
JP2002026519A (ja) * | 2000-07-05 | 2002-01-25 | Furukawa Electric Co Ltd:The | プリント回路基板及びその製造方法 |
JP2003332752A (ja) * | 2002-05-14 | 2003-11-21 | Shinko Electric Ind Co Ltd | メタルコア基板およびその製造方法 |
Also Published As
Publication number | Publication date |
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US7378602B2 (en) | 2008-05-27 |
US20070271783A1 (en) | 2007-11-29 |
US20060083895A1 (en) | 2006-04-20 |
JP2006114741A (ja) | 2006-04-27 |
US7905014B2 (en) | 2011-03-15 |
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