JP5202248B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP5202248B2 JP5202248B2 JP2008300972A JP2008300972A JP5202248B2 JP 5202248 B2 JP5202248 B2 JP 5202248B2 JP 2008300972 A JP2008300972 A JP 2008300972A JP 2008300972 A JP2008300972 A JP 2008300972A JP 5202248 B2 JP5202248 B2 JP 5202248B2
- Authority
- JP
- Japan
- Prior art keywords
- word line
- voltage
- memory device
- semiconductor memory
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 53
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 13
- 239000003990 capacitor Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 102100031102 C-C motif chemokine 4 Human genes 0.000 description 3
- 102100026620 E3 ubiquitin ligase TRAF3IP2 Human genes 0.000 description 3
- 101710140859 E3 ubiquitin ligase TRAF3IP2 Proteins 0.000 description 3
- 101000777470 Mus musculus C-C motif chemokine 4 Proteins 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008300972A JP5202248B2 (ja) | 2008-11-26 | 2008-11-26 | 半導体記憶装置 |
PCT/JP2009/000756 WO2010061489A1 (ja) | 2008-11-26 | 2009-02-23 | 半導体記憶装置 |
CN2009801457011A CN102216996A (zh) | 2008-11-26 | 2009-02-23 | 半导体存储装置 |
US13/100,939 US8345506B2 (en) | 2008-11-26 | 2011-05-04 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008300972A JP5202248B2 (ja) | 2008-11-26 | 2008-11-26 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010129113A JP2010129113A (ja) | 2010-06-10 |
JP5202248B2 true JP5202248B2 (ja) | 2013-06-05 |
Family
ID=42225381
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008300972A Expired - Fee Related JP5202248B2 (ja) | 2008-11-26 | 2008-11-26 | 半導体記憶装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8345506B2 (zh) |
JP (1) | JP5202248B2 (zh) |
CN (1) | CN102216996A (zh) |
WO (1) | WO2010061489A1 (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9570133B2 (en) | 2009-12-17 | 2017-02-14 | Macronix International Co., Ltd. | Local word line driver |
KR20120093507A (ko) | 2011-02-15 | 2012-08-23 | 삼성전자주식회사 | 효율적인 전력 공급을 위한 반도체 장치 |
JP5837311B2 (ja) * | 2011-03-01 | 2015-12-24 | ローム株式会社 | ドライバ及び半導体記憶装置 |
CN103943136B (zh) * | 2013-01-17 | 2017-09-08 | 旺宏电子股份有限公司 | 一种存储器电路及其操作方法 |
US10127991B2 (en) * | 2016-08-17 | 2018-11-13 | Intel Corporation | Three dimensional memory device with access signal triggering from voltage pump output levels |
JP6952619B2 (ja) | 2018-02-21 | 2021-10-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN108336988B (zh) * | 2018-03-07 | 2022-01-25 | 中科德诺微电子(深圳)有限公司 | 一种mos开关的负压驱动电路 |
US10586600B1 (en) * | 2019-01-28 | 2020-03-10 | Micron Technology, Inc. | High-voltage shifter with reduced transistor degradation |
KR20210076726A (ko) * | 2019-12-16 | 2021-06-24 | 에스케이하이닉스 주식회사 | 메모리 장치 및 이의 동작 방법 |
US20230091623A1 (en) * | 2021-09-23 | 2023-03-23 | Nanya Technology Corporation | Defect inspecting method and system performing the same |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5202855A (en) | 1991-01-14 | 1993-04-13 | Motorola, Inc. | DRAM with a controlled boosted voltage level shifting driver |
KR940002859B1 (ko) | 1991-03-14 | 1994-04-04 | 삼성전자 주식회사 | 반도체 메모리장치에서의 워드라인 구동회로 |
JPH0762954B2 (ja) | 1991-05-31 | 1995-07-05 | インターナショナル・ビジネス・マシーンズ・コーポレイション | ワ−ド線選択・駆動回路 |
KR960006373B1 (ko) | 1992-10-31 | 1996-05-15 | 삼성전자주식회사 | 반도체 메모리 장치의 워드라인 구동회로 |
JP3306682B2 (ja) | 1993-08-18 | 2002-07-24 | 日本テキサス・インスツルメンツ株式会社 | 駆動回路 |
JPH07114793A (ja) * | 1993-08-26 | 1995-05-02 | Nec Corp | 半導体記憶装置 |
JP3667787B2 (ja) | 1994-05-11 | 2005-07-06 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
JPH0863964A (ja) * | 1994-08-29 | 1996-03-08 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP3162591B2 (ja) * | 1994-12-09 | 2001-05-08 | 株式会社東芝 | 半導体集積回路 |
US5696721A (en) * | 1995-05-05 | 1997-12-09 | Texas Instruments Incorporated | Dynamic random access memory having row decoder with level translator for driving a word line voltage above and below an operating supply voltage range |
US5696712A (en) * | 1995-07-05 | 1997-12-09 | Sun Microsystems, Inc. | Three overlapped stages of radix-2 square root/division with speculative execution |
KR100237624B1 (ko) * | 1996-10-30 | 2000-01-15 | 김영환 | 반도체 메모리장치의 로우 디코더 |
JPH10135424A (ja) | 1996-11-01 | 1998-05-22 | Mitsubishi Electric Corp | 半導体集積回路装置 |
JPH10241361A (ja) | 1997-02-25 | 1998-09-11 | Toshiba Corp | 半導体記憶装置 |
JP3763433B2 (ja) | 1997-07-08 | 2006-04-05 | 株式会社日立製作所 | 半導体集積回路装置 |
JPH11283369A (ja) | 1998-03-27 | 1999-10-15 | Hitachi Ltd | 半導体集積回路装置 |
US6147914A (en) | 1998-08-14 | 2000-11-14 | Monolithic System Technology, Inc. | On-chip word line voltage generation for DRAM embedded in logic process |
JP2000067538A (ja) * | 1998-08-24 | 2000-03-03 | Alps Electric Co Ltd | サーボパターンが記録されたディスクおよび前記ディスクから読まれたサーボパターンの演算処理方法 |
JP2001126479A (ja) | 1999-10-29 | 2001-05-11 | Toshiba Corp | 半導体メモリ装置 |
JP2001202778A (ja) | 2000-01-19 | 2001-07-27 | Toshiba Corp | 半導体記憶装置 |
JP2001297583A (ja) | 2000-04-13 | 2001-10-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6545923B2 (en) | 2001-05-04 | 2003-04-08 | Samsung Electronics Co., Ltd. | Negatively biased word line scheme for a semiconductor memory device |
US6546923B2 (en) * | 2001-05-31 | 2003-04-15 | Erven D. Erickson | Ball launching apparatus |
US20050105372A1 (en) * | 2003-10-30 | 2005-05-19 | Fujitsu Limited | Semiconductor memory |
JP4437710B2 (ja) * | 2003-10-30 | 2010-03-24 | 富士通マイクロエレクトロニクス株式会社 | 半導体メモリ |
JP4951786B2 (ja) * | 2007-05-10 | 2012-06-13 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
JP2008287826A (ja) | 2007-05-21 | 2008-11-27 | Panasonic Corp | 半導体記憶装置 |
-
2008
- 2008-11-26 JP JP2008300972A patent/JP5202248B2/ja not_active Expired - Fee Related
-
2009
- 2009-02-23 CN CN2009801457011A patent/CN102216996A/zh active Pending
- 2009-02-23 WO PCT/JP2009/000756 patent/WO2010061489A1/ja active Application Filing
-
2011
- 2011-05-04 US US13/100,939 patent/US8345506B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
WO2010061489A1 (ja) | 2010-06-03 |
US20110205829A1 (en) | 2011-08-25 |
JP2010129113A (ja) | 2010-06-10 |
US8345506B2 (en) | 2013-01-01 |
CN102216996A (zh) | 2011-10-12 |
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