JP4988843B2 - 半導体フリップチップパッケージ用の基板およびプロセス - Google Patents
半導体フリップチップパッケージ用の基板およびプロセス Download PDFInfo
- Publication number
- JP4988843B2 JP4988843B2 JP2009522071A JP2009522071A JP4988843B2 JP 4988843 B2 JP4988843 B2 JP 4988843B2 JP 2009522071 A JP2009522071 A JP 2009522071A JP 2009522071 A JP2009522071 A JP 2009522071A JP 4988843 B2 JP4988843 B2 JP 4988843B2
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- Prior art keywords
- bump
- patterned
- solder
- substrate
- conductive circuit
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- H—ELECTRICITY
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/496,111 US7652374B2 (en) | 2006-07-31 | 2006-07-31 | Substrate and process for semiconductor flip chip package |
| US11/496,111 | 2006-07-31 | ||
| PCT/CN2007/002228 WO2008017232A1 (en) | 2006-07-31 | 2007-07-23 | Substrate and process for semiconductor flip chip package |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009545180A JP2009545180A (ja) | 2009-12-17 |
| JP2009545180A5 JP2009545180A5 (enExample) | 2010-03-25 |
| JP4988843B2 true JP4988843B2 (ja) | 2012-08-01 |
Family
ID=38985352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009522071A Active JP4988843B2 (ja) | 2006-07-31 | 2007-07-23 | 半導体フリップチップパッケージ用の基板およびプロセス |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7652374B2 (enExample) |
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| US20110285013A1 (en) * | 2010-05-20 | 2011-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling Solder Bump Profiles by Increasing Heights of Solder Resists |
| US8922004B2 (en) * | 2010-06-11 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper bump structures having sidewall protection layers |
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- 2007-07-23 MY MYPI20090319 patent/MY151533A/en unknown
- 2007-07-23 CN CN2007800278123A patent/CN101496168B/zh active Active
- 2007-07-23 JP JP2009522071A patent/JP4988843B2/ja active Active
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015198836A1 (ja) * | 2014-06-27 | 2015-12-30 | ソニー株式会社 | 半導体装置およびその製造方法 |
| JPWO2015198836A1 (ja) * | 2014-06-27 | 2017-04-20 | ソニー株式会社 | 半導体装置およびその製造方法 |
| US10014248B2 (en) | 2014-06-27 | 2018-07-03 | Sony Corporation | Semiconductor device with less positional deviation between aperture and solder |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2008017232A1 (en) | 2008-02-14 |
| KR20090042777A (ko) | 2009-04-30 |
| MY151533A (en) | 2014-05-30 |
| CN101496168B (zh) | 2011-06-01 |
| US20080023829A1 (en) | 2008-01-31 |
| CN101496168A (zh) | 2009-07-29 |
| JP2009545180A (ja) | 2009-12-17 |
| US7652374B2 (en) | 2010-01-26 |
| EP2054933A4 (en) | 2010-04-21 |
| EP2054933A1 (en) | 2009-05-06 |
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