Classifications

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  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/341—Surface mounted components
  • H05K3/3431—Leadless components
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  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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  • H01L24/10—Bump connectors ; Manufacturing methods related thereto
  • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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  • H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
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  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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Definitions

• This invention relates to a substrate for semiconductor flip chip package, and a process to fabricate the flip chip device with the substrate.
• Flip chip technology is one of the most frequently used package technology for chip scale package. As the flip chip technology can employ area array to dispose bump pad and be connected to the carrier through a bump, it can reduce the packaging area and shorten the transmission path of the signal.
• Traditional type of bump pad design of the substrate can be classified into SMD (Solder Mask Defined) type and
• NSMD Non-Solder Mask Defined
• FIG. 1 and 2 are cross-sectional views of a flip chip package of the NSMD type as an example in the prior art. As shown in FIG. 1 and 2, a plurality of bumps
• the substrate 130 is composed of one or more layers of patterned conducting (e.g., copper) foil and insulating layers stacked in an alternating sequence, together with etching holes (not shown) in the insulating layers for interconnecting the patterned conducting layers.
• the substrate 130 has its surface coated with a solder mask layer 150, and exposes only the bump pads 140 for connection to the bumps of the chip 120. As shown in FIG. 2, a reflow process is employed in the conventional method to heat the bump 110. The heated bumps 110 will melt and form good bonding with the bump pads 140.
• the bump to bump pad connection method suffers from several problems when there are defects or alignment problems on the chip 120 or the substrate 130.
• Typical defects include the position offset of either left-offset or right-offset between bumps 110 and the bump pads 140 as shown in FIG. 3, elevation offset between the coplanarity of the substrate 130 to the chip 120 as shown in FIG. 4, or between the bumps 112 as shown in FIG. 5, position offset due to the misalignment between the distribution of the array of the bumps 110 to the distribution of the bump pads 140 on the substrate 130 as shown in FIG. 6 and FIG. 7.
• the following describes in details the above defects in the flip chip fabricated by conventional process.
• Elevation offset problem can also be caused by non-uniformity in the sizes of the bumps 110.
• one or more of the bumps 112 are too small such that they are unable to touch the bump pads 140, or the bumps 112 are able to touch the bump pads 140 but the contact areas are too small to have a good contact between the bumps 112 and the bump pads 140.
• bad solder joint will be formed between the bumps 112 and the bump pads 140 with low electrical conductance, or there are no electrical contact between the bumps 112 and the bump pads 140 at all, In either case, the bumps 112 are said to have been cracked due to the thermal stress in the refiow process.
• the position offset can also be caused by the misalignment between the distribution of the array of the bumps 110 to the distribution of the bump pads 140 on the substrate 130 as shown in FIG. 6 (showing a misaligned bump 113 straddling a bump pad 142 and a solder mask portion 152), and FIG. 7 (showing a bump 114 straddling a misaligned bump pad 142 and solder mask portion 152).
• the bumps 110 are said to have been cracked due to the thermal stress in the reflow process
• FIG. i4, 15 and 16 are simplified cross sectional side view of prior art flip chips (U.S. patentno. 6975035) illustrating a chip attached to a substrate, wherein the bumps are substantially inserted into the recesses of the substrate with different mounting method.
• the bumps 110 in FIG. 14 are directly bonded to the metallic pads of the substrate, whereas the bumps 110 in FIG. 15 were coated with conductive paste 170 before being inserted into the recesses and interconnections are formed between the conductive paste and the pads.
• the conductive paste 170 is deposited onto the pads instead of the bumps, and interconnections are formed between the bumps 110 and the conductive paste 170.
• FIG. 14 does not solve the potential elevation offset problem as depicted in FIG. 4.
• Mounting method illustrated in FIG. 15 and 16 solves the noncoplanarity problem introduced by inconsistent bump height and imperfection of the substrate, but the potential risk of positional offset as observed in FIG. 3 is still exist.
• the conductive paste 170 cannot spread over the exposed area of the pads.
• only part of the bump surface is contacting the conductive paste 170.
• the conducting areas in both cases are small and thus the solder joint reliability is low.
• splitting of conductive paste 170 onto the surface of the substrate 130 would occur when the bumps llO are inserted into the recesses in FIG. 16.
• the invention is aimed at providing a substrate for flip chip package and a process to fabricate the flip chip device, where the fabrication of the flip chip has large tolerance of chip to substrate co-planar offset, position offset, and accuracy of alignments of the bumps on the chip, and etching holes (bump pads) on the substrate.
• the fabricated flip chip package has an increased contact area between the bumps and the bump pads, thus increase the solder joint reliability, and hence the yield and reliability of the package.
• the present invention provides semiconductor package structure for flip chip package that includes at least a plurality of patterned circuit layers which can be copper or other conductive materials, and an insulating substrate, which can be polymide or other insulating materials, alternately stacking up each other.
• the patterned circuit layers are electrically connected with each other, wherein one of the patterned circuit layers is positioned on the surface of the substrate.
• the patterned circuit layer includes a plurality of bump pads.
• the substrate that covers the patterned circuit layer is etched to form holes which expose the bump pads to the chip.
• the sidewall of the etching holes of the substrate can be electrically plated with copper, or other conductive materials to help to increase the contact area between the chip and the bump pads as discussed in the following.
• the etching holes are filled with solder paste.
• the chip is studd[.i] bumpedstud or bumped with other technique.
• the flip chip package is formed by having the bumps on the chip penetrate into the etching holes filled with solder paste. Therefore, after a reflow process, the contact area between the bumps and the bump pads is not limited to the top surface of the bump pads, but the contact area also include the interior surfaces of the etching holes.
• the contact area between the bumps and the bump pads also includes the side surfaces of the etching holes. Since the contact area between the bumps and the bump pads increases, the solder joint reliability can be improved and the yield and the reliability of the package can also be improved.
• FIG. 1 is a cross-sectional view of a flip chip package in NSMD form according to an example of the prior art with a bumped chip and a substrate with bump pads ready to be form electrical connection
• FIG. 2 is a cross-sectional view of a flip chip package in NSMD form according to an example of the prior art with the bumps of the chip electrically connected to the bump pads of the substrate;
• FIG. 3 is a cross-sectional view of a flip chip package in NSMD form according to an example of the prior art that suffers from position offset problem with misalignment between the bumps on the chip and the bump pads on the substrate;
• FIG. 4 is a cross-sectional view of a flip chip package in NSMD form according to an example of the prior art that suffers from elevation offset problem with a defective substrate
• FIG. 5 is a cross-sectional view of a flip chip package in NSMD form according to an example of the prior art that suffers from elevation offset problem with nonuniform ball size of the bump on the chip;
• FIG. 6 is a cross-sectional view of a flip chip package in NSMD form according to an example of the prior art that suffers from position offset problem with nonuniform bump distribution on the chip;
• FIG. 7 is a cross-sectional view of a flip chip package in NSMD form according to an example of the prior art that suffers from position offset problem with nonuniform bump distribution on the substrate;
• FIG. 8 is a cross-sectional view of a flip chip package according to an illustrative embodiment of the present invention.
• FIG. 9 is a cross-sectional view of a flip chip package according to another embodiment of the present invention with the sidewall of the etching holes plated with copper that electrically connect to the bump pads;
• FIG. 10 is a cross-sectional view of a flip chip package according to another embodiment of the present invention with the etching hole filled with solder paste;
• FIG, 11 is a cross-sectional view of a flip chip package according to another embodiment of the present invention with the bumped chip penetrates into the solder paste filled etching holes of the substrate;
• FIG. 12 is a cross-sectional view of a flip chip package according to another embodiment of the present invention with the bumped chip penetrates into the solder paste filled etching holes of the substrate after a reflow process that collapse the solder paste to form electrical connection between the bumps of the chip and the bump pads;
• FIG. 13 is a cross-sectional view of a flip chip package according to another embodiment of the present invention with the bumped chip penetrates into the solder paste filled etching holes of the substrate after a reflow process that collapse the solder paste to form electrical connection between the bumps of the chip and the bump pads, where the bumps on the chips and the bump pads on the substrate exhibit various forms of non-uniformity;
• FIG. 14 is a cross sectional view of a flip chip package according to an example of prior art for which the bumps attached to the chip are substantially inserted into the recesses of the substrate;
• FIG. 15 is a cross sectional view of a flip chip package according to an example of prior ait for which the bumps attached to the chip are substantially inserted into the recesses of the substrate using another mounting method;
• FIG. 16 is a cross sectional view of a flip chip package according to an example of prior ait for which the bumps attached to the chip are substantially inserted into the recesses of the substrate using another mounting method;
• FIG. 17 is a cross-sectional view of a flip chip package in another embodiment of the invention.
• This application discloses a new way to form electrical connection between the bumped chip and the patterned circuit layer of the substrate. As will be discussed regarding the illustrative embodiments of the present invention, most of the fabrication problem in flip chip can be relieved by using a simple process discussed in this invention.
• FIG. 8 is a cross-sectional view of disclosed flip chip substrate taking copper as an example to form the patterned circuit layer according to an illustrative embodiment of the invention.
• the substrate 830 is formed by an insulating core 832 layer on top of a patterned conductive circuit layer 860. Additional insulating layers and conductive circuit layers stacked in an alternating sequence can be included in the substrate 830.
• the top insulating layer 832 on the surface of the substrate includes a plurality of etching holes 834.
• the etching holes can be formed by patterning and chemical etching, or any other holes forming technique such as punching, mechanical drilling or laser drilling.
• the sidewalls 846 of the etching holes 834 can also be coated with a conductive layer 844 ⁇ e.g., copper), as shown in FIG. 9, by any metal buildup or coating techniques well-known in the art such as electroplating after masking the substrate by photoresist or after electroless plating/deposit of a seed metal layer onto the inside wall of the hole.
• a variety of well-known processes in plated through-hole (“PTH”) technology can be used to plate the sidewalls 846 with a conductive layer 844[.2],
• PTH plated through-hole
• the etching holes 834 are filled with a solder paste 870, as shown in FIG. 10.
• the chip 820 is stud bumped on its active surface in this illustrative embodiment of the invention as shown in FIG. 10.
• each bump 810 has a small protrusion 812 at the tip.
• the etching holes 834 have sufficient capacity to accommodate enough solder paste 870 to ensure adequate electrical contact between the solder bumps 810 and solder bump pads 840 throughout the range of acceptable defects such as position offset due to miss- alignment or non-uniform distribution, and elevation offset due to lack of coplanarity of the chip and substrate.
• the etching holes 834 in the illustrative embodiments have a depth that is approximately the same as the width of the bump pads 840. And the depth of the etching holes in the prior art is comparable to the height of the bumps. Other suitable depths can be used.
• the depth of the etching hole 840 can be designed based on the intended sizes of the bumps 810 to be attached to the substrate 830. For example, a depth of between about 0.5 to about 1.5 times the diameter of the bumps 810 can be used. As another example, a depth of between about 0,7 to about 1.2 times the diameter of the bumps 810 can be used. From yet another perspective, the holes 834 in the illustrative embodiment have sufficient depth to permit the solder paste to immerse a significant portion (e.g., one half of the height of the bumps) of the bumps 810 after the solder paste is collapsed in the reflow process.
• a significant portion e.g., one half of the height of the bumps
• initial (i.e., pre-reflow) contact between the chip 820 and the substrate 830 is formed by having the stud bump 810 of the chip 820 penetrate into the solder paste 870 that fill etching hole 834 as shown in FIG. 11.
• a reflow process is then performed on the chip 820 attached substrate 830 to melt the solder paste 870, such that the melted solder paste 870 collapses (as indicated by the change in shape of the surface 872 of the solder paste 870 between FIGS. 11 and 12) to fill the etching hole FIG. 12.
• the electrical conduction between each of the bumps 810 and each of the bump pads 840 is therefore ensured to a higher degree than the prior art due to the increased certainty of adequate contact area via the solder paste 870. Therefore, the solder joint reliability is improved, with the resultant decrease in the electrical contact resistance between the bumps 810 and the bump pads 840.
• position offset problems due to miss-alignment, or nonuniform distribution, and elevation offset problems due to coplanarity of the chip and substrate, or the bumps can be alleviated,
• the insulating layer 832 can be made of any insulating material suitable for flip-chip packaging.
• a polyimide can be used.
• Other materials, such as high temperature insulating materials can also be applied to form the substrate. Examples include Bismaleimide-Taiazine (BT), (Flame Resistant) FR- 4 and FR-5.
• the conductive layer 860, bump pads 840 and conductive inner walls 844 can be made from any suitable conductive materials for flip-chip packaging. For example, copper, gold, nickel or a combination of them can be used.
• FIG. 13 is a cross-sectional view showing chips and substrate that suffer from position offset, elevation offset, and elevation offset due to nonuniform stud bump size, and position offset due to miss alignment in the distribution of the bumps 810 and bump pads 840.
• the present invention provides adequate design margins of the etching holes 834.
• the width of etching holes 834 is about twice the diameter of the stud bump 810, such that all the bumps 810 can penetrate into the etching holes 834, with sufficient tolerance for lateral alignment variations contemplated. Other relative sizes can be used.
• the width of the etching holes 834 can be from about 1.5 times to about 2.5 times the diameter of the stud bump 810.
• FIG. 16 U.S. patent no. 6975035
• the solder paste 870 that fills the etching holes 834 is collapsed after the reflow process and forms good contacts with the bumps 810 and bump pads 840.
• the stud bumps in the present invention are intentionally formed with elongated lead, such that elongated part of the bump will be completely emerged into but not only partly contacting with the solder paste as illustrated in the prior art.
• the stud bumps size to etching holes size ratio in the illustrative embodiment is comparatively smaller to the prior arts, there will be no splitting of solder paste out of the etching holes onto the substrate surface when the bumps penetrate into the solder paste.
• adhesive element 180 or conductive paste 170 is used as a height controller for the attachment of the chip to the substrate. Ih one example, the height of attachment is predetermined and controlled by the flip chip bonder. This insertion method is not accurate since there is no mechanical feedback and thus the machine cannot adjust the insertion height to compensate for the non-uniformity of the substrates.
• the bumps are predetermined and controlled by the flip chip bonder.
• the machine can detect the stress when the substrate surface contacts the chip surface or the tips of the stud bump contacts the surface of the bond pads.
• an underfill material (not shown) is filled between the chip and the substrate to protect the bump from being cracked due to fatigue collapse caused by thermal stress because of the difference in the coefficient of thermal expansion between the chip and the substrate.
• an adhesive layer 1780 is included in between the chip and the substrate 1730 to further compensate for the irregularities of the substrate 1730 and act as a height controller for the attachment of the chip to the substrate 1730.
• the added adhesive layer 1780 will also function as the interconnecting agent between the chip an the substrate 1730, such that the chip is glued onto the substrate 1730 by both the adhesive layer 1780, and also by the bonding formed between the solder paste 1770 and the stud bump 1710.
• other type of adhesive techniques can be applied to provide extra strength to glue the chip onto the substrate, which will be aligned with the presented embodiment. Noted that in the case of having an extra layer of adhesive material between the chip and the substrate, it will not be necessary to underfill between the chip and the substrate.
• the substrate for flip chip package of the present invention increases the contact area between the bumps and the bump pads to improve the solder joint reliability and the yield of the product, as well as increase the reliability.
• the tolerance in the alignment accuracy is improved due to the bumps penetrating into the etching holes filled with solder paste, which collapse during reflow.
• the area of contact between the bumps and the bump pads is increased, and the adverse impact to the solder joint due to the coplanar error, or position error is reduced. Therefore, the problems of poor contacts between the bumps and the bump pads, and associate large electrical contact resistance is effectively addressed. Consequently, the yield and the quality are also improved.
• Another advantage of the invention is that as the tolerance of the accuracy of alignment between the bumps and the bump pads enhanced, it become easier to align the bumps on the chips with the etching holes (bump pads) on the substrate. This is because with a smaller pressure need to be applied to the chip, it is highly probable that the stressed chip will fall into the etching hole in a similar manner as that discussed in US patent number 6,573,610, which is incorporated herein by reference.
• small vibrations such as ultrasonic vibrations can be applied to the attached chip, such that the vibrating chip will have energy to move around on the surface of the substrate, but when it has penetrated into the etching hole, it will not have enough energy to escape from the etching hole. The probability of obtaining attached chips with substrates that are aligned is thus enhanced.

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• 2006
  • 2006-07-31 US US11/496,111 patent/US7652374B2/en active Active
• 2007
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  • 2007-07-23 EP EP07764102A patent/EP2054933A4/en not_active Withdrawn
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