JP4865361B2 - ドライエッチング方法 - Google Patents

ドライエッチング方法 Download PDF

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Publication number
JP4865361B2
JP4865361B2 JP2006054914A JP2006054914A JP4865361B2 JP 4865361 B2 JP4865361 B2 JP 4865361B2 JP 2006054914 A JP2006054914 A JP 2006054914A JP 2006054914 A JP2006054914 A JP 2006054914A JP 4865361 B2 JP4865361 B2 JP 4865361B2
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JP
Japan
Prior art keywords
gas
etched
etching
dry etching
mask pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006054914A
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English (en)
Japanese (ja)
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JP2007234870A (ja
JP2007234870A5 (https=
Inventor
聡 宇根
正道 坂口
謙一 桑原
朋祥 市丸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi High Tech Corp
Original Assignee
Hitachi High Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi High Technologies Corp filed Critical Hitachi High Technologies Corp
Priority to JP2006054914A priority Critical patent/JP4865361B2/ja
Priority to US11/505,292 priority patent/US20070207618A1/en
Priority to KR1020060078748A priority patent/KR100894300B1/ko
Priority to TW095131155A priority patent/TW200735208A/zh
Publication of JP2007234870A publication Critical patent/JP2007234870A/ja
Publication of JP2007234870A5 publication Critical patent/JP2007234870A5/ja
Priority to US12/435,787 priority patent/US8143175B2/en
Application granted granted Critical
Publication of JP4865361B2 publication Critical patent/JP4865361B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2006054914A 2006-03-01 2006-03-01 ドライエッチング方法 Expired - Fee Related JP4865361B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2006054914A JP4865361B2 (ja) 2006-03-01 2006-03-01 ドライエッチング方法
US11/505,292 US20070207618A1 (en) 2006-03-01 2006-08-17 Dry etching method
KR1020060078748A KR100894300B1 (ko) 2006-03-01 2006-08-21 드라이에칭방법
TW095131155A TW200735208A (en) 2006-03-01 2006-08-24 Dry etching method
US12/435,787 US8143175B2 (en) 2006-03-01 2009-05-05 Dry etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006054914A JP4865361B2 (ja) 2006-03-01 2006-03-01 ドライエッチング方法

Publications (3)

Publication Number Publication Date
JP2007234870A JP2007234870A (ja) 2007-09-13
JP2007234870A5 JP2007234870A5 (https=) 2009-02-19
JP4865361B2 true JP4865361B2 (ja) 2012-02-01

Family

ID=38471971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006054914A Expired - Fee Related JP4865361B2 (ja) 2006-03-01 2006-03-01 ドライエッチング方法

Country Status (4)

Country Link
US (2) US20070207618A1 (https=)
JP (1) JP4865361B2 (https=)
KR (1) KR100894300B1 (https=)
TW (1) TW200735208A (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013258244A (ja) 2012-06-12 2013-12-26 Tokyo Electron Ltd エッチング方法及びプラズマ処理装置
JP2014003085A (ja) * 2012-06-15 2014-01-09 Tokyo Electron Ltd プラズマエッチング方法及びプラズマ処理装置
CN104425228B (zh) * 2013-08-28 2017-06-16 中芯国际集成电路制造(上海)有限公司 多晶硅栅极的形成方法
JP7478059B2 (ja) * 2020-08-05 2024-05-02 株式会社アルバック シリコンのドライエッチング方法
WO2025027769A1 (ja) 2023-07-31 2025-02-06 株式会社日立ハイテク プラズマ処理方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56100421A (en) * 1980-01-17 1981-08-12 Toshiba Corp Plasma etching method
JPS56144542A (en) * 1980-03-17 1981-11-10 Ibm Method of selectively reactively ion etching polycrystalline silicon for monocrsytalline silicon
EP0338102B1 (de) * 1988-04-19 1993-03-10 International Business Machines Corporation Verfahren zur Herstellung von integrierten Halbleiterstrukturen welche Feldeffekttransistoren mit Kanallängen im Submikrometerbereich enthalten
JPH07263415A (ja) * 1994-03-18 1995-10-13 Fujitsu Ltd 半導体装置の製造方法
JP3438313B2 (ja) * 1994-05-12 2003-08-18 富士通株式会社 パターン形成方法
KR100434133B1 (ko) 1995-07-14 2004-08-09 텍사스 인스트루먼츠 인코포레이티드 중간층리쏘그래피
JP2935346B2 (ja) * 1996-07-30 1999-08-16 日本電気株式会社 半導体装置およびその製造方法
US5818110A (en) * 1996-11-22 1998-10-06 International Business Machines Corporation Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same
KR100291585B1 (ko) * 1997-07-25 2001-11-30 윤종용 반도체장치의금속막식각방법
KR20010003257A (ko) 1999-06-22 2001-01-15 김영환 반도체소자의 제조방법
JP2001035808A (ja) * 1999-07-22 2001-02-09 Semiconductor Energy Lab Co Ltd 配線およびその作製方法、この配線を備えた半導体装置、ドライエッチング方法
TW452971B (en) 1999-12-28 2001-09-01 Promos Technologies Inc Manufacturing method of bottle-shaped deep trench
KR20010083476A (ko) 2000-02-15 2001-09-01 박종섭 미세패턴 형성방법
JP2002151470A (ja) * 2000-11-09 2002-05-24 Mitsubishi Electric Corp ハードマスクの形成方法および半導体装置の製造方法
JP2002343798A (ja) * 2001-05-18 2002-11-29 Mitsubishi Electric Corp 配線層のドライエッチング方法、半導体装置の製造方法および該方法によって得られた半導体装置
JP4257051B2 (ja) * 2001-08-10 2009-04-22 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP2003163349A (ja) * 2001-11-28 2003-06-06 Mitsubishi Electric Corp 半導体装置の製造方法
US6900139B1 (en) * 2002-04-30 2005-05-31 Advanced Micro Devices, Inc. Method for photoresist trim endpoint detection
US6762130B2 (en) 2002-05-31 2004-07-13 Texas Instruments Incorporated Method of photolithographically forming extremely narrow transistor gate elements
KR200291154Y1 (ko) * 2002-07-09 2002-10-11 박성준 전기ㆍ전자기기의 전선 정리용 기구

Also Published As

Publication number Publication date
US20090280651A1 (en) 2009-11-12
JP2007234870A (ja) 2007-09-13
TWI334174B (https=) 2010-12-01
KR100894300B1 (ko) 2009-04-24
TW200735208A (en) 2007-09-16
KR20070090063A (ko) 2007-09-05
US20070207618A1 (en) 2007-09-06
US8143175B2 (en) 2012-03-27

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