JP2007234870A - ドライエッチング方法 - Google Patents
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- JP2007234870A JP2007234870A JP2006054914A JP2006054914A JP2007234870A JP 2007234870 A JP2007234870 A JP 2007234870A JP 2006054914 A JP2006054914 A JP 2006054914A JP 2006054914 A JP2006054914 A JP 2006054914A JP 2007234870 A JP2007234870 A JP 2007234870A
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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Abstract
【解決手段】プラズマエッチング装置を使用して半導体基板に配線加工を行うドライエッチング方法であって、被エッチング材12の上に設けたホトレジスト15およびSiN、SiON、SiO等の無機膜14,13からなるマスクパターンを用いて被エッチング材12をエッチングする工程において、塩素含有ガスまたは臭素含有ガス等のハロゲン系ガスと、CF4、CHF3、SF6、NF3からなるフッ素含有ガスうちの少なくとも一つのフッ素含有ガスとの混合ガスを用いて被エッチング材12の加工中に前記マスクパターンと被エッチング材の加工寸法を同じ程度に縮小化させる。
【選択図】図2(D)
Description
Claims (11)
- プラズマエッチング装置を使用して半導体基板に配線加工を行うドライエッチング方法であって、
被エッチング材の上に設けたSiN、SiON、SiO等の無機膜からなるマスクパターンを用いて前記被エッチング材をエッチングする工程において、前記被エッチング材の加工中に前記マスクパターンと前記被エッチング材の加工寸法を同じ程度に縮小化させることを特徴とするドライエッチング方法。 - 前記加工寸法の縮小化を、塩素含有ガスまたは臭素含有ガス等のハロゲン系ガスと、CF4、CHF3、SF6、NF3からなるフッ素含有ガスうちの少なくとも一つのフッ素含有ガスとの混合ガスを用いて行うことを特徴とする請求項1に記載のドライエッチング方法。
- 前記加工寸法の縮小化を、塩素含有ガスまたは臭素含有ガス等のハロゲン系ガスと、CF4、CHF3、SF6、NF3からなるフッ素含有ガスのうち少なくとも一つのフッ素含有ガスとの混合ガスを用いて行い、前記フッ素含有ガスを前記混合ガスの40〜90%の比率で用いることを特徴とする請求項1に記載のドライエッチング方法。
- 前記加工寸法の縮小化を、前記プラズマエッチング装置のRFバイアスを制御して行い、前記被エッチング材の縮小化率を調整することを特徴とする請求項1に記載のドライエッチング方法。
- 前記加工寸法の縮小化を、塩素含有ガスまたは臭素含有ガス等のハロゲン系ガスと、CF4、CHF3、SF6、NF3からなるフッ素含有ガスうちの少なくとも一つのフッ素含有ガスとの混合ガスを用いて行うとともに前記プラズマエッチング装置のRFバイアスを制御して前記被エッチング材の縮小化率を調整することを特徴とする請求項1に記載のドライエッチング方法。
- プラズマエッチング装置を使用して半導体基板に配線加工を行うドライエッチング方法であって、
被エッチング材の上に設けたホトレジストおよびSiN、SiON、SiO等の無機膜のマスクパターンを用いて前記被エッチング材をエッチングする工程において、前記被エッチング材の加工中に前記マスクパターンと前記被エッチング材の加工寸法を同じ程度に縮小化させることを特徴とするドライエッチング方法。 - 前記加工寸法の縮小化を、塩素含有ガスまたは臭素含有ガス等のハロゲン系ガスと、CF4、CHF3、SF6、NF3からなるフッ素含有ガスうちの少なくとも一つのフッ素含有ガスとの混合ガスを用いて行うことを特徴とする請求項6に記載のドライエッチング方法。
- 前記加工寸法の縮小化を、塩素含有ガスまたは臭素含有ガス等のハロゲン系ガスと、CF4、CHF3、SF6、NF3からなるフッ素含有ガスのうち少なくとも一つのフッ素含有ガスとの混合ガスを用いて行い、前記フッ素含有ガスを前記混合ガスの40〜90%の比率で用いることを特徴とする請求項6に記載のドライエッチング方法。
- 前記加工寸法の縮小化を、前記プラズマエッチング装置のRFバイアスを制御して行い、前記被エッチング材の縮小化率を調整することを特徴とする請求項6に記載のドライエッチング方法。
- 前記加工寸法の縮小化を、塩素含有ガスまたは臭素含有ガス等のハロゲン系ガスと、CF4、CHF3、SF6、NF3からなるフッ素含有ガスうちの少なくとも一つのフッ素含有ガスとの混合ガスを用いて行うとともに、前記プラズマエッチング装置のRFバイアスを制御して前記被エッチング材の縮小化率を調整することを特徴とする請求項6に記載のドライエッチング方法。
- プラズマエッチング装置を使用してホトレジストおよびSiN、SiON、SiO等の無機膜のマスクパターンを用いて半導体基板に設けた配線層に配線加工を行うドライエッチング方法であって、
前記ホトレジストを用いて形成したマスクパターンをO2を用いて縮小化する第1の工程と、
前記縮小化したホトレジストを用いて形成したマスクパターンを使用してCF4およびCHF3の混合ガスを用いてSiN、SiON、SiO等の無機膜の前記マスクパターンを異方性エッチングする第2の工程と、
前記ホトレジストおよびSiN、SiON、SiO等の無機膜のマスクパターンを使用してCl2およびCF4の混合ガスを用いて前記配線層をエッチングするとともに前記マスクパターンを縮小化する第3の工程と、
第3の工程に続いてSiN、SiON、SiO等の無機膜のマスクパターンを使用してHBrおよびO2の混合ガスを用いて配線層をエッチングする第4の工程と、
を有することを特徴とするドライエッチング方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006054914A JP4865361B2 (ja) | 2006-03-01 | 2006-03-01 | ドライエッチング方法 |
US11/505,292 US20070207618A1 (en) | 2006-03-01 | 2006-08-17 | Dry etching method |
KR1020060078748A KR100894300B1 (ko) | 2006-03-01 | 2006-08-21 | 드라이에칭방법 |
TW095131155A TW200735208A (en) | 2006-03-01 | 2006-08-24 | Dry etching method |
US12/435,787 US8143175B2 (en) | 2006-03-01 | 2009-05-05 | Dry etching method |
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Application Number | Priority Date | Filing Date | Title |
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JP2006054914A JP4865361B2 (ja) | 2006-03-01 | 2006-03-01 | ドライエッチング方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007234870A true JP2007234870A (ja) | 2007-09-13 |
JP2007234870A5 JP2007234870A5 (ja) | 2009-02-19 |
JP4865361B2 JP4865361B2 (ja) | 2012-02-01 |
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JP2006054914A Expired - Fee Related JP4865361B2 (ja) | 2006-03-01 | 2006-03-01 | ドライエッチング方法 |
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US (2) | US20070207618A1 (ja) |
JP (1) | JP4865361B2 (ja) |
KR (1) | KR100894300B1 (ja) |
TW (1) | TW200735208A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013187219A1 (ja) * | 2012-06-12 | 2013-12-19 | 東京エレクトロン株式会社 | エッチング方法及びプラズマ処理装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014003085A (ja) * | 2012-06-15 | 2014-01-09 | Tokyo Electron Ltd | プラズマエッチング方法及びプラズマ処理装置 |
CN104425228B (zh) * | 2013-08-28 | 2017-06-16 | 中芯国际集成电路制造(上海)有限公司 | 多晶硅栅极的形成方法 |
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2006
- 2006-03-01 JP JP2006054914A patent/JP4865361B2/ja not_active Expired - Fee Related
- 2006-08-17 US US11/505,292 patent/US20070207618A1/en not_active Abandoned
- 2006-08-21 KR KR1020060078748A patent/KR100894300B1/ko not_active IP Right Cessation
- 2006-08-24 TW TW095131155A patent/TW200735208A/zh not_active IP Right Cessation
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2009
- 2009-05-05 US US12/435,787 patent/US8143175B2/en not_active Expired - Fee Related
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JPS56100421A (en) * | 1980-01-17 | 1981-08-12 | Toshiba Corp | Plasma etching method |
JPS56144542A (en) * | 1980-03-17 | 1981-11-10 | Ibm | Method of selectively reactively ion etching polycrystalline silicon for monocrsytalline silicon |
JPH07307328A (ja) * | 1994-05-12 | 1995-11-21 | Fujitsu Ltd | パターン形成方法 |
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Cited By (4)
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KR20150024307A (ko) * | 2012-06-12 | 2015-03-06 | 도쿄엘렉트론가부시키가이샤 | 에칭 방법 및 플라즈마 처리 장치 |
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Also Published As
Publication number | Publication date |
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US8143175B2 (en) | 2012-03-27 |
US20090280651A1 (en) | 2009-11-12 |
TWI334174B (ja) | 2010-12-01 |
JP4865361B2 (ja) | 2012-02-01 |
KR100894300B1 (ko) | 2009-04-24 |
TW200735208A (en) | 2007-09-16 |
KR20070090063A (ko) | 2007-09-05 |
US20070207618A1 (en) | 2007-09-06 |
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