US20070207618A1 - Dry etching method - Google Patents

Dry etching method Download PDF

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Publication number
US20070207618A1
US20070207618A1 US11/505,292 US50529206A US2007207618A1 US 20070207618 A1 US20070207618 A1 US 20070207618A1 US 50529206 A US50529206 A US 50529206A US 2007207618 A1 US2007207618 A1 US 2007207618A1
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US
United States
Prior art keywords
gas
etched
fluorine
containing gas
dry etching
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Abandoned
Application number
US11/505,292
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English (en)
Inventor
Satoshi Une
Masamichi Sakaguchi
Kenichi Kuwabara
Tomoyoshi Ichimaru
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Hitachi High Tech Corp
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Individual
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Filing date
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Assigned to HITACHI HIGH-TECHNOLOGIES CORPORATION reassignment HITACHI HIGH-TECHNOLOGIES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SAKAGUCHI, MASAMICHI, ICHIMARU, TOMOYOSHI, KUWABARA, KENICHI, UNE, SATOSHI
Publication of US20070207618A1 publication Critical patent/US20070207618A1/en
Priority to US12/435,787 priority Critical patent/US8143175B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks

Definitions

  • the present invention relates to a method for etching semiconductor devices. More specifically, the present invention relates to a dry etching method capable of reducing the wiring dimension without causing defective pattern by reducing the processing dimension simultaneously while processing a material to be etched which is the wiring layer disposed on the semiconductor substrate.
  • the photoresist pattern used as the mask is reduced in dimension via dry etching prior to processing the material to be etched, so as to reduce the processing dimension of the material to be etched.
  • ArF resist has been adopted as the material for the photoresist mask capable of being exposed via an ArF laser, which is capable of forming a micropattern with higher accuracy.
  • ArF resist cannot be deposited as thick as the conventional mask members, and since ArF has a high etching rate, it has a property vulnerable to etching. Therefore, the ArF resist has a drawback in that the mask is removed during processing of the material to be etched, making it impossible to perform fine wiring process of the material to be etched with high accuracy.
  • an inorganic film layer composed of SiON, SiN, SiO or the like is disposed between the photoresist mask and the material to be etched, wherein the inorganic film layer is processed via dry etching using a reduced photoresist mask pattern, according to which an inorganic film mask having a slow etching rate is formed to realize stable processing of the material to be etched.
  • This technique is disclosed for example in Japanese patent application laid-open publication No. 9-237777 (patent document 1).
  • the object of the present invention is to provide a dry etching method capable of reducing the processing dimension during processing of the material to be etched, and realizing fine processing without causing drawbacks such as disconnection and deflection of the material to be etched due to mask defection.
  • the above object can be realized by using a patterned photoresist as the mask so as to process an inorganic layer via dry etching to form an inorganic film mask, and then simultaneously reducing the inorganic film mask and the material to be etched during the process for etching the material to be etched.
  • the present invention enables to reduce the processing dimension significantly and perform fine wire processing without causing disconnection or deflection of the wiring of the material to be etched which may accompany the reduction of the processing dimension.
  • FIG. 1 is a schematic cross-sectional view of a microwave plasma etching apparatus to which the etching method of the present invention is applied;
  • FIG. 2A is a cross-sectional view showing the relevant portion of a semiconductor substrate after forming a resist mask according to an embodiment of the present invention
  • FIG. 2B is a cross-sectional view showing the relevant portion of a semiconductor substrate during a resist mask reduction process according to an embodiment of the present invention
  • FIG. 2C is a cross-sectional view showing the relevant portion of a semiconductor substrate during the etching process of SiON film and SiN film according to an embodiment of the present invention
  • FIG. 2D is a cross-sectional view showing the relevant portion of a semiconductor substrate during the etching process for reducing the SiON film and SiN film and reducing the polysilicon film according to an embodiment of the present invention
  • FIG. 2E is a cross-sectional view showing the relevant portion of a semiconductor substrate during the etching process of the polysilicon film according to an embodiment of the present invention
  • FIG. 3A is a graph describing the RF bias dependency of the reduction rate according to the present invention.
  • FIG. 3B is a drawing illustrating the etching depth and the lateral direction etching of the mask according to FIG. 3A .
  • FIG. 1 illustrates a plasma etching apparatus to which the dry etching method according to the present invention is applied.
  • the illustrated plasma etching apparatus is an example of a microwave plasma etching apparatus utilizing microwaves and magnetic field as means for generating plasma.
  • Microwaves generated by a magnetron 1 travel through a waveguide 2 and a quartz panel 3 to enter a vacuum chamber.
  • Solenoid coils 4 are disposed around the vacuum chamber, which generate a magnetic field that acts together with the microwaves entering the vacuum chamber to cause electron cyclotron resonance (ECR) Thereby, process gases can efficiently be turned into plasma 5 with high density.
  • ECR electron cyclotron resonance
  • a processing wafer 6 is held onto the electrode via electrostatic chuck by applying a DC voltage to a substrate stage 8 from an electrostatic chuck power supply 7 . Furthermore, a high-frequency power supply 9 is connected to the electrode, applying high-frequency power (RF bias) so as to provide an accelerating potential in the perpendicular direction with respect to the wafer to the ions in the plasma.
  • the gas used for etching is discharged after etching through an exhaust port disposed on the lower portion of the apparatus via a turbo pump—dry pump (not shown).
  • Plasma etching apparatuses such as a microwave plasma etching apparatus, an inductively coupled plasma etching apparatus, a helicon wave plasma etching apparatus and a double-frequency-excited parallel plate plasma etching apparatus are adopted.
  • FIGS. 2A through 2E illustrate the manufacturing method of a semiconductor device using the plasma etching apparatus of FIG. 1 .
  • FIG. 2A shows the structure of a sample used in the present embodiment
  • FIG. 2B shows the step of reducing the processing dimension of the photoresist mask
  • FIG. 2C shows the mask forming process of the SiON film and SiN film
  • FIG. 2D shows the step of processing the mask and polysilicon film and the step of reducing the processing dimension
  • FIG. 2E shows the step of processing the polysilicon film.
  • FIG. 2A The example of the structure of a sample used according to one preferred embodiment of the present invention is shown in FIG. 2A .
  • a gate oxide film 11 (2 nm), a polysilicon film 12 (film thickness 100 nm), an SiN film 13 (50 nm), an SiON film 14 (25 nm) and a photoresist 15 (250 nm) are sequentially formed on a silicon substrate 10 with a diameter of 12 inches, and thereafter, a mask pattern is formed via photolithography technology.
  • FIG. 2B shows the step of reducing the processing dimension of the photoresist mask that has been performed conventionally, and for example, etching is performed using plasma generated from a mixed gas having O 2 gas added to Ar gas, with the processing pressure set to 0.2 Pa and the microwaves set to 600 W.
  • the O 2 gas flow rate determines the reducing rate of the photoresist, and approximately 10% of O 2 gas is added so as to set the reduction rate to approximately 1.5 nm/sec.
  • the reduction rate increases by increasing the amount of O 2 gas.
  • a pattern with an initial photoresist pattern dimension of 100 nm is subjected to processing for 43 seconds, by which the photoresist pattern dimension is narrowed down to 35 nm.
  • the photoresist 15 is used as a mask to etch the SiON film 14 and the SiN film 13 .
  • the etching process is performed while having the interface with the polysilicon film 12 detected via an etching monitor such as an EPD (end point detector).
  • etching is performed by applying 100 W of RF bias to plasma generated from a mixed gas composed of CF 4 gas and CHF 3 gas mixed with a ratio of 1:1 and with the processing pressure set to 0.8 Pa.
  • the etching of the SiN film 13 is ended when the surface of the polysilicon film 12 is detected.
  • the step of reducing the processing dimension of the polysilicon film illustrated in FIG. 2D is the characteristic step of the present invention, wherein the pattern dimension is reduced by performing etching in the depth direction and simultaneously performing etching in the lateral direction using the pattern of the SiON film 14 and the SiN film 13 formed in FIG. 2C as the mask.
  • CF 4 together with Cl 2 , it becomes possible to etch the mask material simultaneously while etching the polysilicon film 12 .
  • processing conditions for example, 30 W of RF bias is applied to plasma generated by applying 900 W of microwaves to a mixed gas composed of Cl 2 gas and CF 4 gas with a ratio of 1:3 and a processing pressure of 0.2 Pa, so as to perform etching both in the depth direction and the lateral direction.
  • the etching thickness of the polysilicon in the lateral direction depends on the application thickness of the RF bias, as shown in FIG. 3A , and according to the present embodiment, the processing conditions are optimized so that the reduction ratio in the lateral direction with respect to the depth direction is approximately 0.32. According to the present embodiment, processing is performed under this processing condition until approximately 50 nm which is half the thickness 100 nm of the polysilicon film 12 is etched, and then the pattern reduced to 35 nm via the processing dimension reduction step of the photoresist 14 , the SiON film 14 and the SiN film 13 is further reduced by 16 nm to obtain a pattern with a dimension of 19 nm.
  • the photoresist 14 is totally etched, and thereafter, the SiON film 14 and the SiN film 13 are used as the mask.
  • isotropic etching can be continued until either the photoresist 14 is gone or the mask width reaches a determined size, which for example is 19 nm.
  • the reduction thickness according to FIG. 3A is the value obtained by subtracting dimension B of the mask width after etching from the initial dimension A of the mask width, and the reduction ratio is the value obtained by dividing this reduction thickness by the etching depth of the polysilicon film.
  • the processing dimension of the polysilicon subjected to reduction in the former step is maintained while the remaining polysilicon film is etched.
  • processing conditions for example, etching is performed by applying 30 W of RF bias to plasma generated by applying 900 W of microwaves to a mixed gas having O 2 gas added to HBr gas in the amount of approximately 4% of the HBr gas flow rate, with the processing pressure set to 0.4 Pa. According to the etching conditions in this step, the etching of the polysilicon in the lateral direction will not occur, and the etching is performed while maintaining the processing dimension formed in the upper layer.
  • the present embodiment enables to realize a polysilicon wiring process with a width of 19 nm without causing any disconnection or deflection (side etching) of the material being etched by using a mask pattern having an initial dimension of 100 nm.
  • the processing conditions of the process of FIG. 2D (wherein the ratio of Cl 2 gas to CF 4 gas is 1:3) is a condition optimized to correspond to the sample of the present embodiment, and the amount of CF 4 to be added should preferably be within the range of 40 to 90% from the viewpoint of shape control. If the amount of CF 4 being added is 40% or smaller, the etching performed by fluorine in the lateral direction will not progress effectively, and it becomes difficult to reduce the pattern dimension. On the other hand, if the amount of CF 4 being added is 90% or greater, the isotropic etching by fluoride becomes intense, by which the side etching is performed intensely and the perpendicular profile will not be maintained. Other than the reduction rate control method shown in FIG.
  • the reduction rate can also be controlled by adding O 2 gas to the Cl 2 gas and CF 4 gas, or fluorine-containing gas such as CHF 3 , SF 6 and NF 3 , or by using fluorine-containing gas such as CHF 3 , SF 6 and NF 3 instead of the CF 4 gas.
  • the reduction rate can also be controlled by using a halogen-based gas such as HBr gas instead of the Cl 2 gas.
  • the present embodiment discloses process conditions optimized with respect to the sample of a semiconductor device, and the method for etching the polysilicon film 12 , the SiN film 13 , the SiON film 14 and the photoresist 15 is not restricted to the conditions of the present embodiment.
  • the present invention is described with reference to the wiring process of polysilicon, it is not restricted thereto, and the present invention can also be applied to wiring processes of materials other than polysilicon in a semiconductor device manufacturing process.
  • the present invention can be applied to the wiring process of an object having tungsten silicide (WSi) film formed on a polysilicon film 12 , and further having an SiN film 13 , an SiON film 14 , a photoresist 15 and the like formed thereon. Since the reduction rate varies according to the material to be processed, it is preferable to seek the appropriate gas or the appropriate processing conditions corresponding to the material.
  • WSi tungsten silicide
  • a sample having a photoresist mask is used in the present embodiment, but the present invention can be applied to samples using an inorganic film mask such as SiN, SiON and SiO 2 , in other words, samples having the photoresist 15 of FIG. 2D removed.
  • an inorganic film mask such as SiN, SiON and SiO 2
  • the present embodiment utilizes a plasma etching apparatus using microwaves and magnetic fields, but the present invention can be applied regardless of how plasma is generated.
  • equivalent effects can be achieved by applying the present invention to a helicon wave plasma etching apparatus, an inductively-coupled plasma etching apparatus, a capacitively-coupled plasma etching apparatus and so on.

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
US11/505,292 2006-03-01 2006-08-17 Dry etching method Abandoned US20070207618A1 (en)

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US12/435,787 US8143175B2 (en) 2006-03-01 2009-05-05 Dry etching method

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JP2006-054914 2006-03-01
JP2006054914A JP4865361B2 (ja) 2006-03-01 2006-03-01 ドライエッチング方法

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104303274A (zh) * 2012-06-15 2015-01-21 东京毅力科创株式会社 等离子体蚀刻方法及等离子体处理装置
US9224616B2 (en) 2012-06-12 2015-12-29 Tokyo Electron Limited Etching method and plasma processing apparatus

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104425228B (zh) * 2013-08-28 2017-06-16 中芯国际集成电路制造(上海)有限公司 多晶硅栅极的形成方法
JP7478059B2 (ja) * 2020-08-05 2024-05-02 株式会社アルバック シリコンのドライエッチング方法
WO2025027769A1 (ja) 2023-07-31 2025-02-06 株式会社日立ハイテク プラズマ処理方法

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US5818110A (en) * 1996-11-22 1998-10-06 International Business Machines Corporation Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same
US20020173150A1 (en) * 2001-05-18 2002-11-21 Mitsubishi Denki Kabushiki Kaisha Wiring layer dry etching method, semiconductor device manufacturing method, and semiconductor device obtained according to the method
US20050151262A1 (en) * 2001-08-10 2005-07-14 Tsuyoshi Tamaru Semiconductor integrated circuit device
US20050266593A1 (en) * 1999-07-22 2005-12-01 Semiconductor Energy Laboratory Co., Ltd. Wiring and manufacturing method thereof, semiconductor device comprising said wiring, and dry etching method

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9224616B2 (en) 2012-06-12 2015-12-29 Tokyo Electron Limited Etching method and plasma processing apparatus
CN104303274A (zh) * 2012-06-15 2015-01-21 东京毅力科创株式会社 等离子体蚀刻方法及等离子体处理装置

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Publication number Publication date
JP4865361B2 (ja) 2012-02-01
US20090280651A1 (en) 2009-11-12
JP2007234870A (ja) 2007-09-13
TWI334174B (https=) 2010-12-01
KR100894300B1 (ko) 2009-04-24
TW200735208A (en) 2007-09-16
KR20070090063A (ko) 2007-09-05
US8143175B2 (en) 2012-03-27

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