JP7350983B2 - 半導体装置製造方法およびプラズマ処理方法 - Google Patents
半導体装置製造方法およびプラズマ処理方法 Download PDFInfo
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- JP7350983B2 JP7350983B2 JP2022506213A JP2022506213A JP7350983B2 JP 7350983 B2 JP7350983 B2 JP 7350983B2 JP 2022506213 A JP2022506213 A JP 2022506213A JP 2022506213 A JP2022506213 A JP 2022506213A JP 7350983 B2 JP7350983 B2 JP 7350983B2
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Description
本発明の一実施形態に利用可能なECR(Electron Cyclotron Resonance)方式のマイクロ波プラズマエッチング装置(以下、「プラズマ処理装置」ともいう。)300の概略断面図を、図3に示す。このマイクロ波プラズマエッチング装置300において、上部が開放された真空容器301の上部に真空容器301内にエッチングガスを供給するためのシャワープレート302(例えば石英製)と、誘電体窓303(例えば石英製)とを配置し、真空容器301を密封することにより、プラズマ処理室である処理室304を形成する。シャワープレート302にはエッチングガスを流すためのガス供給装置305が接続される。
図4の(A)に示すように、レジストマスク膜101に沿ってハードマスク膜であるSiO2膜102をエッチングする。
図4の(B)に示すように、nチャネルFET形成領域Rnの有機埋込膜であるBARC膜103をエッチングする。
図4の(C)に示すように、露出したnチャネルFET形成領域RnのWFM膜であるTiN膜104をある一定量エッチング(アンダーエッチング)し、かつnチャネルFET形成領域RnとpチャネルFET形成領域Rpの底部のTiN膜104を除去する。
図4の(G)に示すように、マイクロ波プラズマエッチング装置300の処理室304内に表面改質用プラズマ421を発生させて、pチャネルFET形成領域RpのBARC膜103の側面部の表面改質処理を実施する。表面改質処理は、図5に示すような表面改質処理条件51を利用する。
図4の(H)に示すように、有機膜堆積処理を実施する。有機膜堆積処理では、処理室304内に有機膜堆積用プラズマ422を発生させて、pチャネルFET形成領域RpのBARC膜103の側面部および空間111に有機膜431を形成する。有機膜堆積処理は、図6に示すような有機膜堆積処理条件61を利用する。
そして、ステップS4とステップS5とを複数回繰り返して実施する。繰り返し回数は、n回とする。ここで、nの値は、有機膜431の膜厚が所望の膜厚値となるように設定することになる。
その後、有機膜431の膜厚を測定する。
102・・・ハードマスク膜
103・・・有機埋込膜(有機膜)
104・・・WFM膜(仕事関数制御金属膜)
105・・・HK膜(低抵抗ゲート金属膜)
106・・・Si膜(チェネル層)
107・・・Si基板
111・・・凹型の空間
421・・・表面改質用プラズマ
422・・・有機膜堆積用プラズマ
431・・・有機膜(保護膜)
Claims (12)
- Gate All Around型Field effect transistorを備える半導体装置を製造する半導体装置の製造方法において、
n型チャネルの有機膜を除去する工程と、
チャネル間の底面の仕事関数制御金属膜を除去する工程と、
p型チャネルの有機膜に保護膜を形成する工程と、
n型チャネルの仕事関数制御金属膜を除去する工程と、を有し、
前記保護膜を形成する工程は、フッ素含有ガスを用いて生成されたプラズマを前記n型チャネルおよび前記p型チャネルに曝す第一の工程を有することを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記保護膜を形成する工程は、前記第一の工程後、炭素と水素を含有するガスを用いて生成されたプラズマを前記n型チャネルおよび前記p型チャネルに曝す第二の工程をさらに有することを特徴とする半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記第一の工程の処理時間は、前記第二の工程の処理時間より短いことを特徴とするプラズマ処理方法。 - 請求項1に記載の半導体装置の製造方法において、
前記フッ素含有ガスは、SF 6 ガス、NF 3 ガス、CHF 3 ガス、CH 3 Fガス、CH 2 F 2 ガスまたはC 4 F 8 ガスであることを特徴とする半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記炭素と水素を含有するガスは、メタンガスであることを特徴とする半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記第二の工程のプラズマは、メタンガスと窒素ガスとアルゴンガスの混合ガスを用いて生成されることを特徴とする半導体装置の製造方法。 - Gate All Around型Field effect transistorを形成するプラズマ処理方法において、
n型チャネルの有機膜を除去する工程と、
チャネル間の底面の仕事関数制御金属膜を除去する工程と、
p型チャネルの有機膜に保護膜を形成する工程と、
n型チャネルの仕事関数制御金属膜を除去する工程と、を有し、
前記保護膜を形成する工程は、フッ素含有ガスを用いて生成されたプラズマを前記n型チャネルおよび前記p型チャネルに曝す第一の工程を有することを特徴とするプラズマ処理方法。 - 請求項7に記載のプラズマ処理方法において、
前記保護膜を形成する工程は、前記第一の工程後、炭素と水素を含有するガスを用いて生成されたプラズマを前記n型チャネルおよび前記p型チャネルに曝す第二の工程をさらに有することを特徴とするプラズマ処理方法。 - 請求項8に記載のプラズマ処理方法において、
前記第一の工程の処理時間は、前記第二の工程の処理時間より短いことを特徴とするプラズマ処理方法。 - 請求項7に記載のプラズマ処理方法において、
前記フッ素含有ガスは、SF6ガス、NF3ガス、CHF3ガス、CH3Fガス、CH2F2ガスまたはC4F8ガスであることを特徴とするプラズマ処理方法。 - 請求項8に記載のプラズマ処理方法において、
前記炭素と水素を含有するガスは、メタンガスであることを特徴とするプラズマ処理方法。 - 請求項8に記載のプラズマ処理方法において、
前記第二の工程のプラズマは、メタンガスと窒素ガスとアルゴンガスの混合ガスを用いて生成されることを特徴とするプラズマ処理方法。
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US20200006356A1 (en) | 2018-06-27 | 2020-01-02 | International Business Machines Corporation | Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions |
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US20190378906A1 (en) | 2018-06-12 | 2019-12-12 | International Business Machines Corporation | Nanosheet single gate (sg) and extra gate (eg) field effect transistor (fet) co-integration |
US20200006356A1 (en) | 2018-06-27 | 2020-01-02 | International Business Machines Corporation | Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions |
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