JP4832807B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP4832807B2
JP4832807B2 JP2005165252A JP2005165252A JP4832807B2 JP 4832807 B2 JP4832807 B2 JP 4832807B2 JP 2005165252 A JP2005165252 A JP 2005165252A JP 2005165252 A JP2005165252 A JP 2005165252A JP 4832807 B2 JP4832807 B2 JP 4832807B2
Authority
JP
Japan
Prior art keywords
hole
insulating film
interlayer insulating
barrier metal
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005165252A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006024905A (ja
JP2006024905A5 (enExample
Inventor
和義 前川
健壹 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2005165252A priority Critical patent/JP4832807B2/ja
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to US11/148,307 priority patent/US7192871B2/en
Publication of JP2006024905A publication Critical patent/JP2006024905A/ja
Priority to US11/676,951 priority patent/US7709955B2/en
Priority to US11/676,962 priority patent/US7709388B2/en
Publication of JP2006024905A5 publication Critical patent/JP2006024905A5/ja
Priority to US12/730,039 priority patent/US7936069B2/en
Priority to US13/052,712 priority patent/US8222146B2/en
Application granted granted Critical
Publication of JP4832807B2 publication Critical patent/JP4832807B2/ja
Priority to US13/419,053 priority patent/US8432037B2/en
Priority to US13/867,733 priority patent/US8749064B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/034—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics bottomless barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
    • H10W20/0523—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by irradiating with ultraviolet or particle radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/067—Manufacture or treatment of conductive parts of the interconnections by modifying the pattern of conductive parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2005165252A 2004-06-10 2005-06-06 半導体装置 Expired - Fee Related JP4832807B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2005165252A JP4832807B2 (ja) 2004-06-10 2005-06-06 半導体装置
US11/148,307 US7192871B2 (en) 2004-06-10 2005-06-09 Semiconductor device with a line and method of fabrication thereof
US11/676,951 US7709955B2 (en) 2004-06-10 2007-02-20 Semiconductor device with a line and method of fabrication thereof
US11/676,962 US7709388B2 (en) 2004-06-10 2007-02-20 Semiconductor device with a line and method of fabrication thereof
US12/730,039 US7936069B2 (en) 2004-06-10 2010-03-23 Semiconductor device with a line and method of fabrication thereof
US13/052,712 US8222146B2 (en) 2004-06-10 2011-03-21 Semiconductor device with a line and method of fabrication thereof
US13/419,053 US8432037B2 (en) 2004-06-10 2012-03-13 Semiconductor device with a line and method of fabrication thereof
US13/867,733 US8749064B2 (en) 2004-06-10 2013-04-22 Semiconductor device with a line and method of fabrication thereof

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2004172500 2004-06-10
JP2004172500 2004-06-10
JP2005165252A JP4832807B2 (ja) 2004-06-10 2005-06-06 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2008125029A Division JP4786680B2 (ja) 2004-06-10 2008-05-12 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2006024905A JP2006024905A (ja) 2006-01-26
JP2006024905A5 JP2006024905A5 (enExample) 2008-06-26
JP4832807B2 true JP4832807B2 (ja) 2011-12-07

Family

ID=35459691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005165252A Expired - Fee Related JP4832807B2 (ja) 2004-06-10 2005-06-06 半導体装置

Country Status (2)

Country Link
US (5) US7192871B2 (enExample)
JP (1) JP4832807B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9553121B2 (en) 2014-08-28 2017-01-24 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6764940B1 (en) 2001-03-13 2004-07-20 Novellus Systems, Inc. Method for depositing a diffusion barrier for copper interconnect applications
US7842605B1 (en) * 2003-04-11 2010-11-30 Novellus Systems, Inc. Atomic layer profiling of diffusion barrier and metal seed layers
US8298933B2 (en) * 2003-04-11 2012-10-30 Novellus Systems, Inc. Conformal films on semiconductor substrates
US8432037B2 (en) 2004-06-10 2013-04-30 Renesas Electronics Corporation Semiconductor device with a line and method of fabrication thereof
JP4832807B2 (ja) 2004-06-10 2011-12-07 ルネサスエレクトロニクス株式会社 半導体装置
JP4786680B2 (ja) * 2004-06-10 2011-10-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20060009030A1 (en) * 2004-07-08 2006-01-12 Texas Instruments Incorporated Novel barrier integration scheme for high-reliability vias
DE102005024914A1 (de) * 2005-05-31 2006-12-07 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden elektrisch leitfähiger Leitungen in einem integrierten Schaltkreis
US7727888B2 (en) * 2005-08-31 2010-06-01 International Business Machines Corporation Interconnect structure and method for forming the same
JP2007109736A (ja) * 2005-10-11 2007-04-26 Nec Electronics Corp 半導体装置およびその製造方法
JP2007109894A (ja) * 2005-10-13 2007-04-26 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2007180407A (ja) * 2005-12-28 2007-07-12 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP5014632B2 (ja) * 2006-01-13 2012-08-29 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US7528066B2 (en) * 2006-03-01 2009-05-05 International Business Machines Corporation Structure and method for metal integration
DE102006035645B4 (de) * 2006-07-31 2012-03-08 Advanced Micro Devices, Inc. Verfahren zum Ausbilden einer elektrisch leitfähigen Leitung in einem integrierten Schaltkreis
US7510634B1 (en) 2006-11-10 2009-03-31 Novellus Systems, Inc. Apparatus and methods for deposition and/or etch selectivity
US20080128907A1 (en) * 2006-12-01 2008-06-05 International Business Machines Corporation Semiconductor structure with liner
JP5154789B2 (ja) * 2006-12-21 2013-02-27 ルネサスエレクトロニクス株式会社 半導体装置並びに半導体装置の製造方法
KR100790452B1 (ko) * 2006-12-28 2008-01-03 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
US7682966B1 (en) 2007-02-01 2010-03-23 Novellus Systems, Inc. Multistep method of depositing metal seed layers
JP5127251B2 (ja) * 2007-02-01 2013-01-23 パナソニック株式会社 半導体装置の製造方法
US7859113B2 (en) * 2007-02-27 2010-12-28 International Business Machines Corporation Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method
US8030778B2 (en) * 2007-07-06 2011-10-04 United Microelectronics Corp. Integrated circuit structure and manufacturing method thereof
JP2009049178A (ja) * 2007-08-20 2009-03-05 Rohm Co Ltd 半導体装置
US8354751B2 (en) * 2008-06-16 2013-01-15 International Business Machines Corporation Interconnect structure for electromigration enhancement
US7951708B2 (en) * 2009-06-03 2011-05-31 International Business Machines Corporation Copper interconnect structure with amorphous tantalum iridium diffusion barrier
JP5754209B2 (ja) * 2011-03-31 2015-07-29 大日本印刷株式会社 半導体装置の製造方法
US8791014B2 (en) * 2012-03-16 2014-07-29 Globalfoundries Inc. Methods of forming copper-based conductive structures on semiconductor devices
US9842765B2 (en) * 2015-03-16 2017-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US10170358B2 (en) * 2015-06-04 2019-01-01 International Business Machines Corporation Reducing contact resistance in vias for copper interconnects
DE102016125299B4 (de) 2016-01-29 2024-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und Verfahren zu ihrer Herstellung
US10153351B2 (en) 2016-01-29 2018-12-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
CN107564850B (zh) * 2016-07-01 2020-07-07 中芯国际集成电路制造(北京)有限公司 互连结构及其制造方法
JP6934726B2 (ja) * 2017-01-27 2021-09-15 Ｓｐｐテクノロジーズ株式会社 スパッタエッチング用マスク、スパッタエッチング方法及びスパッタエッチング装置
CN107104120B (zh) * 2017-05-24 2019-03-15 成都线易科技有限责任公司 磁感应器件及制造方法
US10249534B2 (en) * 2017-05-30 2019-04-02 Globalfoundries Inc. Method of forming a contact element of a semiconductor device and contact element structure
US10818545B2 (en) * 2018-06-29 2020-10-27 Sandisk Technologies Llc Contact via structure including a barrier metal disc for low resistance contact and methods of making the same
CN110797298A (zh) * 2018-08-03 2020-02-14 群创光电股份有限公司 电子装置及其制备方法
US10685876B2 (en) * 2018-09-18 2020-06-16 International Business Machines Corporation Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability
US11121025B2 (en) * 2018-09-27 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Layer for side wall passivation
CN110718504B (zh) * 2019-09-02 2022-07-29 长江存储科技有限责任公司 插塞结构、三维存储器的形成方法和三维存储器
KR102770334B1 (ko) * 2019-09-25 2025-02-18 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US11424185B2 (en) * 2019-12-30 2022-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US12406877B2 (en) * 2021-04-15 2025-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Homogeneous source/drain contact structure
JP2025077762A (ja) 2023-11-07 2025-05-19 東京エレクトロン株式会社 基板処理方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1109955A (en) * 1914-03-06 1914-09-08 Arthur C Barrett Expansion-bolt.
JPH0714836A (ja) 1993-06-17 1995-01-17 Kawasaki Steel Corp 多層配線構造の半導体装置
JP3027951B2 (ja) * 1997-03-12 2000-04-04 日本電気株式会社 半導体装置の製造方法
JP3660799B2 (ja) * 1997-09-08 2005-06-15 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP2000012684A (ja) * 1998-06-18 2000-01-14 Sony Corp 金属層の形成方法
US6287977B1 (en) 1998-07-31 2001-09-11 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects
JP3317279B2 (ja) 1998-08-17 2002-08-26 セイコーエプソン株式会社 半導体装置の製造方法
JP2000114261A (ja) 1998-10-02 2000-04-21 Seiko Epson Corp 半導体装置とその製造方法
JP2001077195A (ja) 1999-09-07 2001-03-23 Sony Corp 半導体装置
JP2002064139A (ja) * 2000-08-18 2002-02-28 Hitachi Ltd 半導体装置の製造方法
JP2002064138A (ja) 2000-08-18 2002-02-28 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6498091B1 (en) * 2000-11-01 2002-12-24 Applied Materials, Inc. Method of using a barrier sputter reactor to remove an underlying barrier layer
US6436814B1 (en) * 2000-11-21 2002-08-20 International Business Machines Corporation Interconnection structure and method for fabricating same
US6613664B2 (en) * 2000-12-28 2003-09-02 Infineon Technologies Ag Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices
KR100385227B1 (ko) * 2001-02-12 2003-05-27 삼성전자주식회사 구리 다층 배선을 가지는 반도체 장치 및 그 형성방법
US6607977B1 (en) * 2001-03-13 2003-08-19 Novellus Systems, Inc. Method of depositing a diffusion barrier for copper interconnect applications
JP2002299436A (ja) * 2001-03-29 2002-10-11 Toshiba Corp 半導体装置およびその製造方法
JP2003249547A (ja) * 2002-02-22 2003-09-05 Mitsubishi Electric Corp 配線間の接続構造及びその製造方法
US20030203615A1 (en) * 2002-04-25 2003-10-30 Denning Dean J. Method for depositing barrier layers in an opening
US6949461B2 (en) * 2002-12-11 2005-09-27 International Business Machines Corporation Method for depositing a metal layer on a semiconductor interconnect structure
JP2004342702A (ja) * 2003-05-13 2004-12-02 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
JP2005050903A (ja) * 2003-07-30 2005-02-24 Toshiba Corp 半導体装置およびその製造方法
JP4278481B2 (ja) * 2003-10-23 2009-06-17 株式会社ルネサステクノロジ 半導体装置の製造方法
US20050173799A1 (en) * 2004-02-05 2005-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure and method for its fabricating
JP4832807B2 (ja) 2004-06-10 2011-12-07 ルネサスエレクトロニクス株式会社 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9553121B2 (en) 2014-08-28 2017-01-24 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
US20100176511A1 (en) 2010-07-15
US20110171828A1 (en) 2011-07-14
US7709388B2 (en) 2010-05-04
US8222146B2 (en) 2012-07-17
US20070141831A1 (en) 2007-06-21
US7936069B2 (en) 2011-05-03
JP2006024905A (ja) 2006-01-26
US7709955B2 (en) 2010-05-04
US20070138532A1 (en) 2007-06-21
US7192871B2 (en) 2007-03-20
US20050275110A1 (en) 2005-12-15

Similar Documents

Publication Publication Date Title
JP4832807B2 (ja) 半導体装置
CN100424867C (zh) 集成电路的内连线结构
CN1913128B (zh) 双金属镶嵌金属布线图案的形成方法和形成的布线图案
TWI402936B (zh) 用於金屬集成之新穎結構及其製造方法
JP4918778B2 (ja) 半導体集積回路装置の製造方法
US7514354B2 (en) Methods for forming damascene wiring structures having line and plug conductors formed from different materials
US8749064B2 (en) Semiconductor device with a line and method of fabrication thereof
US8466055B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP4764606B2 (ja) 半導体装置およびその製造方法
JP2009026989A (ja) 半導体装置及び半導体装置の製造方法
JP2007042662A (ja) 半導体装置
JP2010507236A (ja) 半導体デバイスおよび相互接続構造体の形成方法
CN1890795B (zh) 使用碳掺杂层和无碳氧化物层的双镶嵌工艺
KR101141214B1 (ko) 반도체 소자의 금속 배선 형성 방법
KR100660915B1 (ko) 반도체 소자의 배선 형성 방법
JP4786680B2 (ja) 半導体装置の製造方法
JP2007115980A (ja) 半導体装置及びその製造方法
JP2007294625A (ja) 半導体装置の製造方法
JP5310721B2 (ja) 半導体装置とその製造方法
CN1913125A (zh) 过孔底接触及其制造方法
JP2007335578A (ja) 半導体装置及びその製造方法
KR100720402B1 (ko) 듀얼 다마센 공정을 이용한 금속 배선 형성 방법
JP2007194566A (ja) 半導体装置およびその製造方法
US20080057711A1 (en) Reduction of punch-thru defects in damascene processing
KR20100073779A (ko) 반도체 소자의 금속배선 및 그 제조 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080512

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080512

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100331

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100511

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100518

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100712

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110628

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110822

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110913

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110921

R150 Certificate of patent or registration of utility model

Ref document number: 4832807

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140930

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees