JP4511092B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
- Publication number
- JP4511092B2 JP4511092B2 JP2001376993A JP2001376993A JP4511092B2 JP 4511092 B2 JP4511092 B2 JP 4511092B2 JP 2001376993 A JP2001376993 A JP 2001376993A JP 2001376993 A JP2001376993 A JP 2001376993A JP 4511092 B2 JP4511092 B2 JP 4511092B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- semiconductor
- manufacturing
- silicon
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- High Energy & Nuclear Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001376993A JP4511092B2 (ja) | 2000-12-11 | 2001-12-11 | 半導体素子の製造方法 |
| US10/011,292 US20020090772A1 (en) | 2000-12-11 | 2001-12-11 | Method for manufacturing semiconductor lamination, method for manufacturing lamination, semiconductor device, and electronic equipment |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000-376293 | 2000-12-11 | ||
| JP2000376293 | 2000-12-11 | ||
| JP2001032513 | 2001-02-08 | ||
| JP2001-32513 | 2001-02-08 | ||
| JP2001376993A JP4511092B2 (ja) | 2000-12-11 | 2001-12-11 | 半導体素子の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002313721A JP2002313721A (ja) | 2002-10-25 |
| JP2002313721A5 JP2002313721A5 (enExample) | 2005-07-14 |
| JP4511092B2 true JP4511092B2 (ja) | 2010-07-28 |
Family
ID=27345407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001376993A Expired - Fee Related JP4511092B2 (ja) | 2000-12-11 | 2001-12-11 | 半導体素子の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20020090772A1 (enExample) |
| JP (1) | JP4511092B2 (enExample) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050195318A1 (en) * | 2003-02-07 | 2005-09-08 | Takahiro Komatsu | Organic information reading unit and information reading device using the same |
| JP4096877B2 (ja) * | 2003-02-07 | 2008-06-04 | 松下電器産業株式会社 | 情報読み取り素子及びそれを用いた情報読み取り装置 |
| US20040262683A1 (en) * | 2003-06-27 | 2004-12-30 | Bohr Mark T. | PMOS transistor strain optimization with raised junction regions |
| JP2005032793A (ja) * | 2003-07-08 | 2005-02-03 | Matsushita Electric Ind Co Ltd | 有機光電変換素子 |
| JP2005032852A (ja) * | 2003-07-09 | 2005-02-03 | Matsushita Electric Ind Co Ltd | 有機光電変換素子 |
| US7045836B2 (en) * | 2003-07-31 | 2006-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having a strained region and a method of fabricating same |
| US7495267B2 (en) * | 2003-09-08 | 2009-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having a strained region and a method of fabricating same |
| WO2005096403A2 (en) * | 2004-03-31 | 2005-10-13 | Matsushita Electric Industrial Co., Ltd. | Organic photoelectric conversion element utilizing an inorganic buffer layer placed between an electrode and the active material |
| US7202145B2 (en) * | 2004-06-03 | 2007-04-10 | Taiwan Semiconductor Manufacturing Company | Strained Si formed by anneal |
| WO2006034672A2 (de) * | 2004-09-30 | 2006-04-06 | Forschungszentrun Rossendorf E.V. | Verfahren zur behandlung von halbleitersubstraten, die mittels intensiven lichtimpulsen ausgeheilt werden |
| DE102005036669A1 (de) * | 2005-08-04 | 2007-02-08 | Forschungszentrum Rossendorf E.V. | Verfahren zur Behandlung von Halbleitersubstratoberflächen, die mittels intensiven Lichtimpulsen kurzzeitig aufgeschmolzen werden |
| US8138066B2 (en) * | 2008-10-01 | 2012-03-20 | International Business Machines Corporation | Dislocation engineering using a scanned laser |
| JP2011187506A (ja) * | 2010-03-04 | 2011-09-22 | Sony Corp | 薄膜トランジスタおよびその製造方法、並びに表示装置 |
| WO2012079113A1 (en) * | 2010-12-15 | 2012-06-21 | Newsouth Innovations Pty Limited | A method of forming a germanium layer on a silicon substrate and a photovoltaic device including a germanium layer |
| US20160126337A1 (en) * | 2013-05-31 | 2016-05-05 | Hitachi Kokusai Electric Inc. | Substrate processing apparatus, semiconductor device manufacturing method, and substrate processing method |
| JP6486735B2 (ja) * | 2015-03-17 | 2019-03-20 | 東芝メモリ株式会社 | 半導体製造方法および半導体製造装置 |
| CN104934330A (zh) * | 2015-05-08 | 2015-09-23 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制备方法、阵列基板和显示面板 |
| EP3252800A1 (en) * | 2016-05-31 | 2017-12-06 | Laser Systems & Solutions of Europe | Deep junction electronic device and process for manufacturing thereof |
| CN114008748B (zh) * | 2019-06-27 | 2025-06-10 | 三菱电机株式会社 | 光半导体装置的制造方法 |
Family Cites Families (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4868614A (en) * | 1981-02-09 | 1989-09-19 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting semiconductor device matrix with non-single-crystalline semiconductor |
| JPH0656887B2 (ja) * | 1982-02-03 | 1994-07-27 | 株式会社日立製作所 | 半導体装置およびその製法 |
| US4914053A (en) * | 1987-09-08 | 1990-04-03 | Texas Instruments Incorporated | Heteroepitaxial selective-area growth through insulator windows |
| US5063166A (en) * | 1988-04-29 | 1991-11-05 | Sri International | Method of forming a low dislocation density semiconductor device |
| US4962051A (en) * | 1988-11-18 | 1990-10-09 | Motorola, Inc. | Method of forming a defect-free semiconductor layer on insulator |
| JPH0828520B2 (ja) * | 1991-02-22 | 1996-03-21 | 株式会社半導体エネルギー研究所 | 薄膜半導体装置およびその製法 |
| TW211621B (enExample) * | 1991-07-31 | 1993-08-21 | Canon Kk | |
| JP3250673B2 (ja) * | 1992-01-31 | 2002-01-28 | キヤノン株式会社 | 半導体素子基体とその作製方法 |
| US5254480A (en) * | 1992-02-20 | 1993-10-19 | Minnesota Mining And Manufacturing Company | Process for producing a large area solid state radiation detector |
| JP2775563B2 (ja) * | 1992-03-23 | 1998-07-16 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| US5399231A (en) * | 1993-10-18 | 1995-03-21 | Regents Of The University Of California | Method of forming crystalline silicon devices on glass |
| US5461243A (en) * | 1993-10-29 | 1995-10-24 | International Business Machines Corporation | Substrate for tensilely strained semiconductor |
| JP2646977B2 (ja) * | 1993-11-29 | 1997-08-27 | 日本電気株式会社 | 順スタガ型薄膜トランジスタの製造方法 |
| JP3108296B2 (ja) * | 1994-01-26 | 2000-11-13 | 三洋電機株式会社 | 表示装置の製造方法 |
| WO1997045827A1 (en) * | 1996-05-28 | 1997-12-04 | The Trustees Of Columbia University In The City Of New York | Crystallization processing of semiconductor film regions on a substrate, and devices made therewith |
| US5686744A (en) * | 1996-06-17 | 1997-11-11 | Northern Telecom Limited | Complementary modulation-doped field-effect transistors |
| US6399970B2 (en) * | 1996-09-17 | 2002-06-04 | Matsushita Electric Industrial Co., Ltd. | FET having a Si/SiGeC heterojunction channel |
| US5847419A (en) * | 1996-09-17 | 1998-12-08 | Kabushiki Kaisha Toshiba | Si-SiGe semiconductor device and method of fabricating the same |
| DE59707274D1 (de) * | 1996-09-27 | 2002-06-20 | Infineon Technologies Ag | Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung |
| US6329270B1 (en) * | 1997-03-07 | 2001-12-11 | Sharp Laboratories Of America, Inc. | Laser annealed microcrystalline film and method for same |
| JPH10270685A (ja) * | 1997-03-27 | 1998-10-09 | Sony Corp | 電界効果トランジスタとその製造方法、半導体装置とその製造方法、その半導体装置を含む論理回路および半導体基板 |
| US5891769A (en) * | 1997-04-07 | 1999-04-06 | Motorola, Inc. | Method for forming a semiconductor device having a heteroepitaxial layer |
| JPH1140501A (ja) * | 1997-05-20 | 1999-02-12 | Fujitsu Ltd | 半導体装置の製造方法及び半導体装置 |
| JP3443343B2 (ja) * | 1997-12-03 | 2003-09-02 | 松下電器産業株式会社 | 半導体装置 |
| FR2773177B1 (fr) * | 1997-12-29 | 2000-03-17 | France Telecom | Procede d'obtention d'une couche de germanium ou silicium monocristallin sur un substrat de silicium ou germanium monocristallin, respectivement, et produits multicouches obtenus |
| US6492694B2 (en) * | 1998-02-27 | 2002-12-10 | Micron Technology, Inc. | Highly conductive composite polysilicon gate for CMOS integrated circuits |
| US6331476B1 (en) * | 1998-05-26 | 2001-12-18 | Mausushita Electric Industrial Co., Ltd. | Thin film transistor and producing method thereof |
| JP3403076B2 (ja) * | 1998-06-30 | 2003-05-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US6475815B1 (en) * | 1998-12-09 | 2002-11-05 | Matsushita Electric Industrial Co., Ltd. | Method of measuring temperature, method of taking samples for temperature measurement and method for fabricating semiconductor device |
| US6369438B1 (en) * | 1998-12-24 | 2002-04-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US6607948B1 (en) * | 1998-12-24 | 2003-08-19 | Kabushiki Kaisha Toshiba | Method of manufacturing a substrate using an SiGe layer |
| US6521492B2 (en) * | 2000-06-12 | 2003-02-18 | Seiko Epson Corporation | Thin-film semiconductor device fabrication method |
| US6461945B1 (en) * | 2000-06-22 | 2002-10-08 | Advanced Micro Devices, Inc. | Solid phase epitaxy process for manufacturing transistors having silicon/germanium channel regions |
| US6403981B1 (en) * | 2000-08-07 | 2002-06-11 | Advanced Micro Devices, Inc. | Double gate transistor having a silicon/germanium channel region |
| JP2002093735A (ja) * | 2000-09-13 | 2002-03-29 | Sony Corp | 半導体装置の製造方法 |
| US7112844B2 (en) * | 2001-04-19 | 2006-09-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
-
2001
- 2001-12-11 US US10/011,292 patent/US20020090772A1/en not_active Abandoned
- 2001-12-11 JP JP2001376993A patent/JP4511092B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002313721A (ja) | 2002-10-25 |
| US20020090772A1 (en) | 2002-07-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4511092B2 (ja) | 半導体素子の製造方法 | |
| TW579602B (en) | Semiconductor device and method for manufacturing same | |
| JP4092541B2 (ja) | 半導体薄膜の形成方法及び半導体装置の製造方法 | |
| TW577174B (en) | Method and apparatus for forming a thin semiconductor film, method and apparatus for producing a semiconductor device, and electro-optical apparatus | |
| JP4323724B2 (ja) | 半導体装置の製造方法 | |
| JP2002231628A (ja) | 半導体薄膜の形成方法及び半導体装置の製造方法、これらの方法の実施に使用する装置、並びに電気光学装置 | |
| JP2002151410A (ja) | 結晶質半導体材料の製造方法および半導体装置の製造方法 | |
| JP2004134577A (ja) | 半導体薄膜の製造方法、薄膜トランジスタ、半導体装置、薄膜太陽電池、複合半導体装置の製造方法、電気光学装置及び電子機器 | |
| JP2003197526A (ja) | 半導体装置の製造方法、半導体装置、表示装置、および電子機器 | |
| JP3319963B2 (ja) | 半導体装置の製造方法 | |
| JPH10173196A (ja) | 半導体装置およびその製造方法 | |
| JPH10189449A (ja) | 結晶性半導体膜の製造方法、および薄膜トランジスタの製造方法 | |
| JP5232360B2 (ja) | 半導体装置及びその製造方法 | |
| JP2005203800A (ja) | 半導体装置の製造方法、アクティブマトリクス基板、及び電子機器 | |
| JP4123410B2 (ja) | 半導体素子の製造方法 | |
| JP2003100637A (ja) | 半導体膜の結晶化方法、薄膜トランジスタの製造方法、電気光学装置及び電子機器 | |
| JP4780860B2 (ja) | 半導体装置の作製方法 | |
| JP2004288864A (ja) | 薄膜半導体、薄膜トランジスタの製造方法、電気光学装置及び電子機器 | |
| JP4701467B2 (ja) | 多結晶膜の製造方法および半導体装置の製造方法 | |
| JP4200530B2 (ja) | 薄膜トランジスタの製造方法 | |
| JP2003174036A (ja) | 薄膜トランジスタの製造方法及び薄膜トランジスタ | |
| JP2003100638A (ja) | 半導体薄膜及び薄膜トランジスタの製造方法、電気光学装置及び電子機器 | |
| JP2003124231A (ja) | 薄膜トランジスタの製造方法、電子機器、および電気光学装置 | |
| JP2011216665A (ja) | 結晶性半導体膜の形成方法、および、半導体デバイスの製造方法 | |
| JP2002270843A (ja) | 薄膜トランジスタの製造方法、不純物の活性化方法及び薄膜トランジスタ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20041110 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20041110 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060616 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060629 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060824 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20061219 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070219 |
|
| A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20070313 |
|
| A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20070420 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100309 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100506 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140514 Year of fee payment: 4 |
|
| LAPS | Cancellation because of no payment of annual fees |