JP4501464B2 - 厚膜回路基板、その製造方法および集積回路装置 - Google Patents
厚膜回路基板、その製造方法および集積回路装置 Download PDFInfo
- Publication number
- JP4501464B2 JP4501464B2 JP2004057401A JP2004057401A JP4501464B2 JP 4501464 B2 JP4501464 B2 JP 4501464B2 JP 2004057401 A JP2004057401 A JP 2004057401A JP 2004057401 A JP2004057401 A JP 2004057401A JP 4501464 B2 JP4501464 B2 JP 4501464B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- paste
- hole
- base material
- thick film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/035—Paste overlayer, i.e. conductive paste or solder paste over conductive layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09981—Metallised walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
- H05K3/247—Finish coating of conductors by using conductive pastes, inks or powders
- H05K3/248—Finish coating of conductors by using conductive pastes, inks or powders fired compositions for inorganic substrates
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
銀系の導体は、エレクトロマイグレーションが発生しやすく、信頼性に問題があった。このため、パラジウムを添加した銀系の導体が考案されているが、導電性が低下するという問題があった。
本形態の厚膜回路基板は、基材と、導体層と、導通部と、から構成される。
なお、本形態及び本発明の厚膜回路基板において、導体層、導通部等の部材の焼成温度は、焼成炉の炉内環境の設定温度であり、局部的に設定温度以上となってもよい。
従来公知の方法を用いて、スルーホールが形成されたアルミナセラミックスよりなる板状の基材1を作成した。基材1のスルーホール10の近傍の断面を図1に示した。
本参考例は、導通部を形成するためのAg系導体ペーストの塗布を、複数回行った以外は、参考例1と同様に厚膜回路基板を製造した。
まず、参考例1と同様に基材1を作成した。
まず、参考例1と同様に基材1を作成し、基材1のスルーホール10の内周面にAg系導体ペースト2を塗布し、乾燥させた。基材1のスルーホール10の近傍の断面を図13に示した。
まず、参考例3と同様に基材1を作成し、基材1のスルーホール10の内周面にAg系導体ペースト2を塗布し、乾燥させた。
まず、参考例3と同様に基材1を作成し、基材1のスルーホール10の内周面にAg系導体ペースト2を塗布し、乾燥させた。
10a…スルーホール内周面 11、13…基材表面
12、14…スルーホール開口部
2,2’…Ag系導体ペースト、導通部
3…Cu系導体ペースト、導体層
4…抵抗体ペースト、抵抗体
5…ボンディングペースト、ボンディングパッド
6…保護ガラス
7…パワー素子 71…アルミボンディングワイヤ
8…接着剤
Claims (6)
- 所定位置に貫通したスルーホールを有する絶縁性の基材と、
所定の回路パターンに応じて該基材の両面に形成された導体層と、
該基材の両面に形成された該導体層を電気的に導通する該スルーホールの内部に形成された導通部と、
を有する厚膜回路基板において、
該導通部が、該基材の両面から該スルーホールの内部に銀系のペーストを塗布、焼成して形成され、
該スルーホールの内部に、少なくとも一方の開口部を閉塞する導体がもうけられ、
該スルーホールの該一方の開口部上に電子部品が載置されることを特徴とする厚膜回路基板。 - 前記導体層が750℃以下で焼成された銅系の導体よりなり、前記導通部が銀系の導体よりなる請求項1記載の厚膜回路基板。
- 前記導体は、前記導体層よりなる請求項1記載の厚膜回路基板。
- 前記導通部は、前記銀系のペーストを前記スルーホールの内周面に複数回塗布して形成された請求項1記載の厚膜回路基板。
- 所定位置に貫通したスルーホールを有する絶縁性の基材と、所定の回路パターンに応じて該基材の両面に形成された導体層と、該基材の両面に形成された該導体層を電気的に導通する該スルーホールの内部に形成された導通部と、を有し、該導通部が該基材の両面側から該スルーホールの内部に銀系のペーストを塗布、焼成して形成され、該スルーホールの内部に、少なくとも一方の開口部を閉塞する導体がもうけられた厚膜回路基板と、
該厚膜回路基板上に載置された電気素子と、
を有することを特徴とする集積回路装置。 - 前記導通部は、前記銀系のペーストを前記スルーホールの内周面に複数回塗布して形成された請求項5記載の集積回路装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004057401A JP4501464B2 (ja) | 2003-04-25 | 2004-03-02 | 厚膜回路基板、その製造方法および集積回路装置 |
US10/831,229 US7417318B2 (en) | 2003-04-25 | 2004-04-26 | Thick film circuit board, method of producing the same and integrated circuit device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003122426 | 2003-04-25 | ||
JP2004057401A JP4501464B2 (ja) | 2003-04-25 | 2004-03-02 | 厚膜回路基板、その製造方法および集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004343056A JP2004343056A (ja) | 2004-12-02 |
JP4501464B2 true JP4501464B2 (ja) | 2010-07-14 |
Family
ID=33302264
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004057401A Expired - Fee Related JP4501464B2 (ja) | 2003-04-25 | 2004-03-02 | 厚膜回路基板、その製造方法および集積回路装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7417318B2 (ja) |
JP (1) | JP4501464B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006055996A2 (de) * | 2004-11-23 | 2006-06-01 | Nessler Medizintechnik Gmbh | Verfahren zur durchkontaktierung eines elektrisch isolierenden trägermaterials |
JP2013232483A (ja) * | 2012-04-27 | 2013-11-14 | Koito Mfg Co Ltd | 回路基板及び回路基板の製造方法 |
CN103237411A (zh) * | 2013-05-06 | 2013-08-07 | 田茂福 | 用细导线排制作的led单面线路板和方法 |
WO2019044752A1 (ja) * | 2017-08-29 | 2019-03-07 | 京セラ株式会社 | 回路基板およびこれを備える電子装置 |
JP7191982B2 (ja) | 2018-12-26 | 2022-12-19 | 京セラ株式会社 | 配線基板、電子装置及び電子モジュール |
US11851321B2 (en) | 2021-03-01 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Micro-electro mechanical system and manufacturing method thereof |
US11990015B2 (en) * | 2021-09-22 | 2024-05-21 | Honeywell International Inc. | Point heat detectors based on surface mounted thermistors |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62265796A (ja) * | 1986-05-14 | 1987-11-18 | 株式会社住友金属セラミックス | セラミツク多層配線基板およびその製造法 |
JPS63226995A (ja) * | 1987-03-16 | 1988-09-21 | 北陸電気工業株式会社 | 回路基板のスル−ホ−ル接続部形成方法 |
JPH0432297A (ja) * | 1990-05-29 | 1992-02-04 | Kyocera Corp | 多層配線基板及びその製造方法 |
JPH04199897A (ja) * | 1990-11-29 | 1992-07-21 | Murata Mfg Co Ltd | スルーホールの形成方法 |
JPH05335748A (ja) * | 1992-05-28 | 1993-12-17 | Kyocera Corp | 多層回路基板 |
JPH06224560A (ja) * | 1993-01-22 | 1994-08-12 | Nippondenso Co Ltd | セラミック多層配線基板 |
JPH088505A (ja) * | 1994-06-22 | 1996-01-12 | Sumitomo Kinzoku Ceramics:Kk | 低温焼成セラミック回路基板およびその製造法 |
JPH08316601A (ja) * | 1995-05-15 | 1996-11-29 | Tokuyama Corp | 回路基板及びその製造方法 |
JPH0964502A (ja) * | 1995-08-23 | 1997-03-07 | Hitachi Ltd | 厚膜集積回路 |
JPH11251740A (ja) * | 1998-02-27 | 1999-09-17 | Fuji Xerox Co Ltd | プリント基板およびその製造方法 |
JP2002246715A (ja) * | 2001-02-15 | 2002-08-30 | Taiyo Yuden Co Ltd | 基板,基板の製造方法及び基板の接続構造 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11177016A (ja) | 1997-12-15 | 1999-07-02 | Denso Corp | 混成集積回路装置 |
JP3603663B2 (ja) | 1999-04-28 | 2004-12-22 | 株式会社デンソー | 厚膜回路基板とその製造方法 |
US6639360B2 (en) * | 2001-01-31 | 2003-10-28 | Gentex Corporation | High power radiation emitter device and heat dissipating package for electronic components |
US6630743B2 (en) * | 2001-02-27 | 2003-10-07 | International Business Machines Corporation | Copper plated PTH barrels and methods for fabricating |
JP3734731B2 (ja) * | 2001-09-06 | 2006-01-11 | 株式会社ノリタケカンパニーリミテド | セラミック電子部品及びその製造方法 |
JP4202641B2 (ja) * | 2001-12-26 | 2008-12-24 | 富士通株式会社 | 回路基板及びその製造方法 |
JP4488684B2 (ja) * | 2002-08-09 | 2010-06-23 | イビデン株式会社 | 多層プリント配線板 |
US20040195669A1 (en) * | 2003-04-07 | 2004-10-07 | Wilkins Wendy Lee | Integrated circuit packaging apparatus and method |
US7042098B2 (en) * | 2003-07-07 | 2006-05-09 | Freescale Semiconductor,Inc | Bonding pad for a packaged integrated circuit |
-
2004
- 2004-03-02 JP JP2004057401A patent/JP4501464B2/ja not_active Expired - Fee Related
- 2004-04-26 US US10/831,229 patent/US7417318B2/en active Active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62265796A (ja) * | 1986-05-14 | 1987-11-18 | 株式会社住友金属セラミックス | セラミツク多層配線基板およびその製造法 |
JPS63226995A (ja) * | 1987-03-16 | 1988-09-21 | 北陸電気工業株式会社 | 回路基板のスル−ホ−ル接続部形成方法 |
JPH0432297A (ja) * | 1990-05-29 | 1992-02-04 | Kyocera Corp | 多層配線基板及びその製造方法 |
JPH04199897A (ja) * | 1990-11-29 | 1992-07-21 | Murata Mfg Co Ltd | スルーホールの形成方法 |
JPH05335748A (ja) * | 1992-05-28 | 1993-12-17 | Kyocera Corp | 多層回路基板 |
JPH06224560A (ja) * | 1993-01-22 | 1994-08-12 | Nippondenso Co Ltd | セラミック多層配線基板 |
JPH088505A (ja) * | 1994-06-22 | 1996-01-12 | Sumitomo Kinzoku Ceramics:Kk | 低温焼成セラミック回路基板およびその製造法 |
JPH08316601A (ja) * | 1995-05-15 | 1996-11-29 | Tokuyama Corp | 回路基板及びその製造方法 |
JPH0964502A (ja) * | 1995-08-23 | 1997-03-07 | Hitachi Ltd | 厚膜集積回路 |
JPH11251740A (ja) * | 1998-02-27 | 1999-09-17 | Fuji Xerox Co Ltd | プリント基板およびその製造方法 |
JP2002246715A (ja) * | 2001-02-15 | 2002-08-30 | Taiyo Yuden Co Ltd | 基板,基板の製造方法及び基板の接続構造 |
Also Published As
Publication number | Publication date |
---|---|
US7417318B2 (en) | 2008-08-26 |
US20040212085A1 (en) | 2004-10-28 |
JP2004343056A (ja) | 2004-12-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3237258B2 (ja) | セラミック多層配線基板 | |
JP4501464B2 (ja) | 厚膜回路基板、その製造方法および集積回路装置 | |
JP2505739B2 (ja) | 電子装置用ハウジング | |
KR100807217B1 (ko) | 세라믹 부품 및 그 제조방법 | |
JPH0210571B2 (ja) | ||
US6690558B1 (en) | Power resistor and method for making | |
JP6172966B2 (ja) | 光学素子用基板及び光学素子パッケージの製造方法並びに光学素子用基板及び光学素子パッケージ | |
JP2000312062A (ja) | 厚膜回路基板とその製造方法 | |
JP4540223B2 (ja) | 電子部品搭載基板 | |
JP2002373961A (ja) | 樹脂封止型電子装置 | |
JPH0595071U (ja) | 厚膜回路基板 | |
JP2003229518A (ja) | 回路装置 | |
JP3896333B2 (ja) | 厚膜多層配線基板 | |
JPS6153852B2 (ja) | ||
JP2734404B2 (ja) | セラミック配線基板およびその製造方法 | |
WO2006032836A1 (en) | Thick-film hybrid production process | |
JP3030605B2 (ja) | 半導体装置 | |
JP3931360B2 (ja) | 厚膜多層基板 | |
JPH11126853A (ja) | 厚膜回路基板の製造方法 | |
JP2605157B2 (ja) | モールドパッケージ型厚膜ハイブリッドic | |
JP4423053B2 (ja) | 配線基板 | |
JPH0964227A (ja) | セラミックパッケージおよびその製造方法 | |
JP2023031643A (ja) | 配線基板およびその製造方法 | |
JPH07183661A (ja) | 厚膜多層基板 | |
JPS6229194A (ja) | 厚膜基板装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060413 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20081216 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081219 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090213 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090818 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091015 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100330 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100412 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 4501464 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130430 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130430 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140430 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |