JP4472023B1 - 電子デバイス用基板、電子デバイス用積層体、電子デバイス及びそれらの製造方法 - Google Patents

電子デバイス用基板、電子デバイス用積層体、電子デバイス及びそれらの製造方法 Download PDF

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JP4472023B1
JP4472023B1 JP2009281839A JP2009281839A JP4472023B1 JP 4472023 B1 JP4472023 B1 JP 4472023B1 JP 2009281839 A JP2009281839 A JP 2009281839A JP 2009281839 A JP2009281839 A JP 2009281839A JP 4472023 B1 JP4472023 B1 JP 4472023B1
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electronic device
magnetic
substrate
substrates
manufacturing
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JP2011124433A (ja
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重信 関根
由莉奈 関根
良治 桑名
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有限会社ナプラ
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Priority to US12/943,447 priority patent/US8580581B2/en
Priority to CN2010105474932A priority patent/CN102142379A/zh
Priority to EP20100252042 priority patent/EP2348526A3/en
Priority to TW099142915A priority patent/TWI436452B/zh
Priority to KR1020100125607A priority patent/KR20110066866A/ko
Publication of JP2011124433A publication Critical patent/JP2011124433A/ja
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Abstract

【課題】TSV技術を適用して電子デバイスを製造に当たり、積層時位置合せを、簡単、かつ、確実に、しかも高精度で実行し得る製造方法、そのための基板、積層体及び電子デバイスを提供すること。
【解決手段】複数枚ｒの基板ＷＦ１〜ＷＦｒを位置合せして積層するに当たり、外部から磁界Ｈを印加し、積層されて隣接する基板ＷＦ１〜ＷＦｒの磁性膜４１−５２の間に磁気的吸引力Ｆｍを生じさせ、磁気的吸引力Ｆｍにより、基板ＷＦ１〜ＷＦｒに設けられた縦導体３を位置合せする。
【選択図】図１

Description

本発明は、電子デバイス用基板、電子デバイス用積層体、電子デバイス及びそれらの製造方法に関する。
電子デバイスの例としては、例えば、各種スケールの集積回路、各種半導体素子もしくはそのチップ等を挙げることができる。この種の電子デバイスにおいて、その三次元回路配置を実現する手法として、回路基板上にＬＳＩを配置し、その間をワイヤ・ボンディングなどの手段で接続する方法がとられてきた。しかし、この方法では、実装面積がＬＳＩの数とともに増加し、配線長の増加から、ＬＳＩ間の信号遅延が大きくなる。
そこで、回路基板に多数の貫通電極を設けておき、この回路基板を積層するＴＳＶ（Through-Silicon-Via)技術が提案されている。特許文献１〜４には、ＴＳＶ技術に不可欠な貫通電極形成技術が開示されている。ワイヤ・ボンディングに対するＴＳＶ技術の優位性は、次のように言われている。
まず、ワイヤ・ボンディングでは、１００〜２００本と接続本数が限られていたが、ＴＳＶ技術を使えば、μｍオーダの間隔で接続用貫通電極を配列できるため、数千本単位での接続本数が可能となる。
また、接続距離が最短になるので、ノイズを受けにくくなること、寄生容量や抵抗が小さくて済むため遅延や減衰、波形の劣化が少なくなること、増幅や静電破壊保護のための余分な回路が不要になること、これらによって、回路の高速動作と低消費電力化が実現されることなどの利点が得られる。
ＴＳＶ技術を用いることにより、アナログやデジタルの回路、ＤＲＡＭのようなメモリ回路、ＣＰＵのようなロジック回路などを含む電子デバイスは勿論のこと、アナログ高周波回路と低周波で低消費電力の回路といった異種の回路を、別々のプロセスによって作り、それらを積層した電子デバイスを得ることもできる。
３次元集積回路（３D IC）にＴＳＶ技術を使用すれば、大量の機能を小さな占有面積の中に詰め込めるようになる。加えて、素子同士の重要な電気経路が劇的に短く出来るために、処理の高速化が導かれる。
ところで、ＴＳＶ技術では、貫通電極を形成した基板を積層してゆくことになるので、積層される基板間で貫通電極を位置合せすることが必要なる。従来、位置合せに当たっては、画像処理技術を使用していた。しかし、貫通電極は、μｍオーダの間隔で配列されており、画像処理技術によって、正確に位置合せすることが困難である。仮に、画面上での位置合せが完了したとしても、実プロセスでは、基板間の位置ずれを生じる危険性がある。
特開平１１−２９８１３８号公報 特開２０００−２２８４１０号公報 特開２００２−１５８１９１号公報 特開２００３−２５７８９１号公報 特開２００６−１１１８９６号公報
本発明の課題は、ＴＳＶ技術を適用して電子デバイスを製造に当たり、積層時位置合せを、簡単、かつ、確実に、しかも高精度で実行し得る製造方法、そのための基板、積層体及び電子デバイスを提供することである。
上述した課題を解決するため、本発明は、複数枚の基板を位置合せして積層する工程を含む電子デバイスの製造方法にあって、前記複数枚の基板のそれぞれは、複数の縦導体と、磁性膜とを有する。前記縦導体は、基板面に対して整列して分布されている。前記磁性膜は、前記縦導体に対して予め定められた位置関係を有して、前記基板面に設けられている。
前記複数枚の基板を位置合せするに当たり、外部から磁界を印加し、積層されて隣接する前記基板の前記磁性膜の間に磁気的吸引力を生じさせ、前記磁気的吸引力により前記縦導体を位置合せする。即ち、磁性膜を、磁気的な位置合せマーカとして機能させる。
上述したように、本発明では、基板面の所定位置に、磁性膜を、縦導体に対して予め定められた位置関係を有して設けておき、隣接する基板の磁性膜の間に磁気的吸引力を生じさせ、磁気的吸引力により縦導体を位置合せするから、ＴＳＶ技術を適用して電子デバイスを製造に当たり、従来用いられていた画像処理との対比において、縦導体の積層時位置合せを、簡単、かつ、確実に、高精度に実行し得る。
しかも、磁界が印加されている限り、積層された基板間に磁気的吸引力が作用するので、積層中又はその後のプロセス、例えば接合プロセス中に基板に位置ずれを生じることがない。
前記縦導体は、基板を貫通する貫通孔内に充填された貫通電極であってもよいし、底部が閉じられている盲孔内に充填された電極であってもよい。
前記磁性膜は、前記縦導体の少なくとも一端面上に設けることができる。この場合は、磁性膜が、縦導体の一部を構成することになる。これとは異なって、磁性膜は、前記縦導体の外側に位置に設けられていてもよい。
前記磁性膜は、具体的には、Ｎｉ、ＣｏもしくはＦｅ又はそれらの合金を含むことができる。
本発明は、更に、上述した製造方法に適用される基板、その基板を積層した積層体、更には、上述した製造法又は積層体を用いた電子デバイスを開示する。
本発明の他の目的、構成及び利点については、添付図面を参照し、更に詳しく説明する。但し、添付図面は、単なる例示に過ぎない。
本発明に係る電子デバイスの製造方法を示す図である。 図１に示した製造方法の実施に用いられる基板の一部を示す平面図ある。 図１に示した製造方法の実施に用いられる基板の一部を示す平面図ある。 図１に示した製造方法を経て得られた積層体又は電子デバイスを示す図である。 本発明に係る電子デバイスの製造方法に係る他の実施形態を示す図である。 図５に示した製造方法の実施に用いられる基板の一例を示す平面図である。
図１を参照すると、複数枚ｒ（ｒは２以上の自然数）の基板ＷＦ１〜ＷＦｒを位置合せして積層する工程を含む電子デバイスの製造方法が図示されている。図１には、簡単な構成の基板が示されているのみであるが、実際には、実現されるべき電子デバイスの種類に応じた機能、及び、構造を満たすべく、より複雑な構造がとられる。
基板ＷＦ１〜ＷＦｒは、各種半導体基板、誘電体基板、絶縁基板もしくは磁性基板またはそれらの複合基板などで構成される。実施例の基板ＷＦ１〜ＷＦｒは、シリコンウエハであり、シリコン層でなる支持層１の一面側に、ＣＭＯＳ等の半導体回路６を有する機能層２を積層した構造となっている。
基板ＷＦ１〜ＷＦｒのそれぞれは、図２及び図３にも図示するように、複数の縦導体３と、磁性膜４１とを有する。縦導体３は、基板面に対して整列して分布されている。縦導体３は、基板ＷＦ１〜ＷＦｒを貫通する貫通孔内に充填された貫通電極であってもよいし、底部が閉じられている盲孔内に充填された電極であってもよい。実施の形態に示す縦導体３は、支持層１を貫通する貫通電極であって、半導体回路６のそれぞれ毎に備えられ、一端が半導体回路６に接続され、半導体回路６に対する接続配線として機能する。
縦導体３及び半導体回路６は、図2に示すように、基板面に想定されるＸＹ平面でみて、Ｘ方向及びＹ方向に所定の配置ピッチＬｘ、Ｌｙをもって、例えば、マトリクス状に整列して配置される。縦導体３のディメンションは、一例として例示すると、配置ピッチＬｘ、Ｌｙ、が４〜１００μｍの範囲、最小部の径が０．５〜２５μｍの範囲である。もっとも、配置ピッチＬｘ、Ｌｙは、一定寸法である必要はない。
通常、Ｘ方向及びＹ方向のそれぞれにおいて、複数個の縦導体３及び半導体回路６を含む領域が、電子デバイスとしての１チップ領域Ｑ１を構成する。１チップ領域Ｑ１に含まれる縦導体３及び半導体回路６の個数は、実施の形態では９個であるが、電子デバイスに応じて変化する任意数である。１チップ領域Ｑ１から、電子デバイスの個品として取り出すためには、Ｘ方向切断位置Ｃｘ及びＹ方向切断位置Ｃｙで切断する。
縦導体３は、縦導体３はメッキ法、溶融金属充填法又は導電ペースト充填法など、公知技術の適用によって形成することができる。縦導体３を組成する材料は、形成方法によって異なる。メッキ法の場合には、おもにＣｕメッキ膜が用いられ、溶融金属充填法の場合には、錫（Ｓｎ)を主成分とする金属材料によって構成され、必要に応じて、インジウム（Ｉｎ）、アルミニウム（Ａｌ)又はビスマス（Ｂｉ)などを含有していてもよい。
縦導体３を形成するには、何れの形成方法をとるにせよ、その前に縦孔（貫通ビア）を形成する必要がある。縦孔（貫通ビア）は、ＣＶＤ法、レーザ穿孔法など、公知の技術によって形成することができる。縦孔（貫通ビア）の形成タイミングとしては、半導体回路6を形成する前に縦孔（貫通ビア）を形成するビア・ファーストと称される手法と、半導体回路6を形成した後に縦孔（貫通ビア）を形成するビア・ラストと称される手法があり、何れの手法を適用してもよい。
磁性膜４１は、縦導体３の一端面上に付着されており、磁性膜４１の表面には、接合膜４２が付着されている。磁性膜４１は、本発明の特徴部分の一つであり、磁気的な位置合せマーカとして機能する。磁性膜４１は、Ｎｉ、ＣｏもしくはＦｅ又はそれらの合金を含む。
接合膜４２は、積層時接合を担う部分であって、Ｓｎ、Ａｇ、Ａｕ、Ｃｕ、Ａｌ、ＩｎまたはＢｉ等から選択された金属材料によって構成される。図示では、一層表示となっているが、電気的特性改善、接合強度向上、溶融特性の改善などの観点から、上述した金属材料の選択的組み合わせ、又は上記金属材料とそれ以外の金属材料との組み合わせになる複数層の多層構造としてもよい。
機能層２は、支持層１と積層される一面とは反対側の面（図１において下面）に、バンプ５を有している。バンプ５は、縦導体３とは反対側において、半導体回路６に対する配線を構成する。図示の例では、バンプ５は、第１接合膜５１と、磁性膜５２と、第２接合膜５３とを順次に積層した構造となっている。第１接合膜５１は、積層時接合を担う部分であり、第２接合膜５３は、半導体回路６と接続される部分である。第１接合膜５１及び第２接合膜５３は、Ｓｎ、Ａｇ、Ａｕ、Ｃｕ、Ａｌ、ＩｎまたはＢｉ等から選択された金属材料によって構成される。図示では、一層表示となっているが、電気的特性改善、接合強度向上、溶融特性の改善などの観点から、上述した金属材料の選択的組み合わせ、又は上記金属材料とそれ以外の金属材料との組み合わせになる複数層の多層構造としてもよい。この点は、接合膜４２の場合と同様である。
磁性膜５２は、第１接合膜５１と第２接合膜５３との間に設けられ、磁性膜４１と同様に、磁気的な位置合せマーカとして機能する。磁性膜５２は、Ｎｉ、ＣｏもしくはＦｅ又はそれらの合金を含む。
積層・位置合せに当たっては、図１に図示するように、上述した基板ＷＦ１〜ＷＦｒの複数枚を、縦導体３が互いに重なるように、一応の位置合せをした上で、順次に積層する。この状態では、基板ＷＦ１〜ＷＦｒの各縦導体３は、一応、重なり合うものの、正確な心合せはできていない。
そこで、積層した状態で、外部から磁界Ｈを印加し、隣接する基板ＷＦ１〜ＷＦｒの磁性膜４１−５２の間に磁気的吸引力Ｆｍを生じさせ、磁気的吸引力Ｆｍにより位置合せする。例えば、隣接する基板ＷＦ１と、基板ＷＦ２とを例に採ると、基板ＷＦ１の磁性膜４１と、基板ＷＦ２の磁性膜５２との間に磁気的吸引力Ｆｍが働き、基板ＷＦ１の縦導体３と基板ＷＦ２の縦導体３が、高精度で位置合せされる。
上述した磁気的な位置合せ操作により、一応の位置合せ状態にあった各基板ＷＦ１〜ＷＦｒの縦導体３が、更に高精度に位置合せされる。磁界Ｈは、図示しない永久磁石又は電磁石で与えられる。
上述したように、本発明では、積層面となる基板面の所定位置に、磁性膜４１、５２を設けておき、隣接する基板ＷＦ１〜ＷＦｒの磁性膜４１−５２の間に磁気的吸引力Ｆｍを生じさせ、磁気的吸引力Ｆｍにより、基板ＷＦ１〜ＷＦｒ、特に縦導体３を位置合せするから、ＴＳＶ技術を適用して電子デバイスを製造に当たり、従来用いられていた画像処理との対比において、基板ＷＦ１〜ＷＦｒの積層時位置合せを、簡単、かつ、確実に、高精度で実行し得る。
位置合せの後は、熱処理を行い、基板ＷＦ１〜ＷＦｒを接合する。これにより、電子デバイス用積層体が得られる。より具体的には、図４に示すように、基板ＷＦ１〜ＷＦｒのうち、互いに隣接する基板、例えば、基板ＷＦ１と基板ＷＦ２において、基板ＷＦ１に備えられた接合膜４２と、基板ＷＦ２に備えられたバンプ５の第２接合膜５３とが接合される。接合プロセスを磁界中で実行すれば、その間、積層された基板ＷＦ１〜ＷＦｒ間に磁気的吸引力を作用させることができるので、接合プロセス中に基板ＷＦ１〜ＷＦｒに位置ずれを生じることがない。
磁性膜は、縦導体３の外側に位置する基板面に設けられていてもよい。その一例を図５に示す。図５を参照すると、基板ＷＦ１〜ＷＦｒのそれぞれにおいて、１チップ領域Ｑ１を画定するＸ方向切断位置Ｃｘ及びＹ方向切断位置Ｃｙに磁性膜６１、６２が設けられている。磁性膜６１、６２は、好ましくは、膜面が支持層１及び機能層２の表面とほぼ一致するように、支持層１及び機能層２に埋め込む。縦導体３の一端面には、磁性膜が存在せず、接合膜４が直接に付着されている。また、バンプ５も、磁性膜を持たず、第１接合層５１及び第２接合層５３を積層した構造となっている。もっとも、図１〜図４に示した磁性膜配置構造との組み合わせを排除するものではない。
上述した基板ＷＦ１〜ＷＦｒの複数枚を、縦導体３が互いに重なるように、一応の位置合せをした上で、順次に積層する。そして、積層した状態で、外部から磁界Ｈを印加し、隣接する基板ＷＦ１〜ＷＦｒの磁性膜６１−６２の間に磁気的吸引力Ｆｍを生じさせ、磁気的吸引力Ｆｍにより位置合せする。これにより、一応の位置合せ状態にあった各基板ＷＦ１〜ＷＦｒの縦導体３が、更に高精度に位置合せされる。
実施の形態において、磁性膜６１、６２は、Ｘ方向切断位置Ｃｘ及びＹ方向切断位置Ｃｙに設けられているから、１チップ化するために、Ｘ方向切断位置Ｃｘ及びＹ方向切断位置Ｃｙで切断した場合、磁性膜６１、６２は、切断刃幅によって全て除去され、チップ個品には残らない。
磁性膜６１、６２のパターンは、磁気的吸引力Ｆｍによる有効な位置合せに寄与する形態であればよい。その一例を、図６に示す。図６では、磁性膜６１、６２は、縦導体３と同様の配置ピッチで支持層１又は機能層２に設けられた孔内に充填されている。磁性膜６１、６２は、Ｘ方向切断位置Ｃｘ及びＹ方向切断位置Ｃｙに、切断幅よりも小さい直径をもって形成されている。従って、１チップ化するために、Ｘ方向切断位置Ｃｘ及びＹ方向切断位置Ｃｙで切断した場合、磁性膜６１、６２は、切断刃幅によって全て除去され、チップ個品には残らない。
磁性膜６１、６２は、図示はしないが、Ｘ方向切断位置Ｃｘ及びＹ方向切断位置Ｃｙに沿って、１チップ領域Ｑを超えて直線状に延びる態様や、直線状に延びているが、異なるチップ領域間では不連続となっている態様や、さらには、チップ領域Ｑ１のコーナ部に設けられている態様など、種々の態様を採ることができる。
本発明に係る電子デバイスは、代表的には、三次元システム・パッケージ（３D-SiP)としての形態をとる。具体的には、システムＬＳＩ、メモリＬＳＩ、イメージセンサ又はＭＥＭＳ等である。アナログやデジタルの回路、ＤＲＡＭのようなメモリ回路、ＣＰＵのようなロジック回路などを含む電子デバイスであってもよいし、アナログ高周波回路と低周波で低消費電力の回路といった異種の回路を、別々のプロセスによって作り、それらを積層した電子デバイスであってもよい。
更に具体的には、センサーモジュル、光電気モジュール、ユニポーラトランジスタ、ＭＯＳ−ＦＥＴ、ＣＭＯＳ−ＦＥＴ、メモリーセル、もしくは、それらの集積回路部品（ＩＣ）、又は各種スケールのＬＳＩ等、凡そ、電子回路を機能要素とする電子デバイスのほとんどのものが含まれ得る。本発明において、集積回路ＬＳＩと称する場合、小規模集積回路、中規模集積回路、大規模集積回路、超大規模集積回路ＶＬＳＩ、ＵＬＳＩ等の全てを含む。
本発明に係る製造方法は、上述にしたように、極めて広範囲の電子デバイスの製造に適用できるものである。電子デバイスの中には、図４に示したような積層体そのものが、電子デバイスの殆どを占めるようなものも存在するし、或いは、図４に示した積層体の上又は下に、インターポーザなどを介して、又は、インターポーザを介することなく、他の回路機能部を積層する構造を採ることもある。
以上、好ましい実施例を参照して本発明を詳細に説明したが、本発明はこれらに限定されるものではなく、当業者であれば、その基本的技術思想および教示に基づき、種々の変形例を想到できることは自明である。
１ 支持層
２ 半導体層
３ 縦導体
４１ 磁性膜
５２ 磁性膜
６１、６２ 磁性膜

Claims (9)

  1. 複数枚の基板を位置合せして積層し、接合する工程を含む電子デバイスの製造方法であって、
    前記複数枚の基板のそれぞれは、複数の縦導体と、磁性膜とを有しており、
    前記縦導体は、前記基板の板厚方向に向かい、基板面に対して整列して分布されており、
    前記磁性膜は、前記基板の前記板厚方向の両側に設けられており、
    前記磁性膜の一方は、前記縦導体の端面の上に設けられ、表面が金属又は合金でなる接合膜によって覆われており、
    前記磁性膜の他方は、前記磁性膜の一方とは反対側において、前記縦導体の上に設けられ、表面が金属又は合金でなる接合膜によって覆われており、
    前記複数枚の基板を位置合せし、接合するに当たり、
    外部から磁界を印加して、隣接する前記基板の前記磁性膜間に磁気的吸引力を生じさせ、
    前記磁気的吸引力により前記縦導体を位置合せし、熱処理して前記接合膜により接合する、
    工程を含む、電子デバイスの製造方法。
  2. 請求項１に記載された製造方法であって、前記接合膜は、Ｓｎ、Ａｇ、Ａｕ、Ｃｕ、Ａｌ、ＩｎまたはＢｉの群から選択された少なくとも一種を含んでいる、
    製造方法。
  3. 請求項１又は２に記載された製造方法であって、前記縦導体膜は、Ｃｕ、又は、Ｓｎを主成分とする、製造方法。
  4. 請求項１乃至３の何れかに記載された製造方法であって、前記磁性膜は、Ｎｉ、ＣｏもしくはＦｅ又はそれらの合金を含む、製造方法。
  5. 基板と、複数の縦導体と、磁性膜とを有する電子デバイス用基板であって、
    前記基板は、複数の縦導体と、磁性膜とを有しており、
    前記縦導体のそれぞれは、板厚方向に向かい、基板面に対して整列して分布されており、
    前記磁性膜は、前記基板の前記板厚方向の両側に設けられており、
    前記磁性膜の一方は、前記縦導体の端面の上に設けられ、表面が金属又は合金でなる接合膜によって覆われており、
    前記磁性膜の他方は、前記磁性膜の一方とは反対側において、前記基板の面上に設けられ、表面が金属又は合金でなる接合膜によって覆われている、
    電子デバイス用基板。
  6. 複数枚の基板を積層した電子デバイス用積層体であって、
    前記複数枚の基板は、請求項５に記載された電子デバイス用基板であり、
    前記電子デバイス用基板のそれぞれは、前記磁性膜及び前記縦導体が位置合せされ、互いに積層され、接合されている、
    電子デバイス用積層体。
  7. 積層体と、回路機能部とを含む電子デバイスであって、
    前記積層体は、請求項６に記載された電子デバイス用積層体であり、
    前記回路機能部は、前記積層体と組み合わされている、
    電子デバイス。
  8. 請求項７に記載された電子デバイスであって、三次元システム・パッケージ（３D-SiP)である、電子デバイス。
  9. 請求項８に記載された電子デバイスであって、システムＬＳＩ、メモリＬＳＩ、イメージセンサ、又はＭＥＭＳの何れかである、電子デバイス。
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TW099142915A TWI436452B (zh) 2009-12-11 2010-12-09 電子裝置用基板、電子裝置用積層體、電子裝置及其等之製造方法
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