TWI436452B - 電子裝置用基板、電子裝置用積層體、電子裝置及其等之製造方法 - Google Patents

電子裝置用基板、電子裝置用積層體、電子裝置及其等之製造方法 Download PDF

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TWI436452B
TWI436452B TW099142915A TW99142915A TWI436452B TW I436452 B TWI436452 B TW I436452B TW 099142915 A TW099142915 A TW 099142915A TW 99142915 A TW99142915 A TW 99142915A TW I436452 B TWI436452 B TW I436452B
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electronic device
substrate
magnetic
bonding
substrates
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TW099142915A
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English (en)
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TW201131697A (en
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Shigenobu Sekine
Yurina Sekine
Yoshiharu Kuwana
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Napra Co Ltd
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Description

電子裝置用基板、電子裝置用積層體、電子裝置及其等之製造方法
本發明關於電子裝置用基板、電子裝置用積層體、電子裝置及其等之製造方法。
作為電子裝置的例子者，可舉出有例如各種比例的積體電路、各種半導體元件或其晶片等。此種電子裝置中，作為實現其三維電路配置的手法者，採取了將LSI配置於電路基板上，並利用線接合(wire bonding)等手段以連接於其間的方法。但是，若是此方法，則安裝面積隨著LSI的數而增加，從配線長度增加的觀點，LSI間的信號延遲會變大。
所以，已提出有預先於電路基板設置多數個貫穿電極，並積層此電路基板的TSV(Through-Silicon-Via)技術。於特開平11-298138號公報、特開2000-228410號公報、特開2002-158191號公報、特開2003-257891號公報、特開2006-111896號公報揭示有TSV技術所不可或缺的貫穿電極形成技術。相對於引線接合，TSV技術的優越性如以下所述。
首先，於線接合的情形下，雖然限制在100～200條的連接條數，但是使用TSV技術的話，能以μm等級的間隔來配列連接用貫穿電極，所以，可達到數千條單位的連接條數。
又，由於連接距離為最短，所以不易接受到雜訊，以小的寄生電容或電阻即可，以致於延遲、衰減與波形劣化變少，不需要用以放大或保護靜電破壞之多餘的電路，如此一來，可獲得實現電路的高速動作與低消耗電力等優點。
以使用TSV技術，當然可獲得包含對比或數位的電路、DRAM那般的記憶電路、CPU那般的邏輯電路等電子裝置，也可藉由另外的製程來製作對比高頻電路與低頻且低消耗電力的電路這般不同種類的電路，以獲得將此等電路予以積層所構成的電子裝置。
將TSV技術使用於三維積體電路(3D IC)的話，可達到將大量的機能塞入小的占有面積之中。而且，可急劇地縮短元件彼等之重要的電路徑，所以可導致處理的高速化。
然而，TSV技術係將形成有貫穿電極的基板予以積層，所以，在要積層的基板間必須將貫穿電極予以對位。習知在對位時係使用影像處理技術。然而，貫穿電極係以μm等級的間隔配列著，難以藉由影像處理技術來正確地對位。假設，即使在畫面上的對位結束，在實際製程上也有產生基板間位置偏移的危險性。
本發明的課題係在於提供一種應用TSV技術來製造電子裝置時，能以簡單既確實且高精度進行積層時對位的製造方法，用於該製造方法之基板、積層體及電子裝置。
為了解決上述課題，本發明係一種電子裝置之製造方法，包含將複數片基板予以對位並積層的步驟；前述複數片基板分別具有複數個縱向導體及磁性膜。前述縱向導體相對於基板面排列分布。前述磁性膜相對於前述縱向導體具有預定的位置關係，且設置於前述基板面。
當要將前述複數片基板予以對位時，係從外部施加磁場，使積層而鄰接之前述基板的前述磁性膜之間產生磁性吸引力，而藉由前述磁性吸引力將前述縱向導體予以對位。即，使磁性膜具有作為磁性的對位標記的機能。
如以上所述，本發明預先於基板面的預定位置將磁性膜設置成相對於縱向導體具有預定的位置關係，並使鄰接之基板的磁性膜之間產生磁性吸引力，藉由磁性吸引力將縱向導體予以對位，所以，當應用TSV技術來製造電子裝置時，於與習知所使用之影像處理的對比上，本發明能以簡單且確實而高精度地進行縱向導體之積層時的對位。
而且，只要是施加了磁場，磁性吸引力就會作用於業經積層的基板間，所以，於積層中或其後的處理，例如於接合處理中不會於基板產生位置偏移。
前述縱向導體可為業已填充在貫穿基板之貫穿孔內的貫穿電極，也可為業已填充於底部封閉之盲孔內的電極。
前述磁性膜可設置在前述縱向導體之至少一端面上。此情形下，磁性膜構成縱向導體的一部分。與此不同的是，磁性膜也可設置於前述縱向導體之外側的位置。
前述磁性膜具體上可包含Ni、Co或Fe或是此等的合金。
本發明進一步揭示應用於以上所述製造方法的基板、積層有該基板的積層體、甚至是使用以上所述之製造法或積層體的電子裝置。
該等其他目標，本發明之解釋及優點將參考附加圖示進一步說明如下。然而，該等附加的圖示僅顯示說明的例子。
參照第1圖，顯示了包含將複數片r(r為2以上的自然數)基板WF1～WFr予以對位並予以積層的步驟之電子裝置的製造方法。雖然第1圖中僅顯示有簡單構成的基板，但是為了因應要實現之電子裝置之種類的機能、以及為了符合構造，乃採用更複雜的構造。
基板WF1～WFr係以各種半導體基板、介電體基板、絕緣基板或磁性基板，或是此等之複合基板等來構成。實施例之基板WF1～WFr係矽晶圓，建構成於矽層所構成之支撐層1的一面側積層有具有CMOS等半導體電路6之機能層2的構造。
基板WF1～WFr中各個基板也如第2圖及第3圖所示，具有複數個縱向導體3、及磁性膜41。縱向導體3相對於基板面排列分布著。縱向導體3可為業已填充在貫穿基板WF1～WFr之貫穿孔內的貫穿電極，也可為業已填充於底部封閉之盲孔內的電極。實施形態所示之縱向導體3係貫穿支撐層1的貫穿電極，且設置在每一個半導體電路6，一端連接於半導體電路6，相對於半導體電路6具有作為連接配線的機能。
縱向導體3及半導體電路6如第2圖所示，以假定於基板面的XY平面來觀看，具有於X方向及Y方向既定的配置間距Lx、Ly，例如整齊排列並配置成矩陣狀。以一例來例示縱向導體3的尺度時，配置間距Lx、Ly為4～100μm的範圍，最小部分的直徑為0.5～25μm的範圍。當然，配置間距Lx、Ly不須為一定的尺寸。
通常，於X方向及Y方向的各個方向，包含複數個縱向導體3及半導體電路6的區域構成作為電子裝置之1個晶片區域Q1。1個晶片區域Q1所包含之縱向導體3及半導體電路6的個數在實施形態中為9個，然而，可為因應電子裝置而改變的任意數。為了從1個晶片區域Q1取出作為電子裝置的個件，而在X方向切斷位置Cx及Y方向切斷位置Cy切斷。
縱向導體3係可藉由應用電鍍法、熔融金屬填充法或導電膏填充法等眾所周知的技術來形成。組成縱向導體3的材料依據形成方法而不同。使用電鍍法時，主要是使用Cu電鍍膜，使用熔融金屬填充法時，係藉由以錫(Sn)為主成分的金屬材料來構成，也可因應需要而含有銦(In)、鋁(Al)或鉍(Bi)等。
為了形成縱向導體3，可採用其中任一形成方法，於此之前必須形成縱向孔(貫穿介層孔)。縱向孔(貫穿介層孔)係可藉由CVD法、雷射穿孔法等眾所周知的技術來形成。縱向孔(貫穿介層孔)的形成時序，乃有稱為在形成半導體電路6之前形成縱向孔(貫穿介層孔)的優先介層孔(Via‧First)的手法，與在形成半導體電路6之後形成縱向孔(貫穿介層孔)的殿後介層孔(Via‧Last)的手法，而可應用其中任一手法。
磁性膜41附著於縱向導體3的一端面上，磁性膜41的表面附著有接合膜42。磁性膜41係本發明的特徵部分之一，而具有作為磁性的對位的機能。磁性膜41包含Ni、Co或Fe或是此等的合金。
接合膜42係當擔積層時接合的部分，藉著從Sn、Ag、Au、Cu、Al、In或Bi等所選擇的金屬材料來構成。圖式中係顯示一層，但是從電性特性的改善、接合強度的提升、熔融特性的改善等觀點，也可為上述金屬材料之選擇性的組合、或是上述金屬材料與此等以外的金屬材料的組合所構成之複數層的多層構造。
機能層2於與支撐層1積層之一面呈相反側的面(第1圖中為下面)具有凸塊(bump)5。凸塊5於與縱向導體3呈相反側構成對於半導體電路6的配線。圖式的例子中，凸塊5係依序積層有第1接合膜51、磁性膜52、第2接合膜53的構造。第1接合膜51係擔當積層時接合的部分，第2接合膜53係與半導體電路6連接的部分。第1接合膜51及第2接合膜53係藉著從Sn、Ag、Au、Cu、Al、In或Bi等所選擇之金屬材料來構成。圖式中係顯示一層，但是從電性特性的改善、接合強度的提升、熔融特性的改善等觀點，也可為上述金屬材料之選擇性的組合、或是上述金屬材料與此以外的金屬材料的組合所構成之複數層的多層構造。此點與接合膜42的情形相同。
磁性膜52設置於第1接合膜51與第2接合膜53之間，與磁性膜41同樣具有作為磁性的對位標記的機能。磁性膜52包含Ni、Co或Fe或是此等的合金。
當要積層、對位時，如第1圖所圖示，係以縱向導體3相互重疊的方式，且以一次對位的狀態下順序地積層以上所述之基板WF1～WFr的複數片。此狀態下，雖然基板WF1～WFr的各縱向導體3一下子就重疊，但是未能達到正確的對位。
因此，在已積層的狀態下，從外部施加磁場H以使鄰接的基板WF1～WFr之磁性膜41-52之間產生磁性吸引力Fm，而藉由磁性吸引力Fm來對位。例如，採取以鄰接的基板WF1與基板WF2為例時，基板WF1的磁性膜41與基板WF2之磁性膜52之間會起磁性吸引力Fm作用，而使基板WF1的縱向導體3與基板WF2的縱向導體3以高精度對位。
藉由以上所述磁性的對位操作，在一次對位狀態下的各基板WF1～WFr的縱向導體3可更高精度地對位。磁場H係利用未以圖式顯示的永久磁石或電磁石來供給。
如以上所述，本發明預先於成為積層面之基板面的預定位置設置磁性膜41、52，使鄰接的基板WF1～WFr的磁性膜41-52之間產生磁性吸引力Fm，藉由磁性吸引力Fm將基板WF1～WFr特別是縱向導體3予以對位，所以，在應用TSV技術來製造電子裝置時，與習知所使用的影像處理對比的情形下，本發明能以簡單且確實而高精度進行基板WF1～WFr之積層時的對位。
對位之後進行熱處理，以將基板WF1～WFr接合。藉此，可獲得電子裝置用積層體。更具體而言，如第4圖所示，在基板WF1～WFr之中，於相互鄰接的基板，例如於基板WF1與基板WF2中，基板WF1所具有的接合膜42與基板WF2所具有的凸塊5的第2接合膜53接合。若是在磁場中進行接合處理的話，其間可使已積層的基板WF1～WFr間發揮磁性吸引力，所以，於接合過程中，於基板WF1～WFr不會產生位置偏移。
磁性膜也可設置在位於縱向導體3之外側的基板面。於第5圖中顯示其一例。參照第5圖，於基板WF1～WFr之各別的基板中，在劃定1晶片區域Q1的X方向切斷位置Cx及Y方向切斷位置Cy設置有磁性膜61、62。磁性膜61、62最好是以膜面與支撐層1及機能層2的表面一致的方式埋入支撐層1及機能層2。縱向導體3的一端面不存在磁性膜，而係接合膜4直接附著。又，凸塊5也不具有磁性膜，而係構成積層有第1接合層51及第2接合層53的構造。當然，不排除與第1圖～第4圖所示之磁性膜配置構造的組合。
以縱向導體3不相互重疊的方式進行了一次對位的情形下，順序地積層以上所述的基板WF1～WFr的複數片。如此一來，在已積層的狀態下，從外部施加磁場H以使鄰接的基板WF1～WFr的磁性膜61-62之間產生磁性吸引力Fm，而藉由磁性吸引力Fm來對位。藉此，在一次對位狀態下的各基板WF1～WFr的縱向導體3可更高精度地對位。
於實施形態中，磁性膜61、62設置於X方向切斷位置Cx及Y方向切斷位置Cy，因此是1晶片化，所以，在X方向切斷位置Cx及Y方向切斷位置Cy切斷的情形下，磁性膜61、62藉由切斷刀刃寬度而全部去除，不會殘留於各個晶片。
磁性膜61、62的圖形為有助於藉由磁性吸引力Fm所達致有效位置的形態即可。其一例如第6圖所示，第6圖中，磁性膜61、62係以與縱向導體3同樣的配置間距填充於已設置在支撐層1或機能層2的孔內。磁性膜61、62以具有比切斷寬度還小的直徑形成於X方向切斷位置Cx及Y方向切斷位置Cy。所以，由於係1晶片化，所以在X方向切斷位置Cx及Y方向切斷位置Cy切斷的情形下，磁性膜61、62藉由切斷刀刃寬度而全部去除，不會殘留於各個晶片。
磁性膜61、62雖未以圖式顯示，唯可採用沿著X方向切斷位置Cx及Y方向切斷位置Cy並超過1晶片區域Q延伸成直線狀的形態、或是雖然延伸成直線狀，然而在不同晶片區域間不連續的形態、或是也可為設置於晶片區域Q1之角落部的形態等各種各式的形態。
本發明之電子裝置在代表性方面係採取三維系統封裝(3D-SiP)的形態。具體上為系統LSI、記憶體LSI、影像感測器或微機電系統(MEMS)等。可為包含對比或數位的電路、DRAM那般的記憶電路、CPU那般的邏輯電路等的電子裝置，也可為以各別的處理來製作對比高頻電路與低頻且低消耗電力之電路等不同的電路，並將其等予以積層的電子裝置。
更具體而言，可包含感測器模組、光電模組、單極電晶體、MOS、FET、CMOS FET、記憶單元、或此等的積體電路零件(IC)、或是各種尺度的LSI等大致幾乎是將電子電路作為機能要素之電子裝置。本發明中，稱為積體電路LSI的情形下，係包含小型積體電路、中型積體電路、大型積體電路、超大型積體電路VLSI、ULSI等之全部。
本發明之製造方法如以上所述，係可應用於極廣範圍之電子裝置的製造。於電子裝置之中，第4圖所示之積層體係存在有幾乎占有電子裝置全部者，或是可採用於第4圖所示積層體之上或下，藉由中介層(interposer)等，或是不藉由中介層而積層其他電路機能部的構造。
本發明參考諸較佳實施例描述如上。然而，顯然熟知本技藝者能輕易的基於在本發明及其中所教示的技術概念而設計各種修改。
1．．．支撐層
2．．．機能層
3．．．縱向導體
4．．．接合膜
5．．．凸塊
6．．．半導體電路
41．．．磁性膜
42．．．接合膜
51．．．第1接合膜
52．．．磁性膜
53．．．第2接合膜
61、62．．．磁性膜
Cx．．．X方向切斷位置
Cy．．．Y方向切斷位置
Fm．．．磁性吸引力
H．．．磁場
Lx、Ly．．．配置間距
Q1．．．晶片區域
WF1～WFr．．．基板
第1圖係顯示本發明之電子裝置之製造方法的圖式。
第2圖係使用於實施第1圖所示之製造方法之基板一部分的平面圖。
第3圖係使用於實施第1圖所示之製造方法之基板一部分的平面圖。
第4圖係顯示業經第1圖所示之製造方法所獲得之積層體或電子裝置的圖式。
第5圖係顯示本發明之電子裝置之製造方法之另一實施形態的圖式。
第6圖係使用於實施第5圖所示之製造方法之基板之一例的平面圖。
1．．．支撐層
2．．．機能層
3．．．縱向導體
5．．．凸塊
6．．．半導體電路
41．．．磁性膜
42．．．接合膜
51．．．第1接合膜
52．．．磁性膜
53．．．第2接合膜
61、62．．．磁性膜
Fm．．．磁性吸引力
H．．．磁場
Lx、Ly．．．配置間距
WF1～WFr．．．基板

Claims (9)

  1. 一種電子裝置之製造方法，其係包含將複數片基板予以對位並積層而接合的步驟；前述複數片基板分別具有複數個縱向導體及磁性膜；前述縱向導體朝前述基板的板厚方向且相對於基板面排列分布；前述磁性膜設置於前述基板的前述板厚方向的兩側；前述磁性膜的一者係設置於前述縱向導體的端面上，且表面以金屬或合金所構成的接合膜覆蓋；前述磁性膜的另一者係設置於前述磁性膜的一者的相反側上，且設置於前述縱向導體上，表面以金屬或合金構成的接合膜所覆蓋；當要將前述複數片基板予以對位並接合時，從外部施加磁場，以使鄰接之前述基板的前述磁性膜之間產生磁性吸引力；藉由前述磁性吸引力將前述縱向導體予以對位，施以熱處理並藉由前述接合膜接合。
  2. 如申請專利範圍第1項之電子裝置之製造方法，其中前述接合膜係包含從Sn、Ag、Au、Cu、Al、In或Bi的群組所選擇的至少一種。
  3. 如申請專利範圍第1項之電子裝置之製造方法，其中前述縱向導體係以Cu或Sn為主成分。
  4. 如申請專利範圍第1項之電子裝置之製造方法，其中前述磁性膜包含Ni、Co或Fe或是其等的合金。
  5. 一種電子裝置用基板，係具有基板、複數個縱向導體及磁性膜之電子裝置用基板，其中前述基板具有複數個縱向導體及磁性膜；前述縱向導體分別朝向板厚方向且相對於基板面排列分布；前述磁性膜設置於前述基板的前述板厚方向的兩側；前述磁性膜的一者係設置於前述縱向導體的端面上，且表面被以金屬或合金所構成的接合膜覆蓋；前述磁性膜的另一者係設置於前述磁性膜的一者的相反側上，且設置於前述基板的面上，表面被以金屬或合金構成的接合膜所覆蓋。
  6. 一種電子裝置用積層體，係積層有複數片基板之電子裝置用積層體，其中前述複數片基板係如申請專利範圍第5項所記載的電子裝置用基板，且前述電子裝置用基板係分別使前述磁性膜及前述縱向導體對位並相互積層而接合。
  7. 一種電子裝置，係包含積層體及電路機能部之電子裝置，其中前述積層體係如申請專利範圍第6項所記載的電子裝置用積層體，且前述電路機能部係與前述積層體組合。
  8. 如申請專利範圍第7項之電子裝置，其係三維系統封裝(3D-SiP)。
  9. 如申請專利範圍第8項之電子裝置，其係系統LSI、記憶體LSI、影像感測器或微機電系統(MEMS)當中的任一者。
TW099142915A 2009-12-11 2010-12-09 電子裝置用基板、電子裝置用積層體、電子裝置及其等之製造方法 TWI436452B (zh)

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