CN102142379A - 电子器件用基板、电子器件用层叠体、电子器件及它们的制造方法 - Google Patents

电子器件用基板、电子器件用层叠体、电子器件及它们的制造方法 Download PDF

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CN102142379A
CN102142379A CN2010105474932A CN201010547493A CN102142379A CN 102142379 A CN102142379 A CN 102142379A CN 2010105474932 A CN2010105474932 A CN 2010105474932A CN 201010547493 A CN201010547493 A CN 201010547493A CN 102142379 A CN102142379 A CN 102142379A
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mentioned
electronic device
substrate
magnetic film
vertical conductor
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关根重信
关根由莉奈
桑名良治
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NAPULA CORP
Napra Co Ltd
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NAPULA CORP
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Abstract

一种电子器件的制造方法，包括将多片基板对位并层叠的工序，上述多片基板分别具有多个纵导体和磁性膜；上述纵导体朝向板厚方向，相对于基板面排列分布；上述磁性膜相对于上述纵导体具有预先设定的位置关系，设在上述基板面的规定位置上；在将上述多片基板对位时，包括从外部施加磁场、使层叠而邻接的上述基板的上述磁性膜之间产生磁吸引力、通过上述磁吸引力将上述纵导体对位的工序。

Description

电子器件用基板、电子器件用层叠体、电子器件及它们的制造方法
技术领域
本发明涉及电子器件用基板、电子器件用层叠体、电子器件及它们的制造方法。
背景技术
作为电子器件的例子，例如可以举出各种规模的集成电路、各种半导体元件或其芯片等。在这种电子器件中，作为实现其三维电路配置的方法，采取将LSI配置到电路基板上、将其之间用引线接合(wire bonding)等手段连接的方法。但是，在该方法中，安装面积随着LSI的数量增加，因为配线长度的增加，LSI间的信号延迟变大。
所以，提出了在电路基板上设置许多贯通电极、将该电路基板层叠的TSV(Through-Silicon-Via)技术。在日本特开平11-298138号公报、日本特开2000-228410号公报、日本特开2002-158191号公报、日本特开2003-257891号公报、日本特开2006-111896号公报中，公开了在TSV技术中不可或缺的贯通电极形成技术。TSV技术相对于引线接合的优越性如以下所述。
首先，在引线接合中，连接根数被限制为100～200根，但如果使用TSV技术，则由于能够以μm量级的间隔来排列连接用贯通电极，所以能够达到几千根单位的连接根数。
此外，由于连接距离为最短，所以不易受到噪声干扰，并且，因为寄生电容及电阻较小即可，所以延迟及衰减、波形的劣化变少，不需要用于放大及静电破坏保护的多余电路，通过这些，能够得到实现电路的高速动作和低消耗功率化的优点等。
通过使用TSV技术，不仅是包括模拟及数字的电路、DRAM那样的存储器电路、CPU那样的逻辑电路等的电子器件，还能够得到通过分别的过程来制作模拟高频电路和低频低消耗功率的电路等不同种类的电路、将它们层叠而成的电子器件。
如果在3维集成电路(3D IC)中使用TSV技术，则能够将大量的功能装入到较小的占用面积之中。此外，由于元件彼此的重要电气路径能够显著变短，所以带来处理的高速化。
并且，在TSV技术中，由于成为将形成有贯通电极的基板层叠，所以需要在层叠的基板间将贯通电极对位。以往，在对位时使用图像处理技术。但是，贯通电极以μm量级的间隔排列，通过图像处理技术难以正确地对位。即使画面上的对位完成，在实际过程中也有发生基板间的位置偏差的危险性。
发明内容
本发明的目的是提供一种在采用TSV技术制造电子器件时、能够简单可靠、并且以高精度地执行层叠时对位的制造方法、适用于该方法的基板、层叠体及电子器件。
为了解决上述问题，本发明是一种电子器件的制造方法，包括将多片基板对位并层叠的工序，上述多片基板分别具有多个纵导体(縦導体)和磁性膜。上述纵导体相对于基板面排列分布。上述磁性膜相对于上述纵导体具有预先设定的位置关系，设在上述基板面上。
在将上述多片基板对位时，从外部施加磁场、使层叠而邻接的上述基板的上述磁性膜之间产生磁吸引力、通过上述磁吸引力将上述纵导体对位。即，使磁性膜作为磁对位标记(marker)发挥功能。
如上所述，在本发明中，在基板面的规定位置上设置磁性膜使其相对于纵导体具有预先设定的位置关系，使邻接的基板的磁性膜之间产生磁吸引力，通过磁吸引力将纵导体对位，所以在采用TSV技术制造电子器件时，在与以往使用的图像处理的对比中，能够简单且可靠地、高精度地执行纵导体的层叠时对位。
并且，只要被施加磁场，在层叠的基板间的磁吸引力就发挥作用，所以在层叠过程中或之后的过程、例如接合过程中不会在基板上发生位置偏差。
上述纵导体既可以是填充在贯通基板的贯通孔内的贯通电极，也可以是填充在底部封闭的盲孔内的电极。
上述磁性膜可以设在上述纵导体的至少一端面上。在此情况下，磁性膜构成纵导体的一部分。与此不同，磁性膜也可以设在上述纵导体的外侧位置上。
上述磁性膜具体而言可以包括Ni、Co或Fe、或者它们的合金。
本发明还公开了适用于上述制造方法的基板、层叠了该基板的层叠体、还有使用上述制造法或层叠体的电子器件。
本发明的其他目的、结构和优点会在以下结合附图详细说明。但是，附图仅表示说明例。
附图说明
图1是表示有关本发明的电子器件的制造方法的图。
图2是表示在图1所示的制造方法的实施中使用的基板的一部分的俯视图。
图3是表示在图1所示的制造方法的实施中使用的基板的一部分的俯视图。
图4是表示经过图1所示的制造方法得到的层叠体或电子器件的图。
图5是表示有关本发明的电子器件的制造方法的另一实施方式的图。
图6是表示在图5所示的制造方法的实施中使用的基板的一例的俯视图。
具体实施方式
参照图1，图示了包括将片数为r(r是2以上的自然数)的多片基板WF1～WFr对位并层叠的工序的电子器件的制造方法。在图1中仅表示了简单结构的基板，但实际上，为了满足对应于所要实现的电子器件的种类的功能及结构而采取更复杂的结构。
基板WF1～WFr由各种半导体基板、电介质基板、绝缘基板或磁性基板或它们的复合基板等构成。实施例的基板WF1～WFr是硅晶片，成为在由硅层形成的支撑层1的一面侧层叠了具有CMOS等半导体电路6的功能层2的结构。
基板WF1～WFr分别如在图2及图3中图示的那样，具有多个纵导体3、和磁性膜41。纵导体3相对于基板面排列分布。纵导体3既可以是填充在贯通基板WF1～WFr的贯通孔内的贯通电极，也可以是填充在底部封闭的盲孔内的电极。实施方式所示的纵导体3是将支撑层1贯通的贯通电极，在半导体电路6的每一个中分别配置，一端连接在半导体电路6上，作为对半导体电路6的连接配线发挥功能。
如图2所示，在设想为基板面的XY平面中观察，纵导体3及半导体电路6在X方向及Y方向上具有规定的配置间距Lx、Ly，例如以矩阵状排列配置。纵导体3的尺寸如果作为一例来例示，则配置间距Lx、Ly是4～100μm的范围，最小部的直径是0.5～25μm的范围。但是，配置间距Lx、Ly并不需要是固定尺寸。
通常，在X方向及Y方向的各自中，包括多个纵导体3及半导体电路6的区域构成作为电子器件的1芯片区域Q1。包含在1芯片区域Q1中的纵导体3及半导体电路6的个数在实施方式中是9个，但它是根据电子器件而变化的任意数。为了从1芯片区域Q1作为电子器件的个体取出，在X方向切断位置Cx及Y方向切断位置Cy进行切断。
纵导体3能够通过应用镀层法、熔融金属填充法或导电糊(paste)填充法等公知技术来形成。组成纵导体3的材料根据形成方法而不同。在镀层法的情况下，主要使用Cu镀层膜，在熔融金属填充法的情况下，由以锡(Sn)为主成分的金属材料构成，根据需要也可以含有铟(In)、铝(Al)或铋(Bi)等。
为了形成纵导体3，不论采用哪种形成方法，都需要在其之前形成纵孔(贯通孔)。纵孔(贯通孔)可以通过CVD法、激光穿孔法等公知的技术形成。作为纵孔(贯通孔)的形成时机，有在形成半导体电路6之前形成纵孔(贯通孔)的、称作通孔在先(via first)的方法，和在形成半导体电路6之后形成纵孔(贯通孔)的、称作通孔在后(via last)的方法，采用哪种方法都可以。
磁性膜41附着在纵导体3的一端面上，在磁性膜41的表面上附着有接合膜42。磁性膜41是本发明的特征部分之一，作为磁对位标记发挥功能。磁性膜41包含Ni、Co或Fe、或它们的合金。
接合膜42是担负层叠时接合的部分，由从Sn、Ag、Au、Cu、Al、In或Bi等中选择的金属材料构成。在图示中显示了一层，但从电气特性改善、接合强度提高、熔融特性的改善等的观点看，也可以是成为上述金属材料的选择的组合、或者上述金属材料与其以外的金属材料之间的组合的多个层的多层结构。
功能层2在与和支撑层1层叠的一面相反侧的面(在图1中是下面)上具有凸块5。凸块5在与纵导体3相反侧构成对半导体电路6的配线。在图示的例子中，凸块5为将第1接合膜51、磁性膜52、第2接合膜53依次层叠的结构。第1接合膜51是担负层叠时接合的部分，第2接合膜53是与半导体电路6连接的部分。第1接合膜51及第2接合膜53由从Sn、Ag、Au、Cu、Al、In或Bi等中选择的金属材料构成。在图示中显示了一层，但从电气特性改善、接合强度提高、熔融特性的改善等的观点看，也可以是成为上述金属材料的选择的组合、或者上述金属材料与其以外的金属材料之间的组合的多个层的多层结构。这一点与接合膜42的情况是同样的。
磁性膜52设在第1接合膜51与第2接合膜53之间，与磁性膜41同样，作为磁对位标记发挥功能。磁性膜52包含Ni、Co或Fe、或它们的合金。
在层叠、对位时，如图1中图示那样，将上述基板WF1～WFr的多片在进行大致对位以使纵导体3相互重叠后依次层叠。在此状态下，基板WF1～WFr的各纵导体3虽然大致重叠，但并不能实现正确的对心。
所以，在层叠的状态下，从外部施加磁场H，在邻接的基板WF1～WFr的磁性膜41-52之间产生磁吸引力Fm，通过磁吸引力Fm进行对位。例如，如果采用邻接的基板WF1和基板WF2为例，则在基板WF1的磁性膜41与基板WF2的磁性膜52之间磁吸引力Fm发挥作用，将基板WF1的纵导体3与基板WF2的纵导体3以高精度对位。
通过上述磁对位操作，将处于大致的对位状态的各基板WF1～WFr的纵导体3更高精度地对位。磁场H由未图示的永磁铁或电磁铁提供。
如上所述，在本发明中，在成为层叠面的基板面的规定位置上，设有磁性膜41、52，使邻接的基板WF1～WFr的磁性膜41-52之间产生磁吸引力Fm，通过磁吸引力Fm将基板WF1～WFr、特别是纵导体3对位，所以在采用TSV技术制造电子器件时，与以往使用的图像处理对比，能够简单且可靠地、且以高精度执行基板WF1～WFr的层叠时对位。
在对位之后，进行热处理，将基板WF1～WFr接合。由此，能够得到电子器件用层叠体。更具体地讲，如图4所示，在基板WF1～WFr中的相互邻接的基板、例如基板WF1和基板WF2中，将基板WF1具备的接合膜42与基板WF2具备的凸块5的第2接合膜53接合。如果在磁场中执行接合过程，则在此期间中，由于能够在层叠的基板WF1～WFr间作用磁吸引力，所以在接合过程中在基板WF1～WFr中不会发生位置偏差。
磁性膜也可以设在位于纵导体3的外侧的基板面上。在图5中表示其一例。如果参照图5，则在基板WF1～WFr的各自中，在围成1芯片区域Q1的X方向切断位置Cx及Y方向切断位置Cy处设有磁性膜61、62。磁性膜61、62优选的是，埋入支撑层1及功能层2中以使其膜面与支撑层1及功能层2的表面大致一致。在纵导体3的一端面上不存在磁性膜，直接附着有接合膜4。此外，凸块5也不具有磁性膜，为将第1接合层51及第2接合层53层叠的结构。但是，并不排除与图1～图4所示的磁性膜配置结构的组合。
在将上述基板WF1～WFr的多片进行大致的对位以使纵导体3相互重叠后，依次层叠。并且，在层叠的状态下，从外部施加磁场H，在邻接的基板WF1～WFr的磁性膜61-62之间产生磁吸引力Fm，通过磁吸引力Fm进行对位。由此，将处于大致的对位状态的各基板WF1～WFr的纵导体3更高精度地对位。
在实施方式中，由于磁性膜61、62设在X方向切断位置Cx及Y方向切断位置Cy处，所以在为了1芯片化而在X方向切断位置Cx及Y方向切断位置Cy进行切断的情况下，磁性膜61、62通过切断刃宽(
Figure BSA00000349274600061
幅)而被全部除去，不残留在芯片个体上。
磁性膜61、62的图案只要是有利于基于磁吸引力Fm的有效对位的形态就可以。在图6中表示其一例。在图6中，磁性膜61、62填充在以与纵导体3同样的配置间距而设在支撑层1或功能层2上的孔内。磁性膜61、62在X方向切断位置Cx及Y方向切断位置Cy上以比切断宽度小的直径而形成。因而，在为了1芯片化而在X方向切断位置Cx及Y方向切断位置Cy进行切断的情况下，磁性膜61、62通过切断刃宽而被全部除去，不残留在芯片个体上。
虽然没有图示，但磁性膜61、62可以采用如下各种形态：沿着X方向切断位置Cx及Y方向切断位置Cy地超过1芯片区域Q以直线状延伸的形态，或者虽以直线状延伸、但在不同的芯片区域间为不连续的形态，还有设在芯片区域Q1的角部上的形态等。
有关本发明的电子器件代表性地采用作为三维系统封装(3D-SiP)的形态。具体而言，是系统LSI、存储器LSI、图像传感器或MEMS等。既可以是包括模拟或数字电路、DRAM那样的存储器电路、CPU那样的逻辑电路等的电子器件，也可以是通过分别的过程来制作模拟高频电路和低频低消耗功率的电路等不同种类的电路、将它们层叠而成的电子器件。
更具体地讲，可以包括传感器模块、光电模块、单极晶体管、MOS FET、CMOS FET、存储器单元、或者它们的集成电路部件(IC)、或各种规模的LSI等，大体上可以包含以电子电路为功能要素的电子器件的几乎全部。在本发明中，在称作集成电路LSI的情况下，包括小规模集成电路、中规模集成电路、大规模集成电路、超大规模集成电路VLSI、ULSI等的全部。
有关本发明的制造方法如上所述，可以适用于极大范围的电子器件的制造。在电子器件之中，既存在图4所示那样的层叠体本身占电子器件的几乎全部那样的结构，或者也有采用在图4所示的层叠体之上或之下、经由中介层(interposer)等或不经由中介层而层叠其他电路功能部的结构的情况。
本发明已经通过以上优选的实施方式进行了具体的描述。但是，显然对于本领域的技术人员而言，容易基于这里描述的技术概念及启示来进行各种变更。

Claims (9)

1.一种电子器件的制造方法，包括将多片基板对位并层叠的工序，其特征在于，
上述多片基板分别具有多个纵导体和磁性膜，
上述纵导体朝向板厚方向，相对于基板面排列分布，
上述磁性膜相对于上述纵导体具有预先设定的位置关系，设在上述基板面的规定位置，
在将上述多片基板对位时，包括如下工序：
从外部施加磁场；
使层叠而邻接的上述基板的上述磁性膜之间产生磁吸引力；
通过上述磁吸引力将上述纵导体对位。
2.如权利要求1所述的制造方法，其特征在于，上述磁性膜设在上述纵导体的至少一端面上。
3.如权利要求1所述的制造方法，其特征在于，上述磁性膜设在上述纵导体的外侧。
4.如权利要求1所述的制造方法，其特征在于，上述磁性膜包括Ni、Co或Fe、或者它们的合金。
5.一种基板，是具有多个纵导体和磁性膜的电子器件用基板，其特征在于，
上述纵导体分别朝向板厚方向，相对于基板面排列分布，
上述磁性膜相对于上述纵导体具有预先设定的位置关系，设在上述基板面的规定位置。
6.一种层叠体，是层叠了多片基板的电子器件用层叠体，其特征在于，
上述多片基板是权利要求5所述的基板，上述磁性膜及上述纵导体被对位并相互层叠。
7.一种电子器件，包括层叠体和电路功能部，其特征在于，
上述层叠体是权利要求6所述的层叠体，
上述电路功能部与上述层叠体组合。
8.如权利要求7所述的电子器件，其特征在于，该电子器件是三维系统封装3D-SiP。
9.如权利要求8所述的电子器件，其特征在于，该电子器件是系统LSI、存储器LSI、图像传感器或MEMS中的某一种。
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