KR20110066866A - 전자 디바이스용 기판, 전자 디바이스용 적층체, 전자 디바이스 및 이들의 제조방법 - Google Patents

전자 디바이스용 기판, 전자 디바이스용 적층체, 전자 디바이스 및 이들의 제조방법 Download PDF

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KR20110066866A
KR20110066866A KR1020100125607A KR20100125607A KR20110066866A KR 20110066866 A KR20110066866 A KR 20110066866A KR 1020100125607 A KR1020100125607 A KR 1020100125607A KR 20100125607 A KR20100125607 A KR 20100125607A KR 20110066866 A KR20110066866 A KR 20110066866A
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electronic device
substrate
magnetic
substrates
magnetic film
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KR1020100125607A
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English (en)
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시게노부 세키네
유리나 세키네
요시하루 구와나
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유겐가이샤 나프라
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Publication of KR20110066866A publication Critical patent/KR20110066866A/ko

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Abstract

복수매의 기판을 위치 맞춤하여 적층하는 공정을 포함한 전자 디바이스의 제조방법으로서, 상기 복수매의 기판의 각각은, 복수의 종도체와 자성막을 가지고 있고, 상기 종도체는, 판두께 방향을 향하여, 기판면에 대해서 정렬되어 분포되어 있으며, 상기 자성막은, 상기 종도체에 대해서 미리 정해진 위치 관계를 가지며, 상기 기판면의 소정 위치에 형성되어 있고, 상기 복수매의 기판을 위치 맞춤할 때에, 외부로부터 자계를 인가하여, 적층되어 인접한 상기 기판의 상기 자성막 사이에 자기적 흡인력을 발생시키고, 상기 자기적 흡인력에 의해 상기 종도체를 위치 맞춤하는 공정을 포함한 전자 디바이스의 제조방법.

Description

전자 디바이스용 기판, 전자 디바이스용 적층체, 전자 디바이스 및 이들의 제조방법{SUBSTRATE FOR ELECTRONIC DEVICE, LAMINATED BODY FOR ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND MANUFACTURING METHOD THEREOF}
본 발명은, 전자 디바이스용 기판, 전자 디바이스용 적층체, 전자 디바이스 및 이들의 제조방법에 관한 것이다.
전자 디바이스의 예로서는, 예를 들면, 각종 스케일의 집적회로, 각종 반도체소자 혹은 그 칩 등을 들 수 있다. 이러한 종류의 전자 디바이스에서, 그 삼차원 회로 배치를 실현하는 수법으로서, 회로기판상에 LSI를 배치하고, 그 사이를 와이어·본딩 등의 수단으로 접속하는 방법이 취해져 왔다. 그러나, 이 방법에서는, 실장 면적이 LSI의 수와 함께 증가하고, 배선 길이가 증가하기 때문에, LSI간의 신호 지연이 커진다.
그리하여, 회로기판에 다수의 관통 전극을 마련해 두고, 이 회로기판을 적층하는 TSV(Through-Silicon-Via) 기술이 제안되어 있다. 일본 공개특허공보 평성 11-298138호, 일본 공개특허공보2000-228410호, 일본 공개특허공보2002-158191호, 일본 공개특허공보2003-257891호, 일본 공개특허공보2006-111896호에는, TSV 기술에 필수적인 관통 전극 형성 기술이 개시되어 있다. 와이어·본딩에 대한 TSV 기술의 우위성은, 다음과 같이 말할 수 있다.
먼저, 와이어·본딩에서는, 100∼200개로 접속 개수가 한정되어 있지만, TSV 기술을 사용하면, ㎛오더의 간격으로 접속용 관통 전극을 배열할 수 있기 때문에, 수천개 단위로의 접속 개수가 가능하다.
또한, 접속 거리가 최단이 되므로, 노이즈를 잘 받지 않는 점, 기생(寄生)용량이나 저항이 작아지기 때문에 지연이나 감쇠, 파형의 열화가 적어지는 점, 증폭이나 정전 파괴 보호를 위한 여분의 회로가 불필요한 점, 이에 따라, 회로의 고속 동작과 저소비 전력화가 실현되는 점 등의 이점을 얻을 수 있다.
TSV 기술을 이용하는 것에 의해, 아날로그나 디지털의 회로, DRAM과 같은 메모리 회로, CPU와 같은 로직 회로 등을 포함한 전자 디바이스는 물론, 아날로그 고주파 회로와 저주파로 저소비 전력의 회로와 같은 이종의 회로를, 각각의 프로세스에 의해서 만들어, 이들을 적층한 전자 디바이스를 얻을 수도 있다.
3차원 집적회로(3DIC)에 TSV 기술을 사용하면, 대량의 기능을 작은 점유 면적속에 담을 수 있게 된다. 게다가, 소자끼리의 중요한 전기 경로를 극적으로 짧게 할 수 있기 때문에, 처리의 고속화로 이어진다.
그런데, TSV 기술에서는, 관통 전극을 형성한 기판을 적층해 나가게 되므로, 적층되는 기판간에 관통 전극을 위치 맞춤하는 것이 필요하다. 종래의 위치 맞춤에서는, 화상 처리 기술을 사용하고 있었다. 그러나, 관통 전극은, ㎛오더의 간격으로 배열되어 있어, 화상 처리 기술에 의해서 정확하게 위치 맞춤하는 것이 곤란하다. 만일, 화면상에서의 위치 맞춤이 완료했다고 해도, 실프로세스에서는, 기판간의 위치 어긋남을 일으킬 위험성이 있다.
본 발명의 과제는, TSV 기술을 적용하여 전자 디바이스를 제조할 때에, 적층시 위치 맞춤을, 간단하게 또한 확실하게, 게다가 고정밀도로 실행할 수 있는 제조방법, 그를 위한 기판, 적층체 및 전자 디바이스를 제공하는 것이다.
상술한 과제를 해결하기 위해서, 본 발명은, 복수매의 기판을 위치 맞춤하여 적층하는 공정을 포함한 전자 디바이스의 제조방법에 있어서, 상기 복수매의 기판의 각각은, 복수의 종도체(縱導體)와 자성막을 가진다. 상기 종도체는, 기판면에 대해서 정렬되어 분포되어 있다. 상기 자성막은, 상기 종도체에 대하여 미리 정해진 위치 관계를 가지며, 상기 기판면에 형성되어 있다.
상기 복수매의 기판을 위치맞춤할 때에, 외부로부터 자계를 인가하여, 적층되어 인접한 상기 기판의 상기 자성막 사이에 자기적 흡인력을 일으켜, 상기 자기적 흡인력에 의해 상기 종도체를 위치 맞춤한다. 즉, 자성막을, 자기적인 위치 맞춤 마커로서 기능시킨다.
상술한 바와 같이, 본 발명에서는, 기판면의 소정 위치에, 자성막을, 종도체에 대해서 미리 정해진 위치 관계를 가지게 형성해 두고, 인접한 기판의 자성막 사이에 자기적 흡인력을 일으켜, 자기적 흡인력에 의해 종도체를 위치 맞춤시키기 때문에, TSV 기술을 적용하여 전자 디바이스를 제조할 때에, 종래 이용되고 있던 화상 처리와의 대비에서, 종도체의 적층시의 위치 맞춤을, 간단하고 또한 확실하게, 고정밀도로 실행할 수 있다.
게다가, 자계가 인가되고 있는 한, 적층된 기판 사이에 자기적 흡인력이 작용하므로, 적층중 또는 그 후의 프로세스, 예를 들면 접합 프로세스중에 기판에 위치 어긋남을 일으키는 경우가 없다.
상기 종도체는, 기판을 관통하는 관통구멍 내에 충전된 관통 전극이라도 좋고, 바닥부가 닫혀져 있는 블라인드 비아(blind via:맹공(盲孔)) 내에 충전된 전극이라도 좋다.
상기 자성막은, 상기 종도체의 적어도 일단면(一端面)상에 형성할 수 있다. 이 경우는, 자성막이, 종도체의 일부를 구성하게 된다. 이와는 달리, 자성막은, 상기 종도체의 바깥쪽 위치에 형성되어 있어도 좋다.
상기 자성막은, 구체적으로는, Ni, Co 혹은 Fe 또는 이들의 합금을 포함할 수 있다.
본 발명은, 또한, 상술한 제조방법에 적용되는 기판, 그 기판을 적층한 적층체, 또는, 상술한 제조법 또는 적층체를 이용한 전자 디바이스를 개시한다.
상술한 바와 같이, 본 발명에서는, 기판면의 소정 위치에, 자성막을, 종도체에 대해서 미리 정해진 위치 관계를 가지게 형성해 두고, 인접한 기판의 자성막 사이에 자기적 흡인력을 일으켜, 자기적 흡인력에 의해 종도체를 위치 맞춤시키기 때문에, TSV 기술을 적용하여 전자 디바이스를 제조할 때에, 종래 이용되고 있던 화상 처리와의 대비에서, 종도체의 적층시의 위치 맞춤을, 간단하고 또한 확실하게, 고정밀도로 실행할 수 있다.
게다가, 자계가 인가되고 있는 한, 적층된 기판 사이에 자기적 흡인력이 작용하므로, 적층중 또는 그 후의 프로세스, 예를 들면 접합 프로세스중에 기판에 위치 어긋남을 일으키는 경우가 없다.
본 발명의 다른 목적, 구성 및 장점들은 첨부한 도면을 참조하여 하기에서 상술될 것이다. 하지만, 첨부한 도면은 단지 설명을 위한 예시적인 것이다.
도 1은, 본 발명에 관한 전자 디바이스의 제조방법을 도시한 도면이다.
도 2는, 도 1에 도시한 제조방법의 실시에 이용되는 기판의 일부를 도시한 평면도이다.
도 3은, 도 1에 도시한 제조방법의 실시에 이용되는 기판의 일부를 도시한 평면도이다.
도 4는, 도 1에 도시한 제조방법을 거쳐 얻어진 적층체 또는 전자 디바이스를 도시한 도면이다.
도 5는, 본 발명에 관한 전자 디바이스의 제조방법에 관한 다른 실시형태를 도시한 도면이다.
도 6은, 도 5에 도시한 제조방법의 실시에 이용되는 기판의 일례를 도시한 평면도이다.
도 1을 참조하면, 복수매 r(r는 2이상의 자연수)의 기판(WF1∼WFr)을 위치 맞춤하여 적층하는 공정을 포함한 전자 디바이스의 제조방법이 도시되어 있다. 도 1에는, 간단한 구성의 기판이 나타나 있을 뿐이지만, 실제로는, 실현되어야 할 전자 디바이스의 종류에 따른 기능, 및, 구조를 만족시키기 위해서, 보다 복잡한 구조가 취해진다.
기판(WF1∼WFr)은, 각종 반도체 기판, 유전체 기판, 절연 기판 혹은 자성 기판 또는 이들의 복합 기판 등으로 구성된다. 실시예의 기판(WF1∼WFr)은, 실리콘웨이퍼이고, 실리콘층으로 된 지지층(1)의 일면측에, CMOS 등의 반도체 회로(6)를 가진 기능층(2)을 적층한 구조로 되어 있다.
기판(WF1∼WFr)의 각각은, 도 2 및 도 3에도 도시한 바와 같이, 복수의 종도체(3)와, 자성막(41)을 가진다. 종도체(3)는, 기판면에 대해서 정렬되어 분포되어 있다. 종도체(3)는, 기판(WF1∼WFr)을 관통하는 관통구멍 내에 충전된 관통 전극이라도 좋고, 바닥부가 닫혀져 있는 블라인드 비아 내에 충전된 전극이라도 좋다. 실시형태에 나타내는 종도체(3)는, 지지층(1)을 관통하는 관통 전극으로서, 반도체 회로(6)의 각각마다 구비되며, 일단이 반도체 회로(6)에 접속되어, 반도체 회로(6)에 대한 접속 배선으로서 기능한다.
종도체(3) 및 반도체 회로(6)는, 도 2에 도시하는 바와 같이, 기판면에 상정되는 XY평면에서 보아, X방향 및 Y방향으로 소정의 배치 피치 Lx, Ly를 가지며, 예를 들면, 매트릭스 형상으로 정렬되어 배치된다. 종도체(3)의 디멘젼은, 일례로서 예시하면, 배치 피치 Lx, Ly,가 4∼100㎛의 범위, 최소부의 지름이 0.5∼25㎛의 범위이다. 무엇보다, 배치 피치 Lx, Ly는, 일정 치수일 필요는 없다.
통상, X방향 및 Y방향의 각각에서, 복수개의 종도체(3) 및 반도체 회로(6)를 포함한 영역이, 전자 디바이스로서의 1칩 영역(Q1)을 구성한다. 1칩 영역(Q1)에 포함되는 종도체(3) 및 반도체 회로(6)의 개수는, 실시형태에서는 9개이지만, 전자 디바이스에 따라 변화하는 임의의 수이다. 1칩 영역(Q1)으로부터, 전자 디바이스의 개품(個品)으로서 꺼내기 위해서는, X방향 절단 위치 Cx 및 Y방향 절단 위치 Cy에서 절단한다.
종도체(3)는 도금법, 용융 금속 충전법 또는 도전 페이스트 충전법 등, 공지 기술의 적용에 의해서 형성할 수 있다. 종도체(3)를 조성하는 재료는, 형성 방법에 따라서 다르다. 도금법의 경우에는, 주로 Cu도금막이 이용되고, 용융 금속 충전법의 경우에는, 주석(Sn)을 주성분으로 하는 금속재료에 의해서 구성되고, 필요에 따라서, 인듐(In), 알루미늄(Al) 또는 비스무트(Bi) 등을 함유하고 있어도 좋다.
종도체(3)를 형성하려면, 어느 형성 방법을 취한다고 해도, 그 전에 종공(縱孔)(관통 비아)을 형성할 필요가 있다. 종공(관통 비아)은, CVD법, 레이저 천공법 등, 공지의 기술에 의해서 형성할 수 있다. 종공(관통 비아)의 형성 타이밍으로서는, 반도체 회로(6)를 형성하기 전에 종공(관통 비아)을 형성하는 비아·퍼스트로 불리는 수법과, 반도체 회로(6)를 형성한 후에 종공(관통 비아)을 형성하는 비아·라스트로 불리는 수법이 있으며, 어느 수법을 적용해도 좋다.
자성막(41)은, 종도체(3)의 일단면상에 부착되어 있으며, 자성막(41)의 표면에는, 접합막(42)이 부착되어 있다. 자성막(41)은, 본 발명의 특징적인 부분의 하나이며, 자기적인 위치 맞춤 마커로서 기능한다. 자성막(41)은, Ni, Co 혹은 Fe 또는 이들의 합금을 포함한다.
접합막(42)은, 적층시 접합을 담당하는 부분으로서, Sn, Ag, Au, Cu, Al, In 또는 Bi 등으로부터 선택된 금속재료에 의해서 구성된다. 도시에서는, 1층으로 표시되어 있지만, 전기적 특성 개선, 접합 강도 향상, 용융 특성의 개선 등의 관점으로부터, 상술한 금속재료의 선택적 조합, 또는 상기 금속재료와 그 이외의 금속재료와의 조합이 되는 복수층의 다층 구조로 해도 좋다.
기능층(2)은, 지지층(1)과 적층되는 일면과는 반대쪽의 면(도 1에서 하면)에, 범프(5)를 가지고 있다. 범프(5)는, 종도체(3)와는 반대쪽에 있어서, 반도체 회로(6)에 대한 배선을 구성한다. 도시한 예에서는, 범프(5)는, 제1 접합막(51)과, 자성막(52)과, 제2 접합막(53)을 차례로 적층한 구조로 되어 있다. 제1 접합막(51)은, 적층시 접합을 담당하는 부분이며, 제2 접합막(53)은, 반도체 회로(6)와 접속되는 부분이다. 제1 접합막(51) 및 제2 접합막(53)은, Sn, Ag, Au, Cu, Al, In 또는 Bi 등으로부터 선택된 금속재료에 의해서 구성된다. 도시에서는, 1층 표시로 되어 있지만, 전기적 특성 개선, 접합 강도 향상, 용융 특성의 개선 등의 관점으로부터, 상술한 금속재료의 선택적 조합, 또는 상기 금속재료와 그 이외의 금속재료와의 조합이 되는 복수층의 다층 구조로 해도 좋다. 이 점은, 접합막(42)의 경우와 동일하다.
자성막(52)은, 제1 접합막(51)과 제2 접합막(53) 사이에 형성되고, 자성막 (41)과 마찬가지로, 자기적인 위치 맞춤 마커로서 기능한다. 자성막(52)은, Ni, Co 혹은 Fe 또는 이들의 합금을 포함한다.
적층·위치 맞춤시에는, 도 1에 도시한 바와 같이, 상술한 기판(WF1∼WFr)의 복수매를, 종도체(3)가 서로 겹치도록, 일단 위치 맞춤을 한 다음, 차례로 적층한다. 이 상태에서는, 기판(WFI∼WFr)의 각 종도체(3)는, 일단, 서로 겹치지만, 정확한 위치 맞춤은 되어 있지 않다.
따라서, 적층한 상태에서, 외부로부터 자계 H를 인가하여, 인접한 기판(WF1∼WFr)의 자성막(41-52) 사이에 자기적 흡인력 Fm를 발생시키고, 자기적 흡인력 Fm에 의해 위치 맞춤한다. 예를 들면, 인접한 기판(WF1)과 기판(WF2)을 예로 들면, 기판(WF1)의 자성막(41)과, 기판(WF2)의 자성막(52)의 사이에 자기적 흡인력 Fm가 작용하여, 기판(WF1)의 종도체(3)와 기판(WF2)의 종도체(3)가, 고정밀도로 위치 맞춤된다.
상술한 자기적인 위치 맞춤 조작에 의해, 일단 위치 맞춤 상태에 있던 각 기판(WF1∼WFr)의 종도체(3)가, 더 고정밀도로 위치 맞춤된다. 자계 H는, 도시하지 않은 영구자석 또는 전자석으로 주어진다.
상술한 바와 같이, 본 발명에서는, 적층면이 되는 기판면의 소정 위치에, 자성막(41,52)을 형성해 두고, 인접한 기판(WF1∼WFr)의 자성막(41∼52)의 사이에 자기적 흡인력 Fm를 발생시키고, 자기적 흡인력 Fm에 의해, 기판(WF1∼WFr), 특히 종도체(3)를 위치 맞춤하기 때문에, TSV 기술을 적용하여 전자 디바이스를 제조할 때에, 종래 이용되고 있던 화상 처리와의 대비에서, 기판(WF1∼WFr) 적층시의 위치 맞춤을, 간단하고 또한 확실하게, 고정밀도로 실행할 수 있다.
위치 맞춤 후에는, 열처리를 행하여, 기판(WF1∼WFr)을 접합한다. 이에 따라, 전자 디바이스용 적층체를 얻을 수 있다. 보다 구체적으로는, 도 4에 도시하는 바와 같이, 기판(WF1∼WFr) 중에서, 서로 인접한 기판, 예를 들면, 기판(WF1)과 기판(WF2)에 있어서, 기판(WF1)에 구비된 접합막(42)과, 기판(WF2)에 구비된 범프(5)의 제2 접합막(53)이 접합된다. 접합 프로세스를 자계(磁界) 중에서 실행하면, 그 동안에, 적층된 기판(WF1∼WFr) 사이에 자기적 흡인력을 작용시킬 수 있으므로, 접합 프로세스중에 기판(WF1∼WFr)에 위치 어긋남을 일으키는 경우가 없다.
자성막은, 종도체(3)의 바깥쪽에 위치한 기판면에 형성되어 있어도 좋다. 그 일례를 도 5에 도시한다. 도 5를 참조하면, 기판(WF1∼WFr)의 각각에서, 1칩 영역 (Q1)을 획정하는 X방향 절단 위치 Cx 및 Y방향 절단 위치 Cy에 자성막(61,62)이 형성되어 있다. 자성막(61,62)은, 바람직하게는, 막면이 지지층(1) 및 기능층(2)의 표면과 거의 일치하도록, 지지층(1) 및 기능층(2)에 메워 넣어진다. 종도체(3)의 일단면에는, 자성막이 존재하지 않고, 접합막(4)이 직접 부착되어 있다. 또한, 범프(5)도, 자성막을 갖지 않고, 제1 접합막(51) 및 제2 접합막(53)을 적층한 구조로 되어 있다. 무엇보다, 도 1∼도 4에 도시한 자성막 배치 구조와의 조합을 배제하는 것은 아니다.
상술한 기판(WF1∼WFr)의 복수매를, 종도체(3)가 서로 겹치도록, 일단 위치 맞춤을 한 다음, 차례로 적층한다. 그리고, 적층한 상태에서, 외부로부터 자계 H를 인가하여, 인접한 기판(WF1∼WFr)의 자성막(61-62) 사이에 자기적 흡인력 Fm를 발생시키고, 자기적 흡인력 Fm에 의해 위치 맞춤한다. 이에 따라, 일단 위치 맞춤 상태에 있던 각 기판(WF1∼WFr)의 종도체(3)가, 더 고정밀도로 위치 맞춤된다.
실시형태에서, 자성막(61,62)은, X방향 절단 위치 Cx 및 Y방향 절단 위치 Cy에 형성되어 있기 때문에, 1칩화하기 위해서, X방향 절단 위치 Cx 및 Y방향 절단 위치 Cy로 절단했을 경우, 자성막(61,62)은, 절단날 폭에 의해서 전부 제거되어, 칩 개품에는 남지 않는다.
자성막(61,62)의 패턴은, 자기적 흡인력 Fm에 의한 유효한 위치 맞춤에 기여하는 형태이면 좋다. 그 일례를, 도 6에 도시한다. 도 6에서는, 자성막(61,62)은, 종도체(3)와 동일한 배치 피치로 지지층(1) 또는 기능층(2)에 형성된 구멍 내에 충전되어 있다. 자성막(61,62)은, X방향 절단 위치 Cx 및 Y방향 절단 위치 Cy에, 절단폭보다 작은 직경으로 형성되어 있다. 따라서, 1칩화하기 위해서, X방향 절단 위치 Cx 및 Y방향 절단 위치 Cy에서 절단했을 경우, 자성막(61,62)은, 절단날 폭에 의해서 전부 제거되어, 칩 개품에는 남지 않는다.
자성막(61,62)은, 도시는 하지 않지만, X방향 절단 위치 Cx 및 Y방향 절단 위치 Cy를 따라서, 1칩 영역(Q)을 넘어 직선 형상으로 이어지는 형태나, 직선 형상으로 이어져 있지만, 다른 칩 영역간에서는 불연속이 되고 있는 형태나, 또는, 칩 영역(Q1)의 코너부에 형성되어 있는 형태 등, 여러 가지 형태를 채택할 수 있다.
본 발명에 관한 전자 디바이스는, 대표적으로는, 삼차원 시스템·패키지(3D-SiP)로서의 형태를 취한다. 구체적으로는, 시스템 LSI, 메모리 LSI, 이미지 센서 또는 MEMS 등이다. 아날로그나 디지털의 회로, DRAM와 같은 메모리 회로, CPU와 같은 로직 회로 등을 포함한 전자 디바이스이더라도 좋고, 아날로그 고주파 회로와 저주파로 저소비 전력의 회로와 같은 이종(異種)의 회로를, 각각의 프로세스에 의해서 만들어, 이들을 적층한 전자 디바이스이더라도 좋다.
더 구체적으로는, 센서 모듈, 광전기 모듈, 유니폴라 트랜지스터, MOS FET, CMOS FET, 메모리 셀, 혹은, 이들의 집적회로 부품(IC), 또는 각종 스케일의 LSI 등, 대략, 전자 회로를 기능 요소로 하는 전자 디바이스의 대부분을 포함할 수 있다. 본 발명에서, 집적회로 LSI라 부르는 경우, 소규모 집적회로, 중규모 집적회로, 대규모 집적회로, 초대규모 집적회로 VLSI, ULSI 등의 전부를 포함한다.
본 발명에 관한 제조방법은, 상술한 바와 같이, 극히 광범위한 전자 디바이스의 제조에 적용할 수 있는 것이다. 전자 디바이스 중에는, 도 4에 도시한 바와 같은 적층체 그 자체가, 전자 디바이스의 대부분을 차지하는 것도 존재하고, 혹은, 도 4에 도시한 적층체 위 또는 아래에, 인터포저 등을 통하여, 또는, 인터포저를 통하지 않고, 다른 회로 기능부를 적층하는 구조를 채택하기도 한다.
이상 본 발명은 상기의 바람직한 실시예에 의하여 상세히 기술되었다. 그러나, 당업자라면 본 발명의 근본적인 기술적 사상 및 본 명세서에 개시된 사항에 기초하여 다양한 변형을 용이하게 할 수 있다는 것은 명확하다 할 것이다.

Claims (9)

  1. 복수매의 기판을 위치 맞춤하여 적층하는 공정을 포함한 전자 디바이스의 제조방법으로서,
    상기 복수매의 기판의 각각은, 복수의 종도체(縱導體)와, 자성막을 가지고 있고,
    상기 종도체는, 판두께 방향을 향하여, 기판면에 대해서 정렬되어 분포되어 있으며,
    상기 자성막은, 상기 종도체에 대해서 미리 정해진 위치 관계를 가지며,
    상기 기판면의 소정 위치에 형성되어 있고,
    상기 복수매의 기판을 위치 맞춤할 때에,
    외부로부터 자계를 인가하여, 적층되어 인접한 상기 기판의 상기 자성막의 사이에 자기적 흡인력을 발생시키고,
    상기 자기적 흡인력에 의해 상기 종도체를 위치 맞춤하는 공정을 포함한 전자 디바이스의 제조방법.
  2. 제 1 항에 있어서, 상기 자성막은, 상기 종도체의 적어도 일단면(一端面)상에 형성되어 있는 전자 디바이스의 제조방법.
  3. 제 1 항에 있어서, 상기 자성막은, 상기 종도체의 바깥측에 형성되어 있는 전자 디바이스의 제조방법.
  4. 제 1 항에 있어서, 상기 자성막은, Ni, Co 혹은 Fe 또는 이들의 합금을 포함한 전자 디바이스의 제조방법.
  5. 복수의 종도체와 자성막을 가진 전자 디바이스용 기판으로서, 상기 종도체의 각각은, 판두께 방향을 향하여, 기판면에 대해서 정렬되어 분포되어 있으며,
    상기 자성막은, 상기 종도체에 대해서 미리 정해진 위치 관계를 가지고, 상기 기판면의 소정 위치에 형성되어 있는 기판.
  6. 복수매의 기판을 적층한 전자 디바이스용 적층체로서,
    상기 복수매의 기판은, 제 5 항에 기재된 것으로서 상기 자성막 및 상기 종도체가 위치 맞춤되어, 서로 적층되어 있는 적층체.
  7. 적층체와 회로 기능부를 포함한 전자 디바이스로서,
    상기 적층체는, 제 6 항에 기재된 것이며,
    상기 회로 기능부는, 상기 적층체와 조합되어 있는 전자 디바이스.
  8. 제 7 항에 있어서, 3차원 시스템·패키지(3D-SiP)인 전자 디바이스.
  9. 제 8 항에 있어서, 시스템 LSI, 메모리 LSI, 이미지 센서, 또는 MEMS중의 어느 하나인, 전자 디바이스.
KR1020100125607A 2009-12-11 2010-12-09 전자 디바이스용 기판, 전자 디바이스용 적층체, 전자 디바이스 및 이들의 제조방법 KR20110066866A (ko)

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