JP2009252893A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2009252893A JP2009252893A JP2008097271A JP2008097271A JP2009252893A JP 2009252893 A JP2009252893 A JP 2009252893A JP 2008097271 A JP2008097271 A JP 2008097271A JP 2008097271 A JP2008097271 A JP 2008097271A JP 2009252893 A JP2009252893 A JP 2009252893A
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】半導体装置1は、複数の半導体パッケージ2,3と、スペーサ201とを備える。半導体パッケージ2,3は、スペーサ201を介して積層されている。各半導体パッケージ2,3、パッケージ基板101,111と、パッケージ基板101,111に実装されたに半導体素子102,112とを有する。スペーサ201は、複数の導電ビア204と容量素子202とを有する。半導体パッケージ2,3は、導電ビア204を介して電気的に接続されている。容量素子202は、複数の導電ビア204のうち、半導体素子112と電源とを電気的に接続する導電ビア及び半導体素子112とグランドとを電気的に接続する導電ビアと電気的に接続されている。
【選択図】図2
Description
2 第1半導体パッケージ
3 第2半導体パッケージ
101 第1パッケージ基板
102 第1半導体素子
111 第2パッケージ基板
112 第2半導体素子
201,301,401 スペーサ
102a,112a 電極
103,113,203,204,303,306,403 パッド
106,107,116,117,207,307,407 導電材
201a,301a,401a 電気的接続部
201b,301b 容量素子実装部
201c,301c 貫通孔部
202,302,402 容量素子
104,114,204,304,404 導電ビア
105,115,205,305 配線層
308 ボンディングワイヤ
51 半導体装置
52 第1半導体パッケージ
53 第2半導体パッケージ
601 実装基板
602 容量素子
701 第1パッケージ基板
702 第1半導体素子
711 第2パッケージ基板
712 第2半導体素子
801 スペーサ
603,703,713,803 パッド
605,705,715 配線層
702a,712a 電極
704,714,804 導電ビア
706,707,716,717,806 導電材
Claims (8)
- 半導体素子をパッケージ基板に実装した半導体パッケージを、スペーサを介して複数積層した半導体装置であって、
前記スペーサは、複数の導電ビアと、少なくとも1つの容量素子とを有し、
複数の前記半導体パッケージは、前記導電ビアによって互いに電気的に接続され、
前記容量素子は、前記複数の導電ビアのうち、前記半導体素子と電源とを電気的に接続する第1導電ビア及び前記半導体素子とグランドとを電気的に接続する第2導電ビアと電気的に接続されていることを特徴とする半導体装置。 - 前記スペーサは、前記半導体パッケージの積層方向に貫通された貫通孔部を有する枠体であり、
隣接して積層される2つの半導体パッケージ間に配置される前記半導体素子は、前記2つの半導体パッケージ間に配されるスペーサの前記貫通孔部に挿入されていることを特徴とする請求項1に記載の半導体装置。 - 前記容量素子は、前記スペーサ上に実装され、
前記容量素子と前記第1導電ビア及び前記第2導電ビアとは、前記スペーサ上に形成された配線層によって電気的に接続されていることを特徴とする請求項1又は2に記載の半導体装置。 - 前記スペーサは、前記複数の導電ビアが形成された電気的接続部と、前記容量素子が実装された容量素子実装部とを有し、
前記半導体パッケージの積層方向の前記容量素子実装部の厚さは、前記電気的接続部の厚さより薄いことを特徴とする請求項1又は2に記載の半導体装置。 - 前記容量素子は、前記導電ビアとワイヤボンディングによって電気的に接続されていることを特徴とする請求項4に記載の半導体装置。
- 前記容量素子は前記スペーサに内蔵されていることを特徴とする請求項1に記載の半導体装置。
- 前記スペーサは、誘電体と、前記誘電体中に積層された複数の導電体層とをさらに有し、
複数の導電体層は、前記第1導電ビアと電気的に接続された第1導電体層と、前記第2導電ビアと電気的に接続された第2導電体層と、を有し、
前記容量素子は、前記第1導電体層と前記第2導電体層とが前記誘電体を介して交互に積層されることにより形成されていることを特徴とする請求項6に記載の半導体装置。 - 前記第1導電体層及び前記第2導電体層は、前記複数の導電ビアのうち信号用の第3導電ビアとは電気的に接続されていないことを特徴とする請求項7に記載の半導体装置。
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JP2008097271A JP2009252893A (ja) | 2008-04-03 | 2008-04-03 | 半導体装置 |
US12/385,138 US20090250801A1 (en) | 2008-04-03 | 2009-03-31 | Semiconductor device |
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JP2008097271A JP2009252893A (ja) | 2008-04-03 | 2008-04-03 | 半導体装置 |
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JP2008097271A Pending JP2009252893A (ja) | 2008-04-03 | 2008-04-03 | 半導体装置 |
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JP (1) | JP2009252893A (ja) |
Cited By (1)
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JP2014112606A (ja) * | 2012-12-05 | 2014-06-19 | Shinko Electric Ind Co Ltd | 半導体パッケージ |
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JP5341717B2 (ja) | 2009-11-10 | 2013-11-13 | ルネサスエレクトロニクス株式会社 | 半導体パッケージ及びシステム |
US9016552B2 (en) * | 2013-03-15 | 2015-04-28 | Sanmina Corporation | Method for forming interposers and stacked memory devices |
JP6119845B2 (ja) * | 2013-04-16 | 2017-04-26 | 株式会社村田製作所 | 高周波部品およびこれを備える高周波モジュール |
US11183765B2 (en) | 2020-02-05 | 2021-11-23 | Samsung Electro-Mechanics Co., Ltd. | Chip radio frequency package and radio frequency module |
US11101840B1 (en) * | 2020-02-05 | 2021-08-24 | Samsung Electro-Mechanics Co., Ltd. | Chip radio frequency package and radio frequency module |
WO2023132595A1 (ko) * | 2022-01-04 | 2023-07-13 | 주식회사 아모센스 | 세라믹 기판 유닛 및 그 제조방법 |
KR20240032231A (ko) * | 2022-09-01 | 2024-03-12 | 주식회사 아모그린텍 | 세라믹 기판 유닛 및 그 제조방법 |
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JPH11260999A (ja) * | 1998-03-13 | 1999-09-24 | Sumitomo Metal Ind Ltd | ノイズを低減した積層半導体装置モジュール |
JP2001274036A (ja) * | 2000-03-28 | 2001-10-05 | Fujitsu Ltd | フィルム状コンデンサ及びその製造方法 |
JP2005217348A (ja) * | 2004-02-02 | 2005-08-11 | Matsushita Electric Ind Co Ltd | 立体的電子回路装置およびその中継基板と中継枠 |
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JP2014112606A (ja) * | 2012-12-05 | 2014-06-19 | Shinko Electric Ind Co Ltd | 半導体パッケージ |
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