JP4351214B2 - 電子装置及びその製造方法 - Google Patents
電子装置及びその製造方法 Download PDFInfo
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- JP4351214B2 JP4351214B2 JP2005515288A JP2005515288A JP4351214B2 JP 4351214 B2 JP4351214 B2 JP 4351214B2 JP 2005515288 A JP2005515288 A JP 2005515288A JP 2005515288 A JP2005515288 A JP 2005515288A JP 4351214 B2 JP4351214 B2 JP 4351214B2
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- H01L2924/11—Device type
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Description
上記の一体化工程が終了すると、第1の絶縁層25の形成処理が実施される。この際、図12Cに示されるように、第1の絶縁層25は保護層17の外周面と貫通孔31Bの内周面との間の間隙内にも充填される。尚、第1の絶縁層25の形成処理が終了した後の工程は、図2A乃至図4Dを用いて説明した第1実施例に係る半導体装置10Aの製造方法と同一であるため、その説明は省略する。
10S〜10V 電子装置
11 半導体チップ
13 電極
14 バリアメタル
15 絶縁膜
16 チップ側PI膜
17 保護層
20A〜20V インターポーザ
21A〜21M インターポーザ基材
22A,22B ポスト電極
23 再配線層
24 外部接続端子
25 第1の絶縁層
26 第2の絶縁層
27 接合補助部材
28 インターポーザ側PI膜
29 補強部材
30,39 段差部
31A〜31C 貫通孔
32 第1のレジスト材
33,36,37 開口部
34 電極用孔
35 第2のレジスト材
40A〜40D キャビティ部
46A,46B 封止樹脂
50A〜50C チップ部品
52 第1のクラッド層
53 第2のクラッド層
54 コア層
55 発光素子
56 受光素子
57 販社部材
59 配線パターン
60,61 ポスト状電極
Claims (17)
- 電子素子と、
前記電子素子が接合されるインターポーザ基材と、前記電子素子の電極と接続される複数のポスト電極とを有するインターポーザとを具備する電子装置において、
前記電子素子と前記インターポーザ基材とを直接接触させることにより一体化すると共に、前記ポスト電極を前記電子素子の電極上に直接形成した構成としたことを特徴とする電子装置。 - 電子素子と、
前記電子素子が接合されるインターポーザ基材と、該インターポーザ基材に形成された貫通孔内に配設され前記電子素子の電極と接続される複数のポスト電極とを有するインターポーザとを具備する電子装置において、
前記電子素子の表面と前記インターポーザ基材の表面とを直接接触させることにより一体化すると共に、前記ポスト電極を前記電子素子の電極上に直接形成した構成としたことを特徴とする電子装置。 - 請求項1または2記載の電子装置において、
前記電子素子の材質と前記インターポーザ基材の材質が同一であることを特徴とする電子装置。 - 請求項1または2記載の電子装置において、
前記電子素子の材質と前記インターポーザ基材の材質を共にシリコンであることを特徴とする電子装置。 - 請求項1または2記載の電子装置において、
前記電子素子は、少なくとも前記インターポーザ基材と接合する位置に第1の絶縁材層を含み、
前記インターポーザ基材は、少なくとも前記電子素子と接合する位置に第2の絶縁層を含むことを特徴とする電子装置。 - 請求項2記載の電子装置において、
複数の前記ポスト電極が、ひとつの前記貫通孔内に配設されていることを特徴とする電子装置。 - 請求項1または2記載の電子装置において、
前記インターポーザ基材に段差部を形成し、該電子素子を前記段差部内に前記電子素子を収納する構成としたことを特徴とする電子装置。 - 請求項1または2記載の電子装置において、
前記インターポーザ基材は複数の前記電子素子が搭載されてなることを特徴とする電子装置。 - 請求項1または2記載の電子装置において、
前記インターポーザ基材は前記電子素子の背面部と接合してなることを特徴とする電子装置。 - 請求項1または2記載の電子装置において、
前記電子素子を封止する封止樹脂を前記インターポーザ基材に配設したことを特徴とする電子装置。 - 請求項1または2記載の電子装置において、
前記電子素子は半導体チップであることを特徴とする電子装置。 - 請求項1または2記載の電子装置において、
前記電子素子は受動素子であることを特徴とする電子装置。 - 貫通孔が形成されたインターポーザ基材の表面と電子素子の表面とを直接接触させることにより、前記インターポーザ基材と前記電子素子とを一体化する一体化工程と、
該一体化工程の終了後、前記貫通孔内でかつ前記電子素子の電極上にポスト電極を直接形成するポスト電極形成工程と、
前記ポスト電極と電気的に接続される再配線層を形成する再配線形成工程と、
前記再配線上に外部接続電極を形成する外部接続電極形成工程と
を有することを特徴とする電子装置の製造方法。 - 電子素子の電極上にポスト電極を直接形成するポスト電極形成工程と、
該ポスト電極形成工程の終了後、貫通孔が形成されたインターポーザ基材の表面と電子素子の表面とを直接接触させ、前記インターポーザ基材と前記電子素子とを一体化する一体化工程と、
前記ポスト電極と電気的に接続される再配線層を形成する再配線形成工程と、
前記再配線上に外部接続電極を形成する外部接続電極形成工程と
を有することを特徴とする電子装置の製造方法。 - 請求項14記載の電子装置の製造方法において、
前記ポスト電極を保持する絶縁材よりなる保護層を前記電子素子に形成する保護層形成工程を有することを特徴とする電子装置の製造方法。 - 電子素子と、
前記電子素子が接合されるインターポーザとを具備する電子装置において、
前記電子素子と前記インターポーザとを直接接触させることにより一体化した構成としたことを特徴とする電子装置。 - 請求項16記載の電子装置において、
前記電子素子は光デバイスであり、
前記インターポーザには、前記光デバイスと光学的に接続される光導波路が設けられていることを特徴とする電子装置。
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