JP4178417B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4178417B2 JP4178417B2 JP2005214218A JP2005214218A JP4178417B2 JP 4178417 B2 JP4178417 B2 JP 4178417B2 JP 2005214218 A JP2005214218 A JP 2005214218A JP 2005214218 A JP2005214218 A JP 2005214218A JP 4178417 B2 JP4178417 B2 JP 4178417B2
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims description 73
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000000034 method Methods 0.000 claims description 34
- 238000007689 inspection Methods 0.000 claims description 33
- 239000000523 sample Substances 0.000 claims description 20
- 238000003825 pressing Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 7
- 238000012216 screening Methods 0.000 claims description 5
- 238000005520 cutting process Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 44
- 230000004888 barrier function Effects 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- 238000002161 passivation Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2868—Complete testing stations; systems; procedures; software aspects
- G01R31/287—Procedures; Software aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2881—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to environmental aspects other than temperature, e.g. humidity or vibrations
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Environmental & Geological Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
半導体チップとなるチップ領域が形成されたウェハを準備する工程と、
前記ウェハをプロービングによって検査する第1プローブ検査と、
平坦面を有する加圧部材によって、前記ウェハの電極を押圧する工程と、
前記ウェハをプロービングによって検査する第2プローブ検査と、
を含む。
半導体チップとなるチップ領域が形成されたウェハを準備する工程と、
前記ウェハをプロービングによって検査する第1プローブ検査と、
平坦面を有する加圧部材によって、前記ウェハの電極を押圧する工程と、
前記ウェハをプロービングによって検査する第2プローブ検査と、
前記ウェハを切断して半導体チップを形成する工程と、
を含む。
(a) まず、ウェハは、プローブ装置を用いて、プロービングによる第1プローブ検査(S1)が行われる。プローブ検査は特に限定されず、公知の方法を採用できる。例えば、プローブ検査は、図3に示すように、半導体ウェハのチップ領域12に形成された電極14にプローブカードのプローブ針を接触させてプローブ針から所定の電圧を印加し、テスタによって各チップ領域12の導通試験などの電気的検査を行う。プローブ検査は、1個のチップ領域12または複数個のチップ領域12毎にプローブ針を電極14に接触させて行い、例えば図3において矢印で示すように、チップ領域12を順次検査することができる。
(b) ついで、加圧部材によって、ウェハの電極14を押圧する(S2)。この工程では、図2に示すように、平坦面22を有する加圧部材20を、平坦面22が下になる状態で下降させ、該平坦面22を電極14の上面に接触させる。そして、加圧部材20をされらに下降させて、電極14に所定の圧力がかかるように該電極14を押圧する。さらに、電極14の加熱による影響を検査したい場合には、加圧部材20を加熱した状態でこの押圧操作を行うことができる。
電極14にかかる荷重 30MPa 45MPa
電極14の温度 300℃以下 300〜350℃
この工程(b)での押圧・加熱操作は、1つのチップ領域12あるいは複数のチップ領域12毎に行うことができる。また、この工程(b)で、電極14のバンプ18の上面が平坦化される。
(c) ついで、第1プローブ検査と同様に、ウェハをプロービングによって検査する第2プローブ検査を行う(S3)。このプローブ検査によって、上記工程(b)での加圧工程、あるいは加圧・加熱工程によって発生した故障を検出することができる。
Claims (7)
- 複数のチップ領域が形成されたウェハを準備する工程と、
前記ウェハをプロービングによって検査する第1プローブ検査と、
平坦面を有する加圧部材によって、第1荷重および第1温度で前記ウェハの電極を押圧する工程と、
前記ウェハをプロービングによって検査する第2プローブ検査を行うことにより、複数の前記チップ領域をスクリーニングする工程と、
前記ウェハを切断して、複数の半導体チップを形成する工程と、
前記スクリーニングの工程を通過した前記半導体チップを第2荷重および第2温度で実装する工程と、をこの順序で含み、
前記第1荷重は、前記第2荷重より大きく、
前記第1温度は、前記第2温度より高い、半導体装置の製造方法。 - 請求項1において、
前記第1温度は、加熱された温度である、半導体装置の製造方法。 - 請求項1または2において、
前記電極を押圧する工程において、該電極の上面が平坦化される、半導体装置の製造方法。 - 請求項1ないし3のいずれか1項において、
前記加圧部材は、実装基板の配線部と半導体チップの電極とを一括して接続するために用いられるボンディングツールを兼用する、半導体装置の製造方法。 - 請求項1ないし4のいずれか1項において、
前記チップ領域において、前記電極の下方に半導体素子が形成されている、半導体ウェハの検査方法。 - 請求項1ないし5のいずれか1項において、
前記実装する工程は、COG実装である、半導体装置の製造方法。 - 請求項1ないし6のいずれか1項において、
半導体ウェハの段階で、前記実装の時に発生する前記半導体チップの故障を予め検出できる、半導体装置の製造方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005214218A JP4178417B2 (ja) | 2005-07-25 | 2005-07-25 | 半導体装置の製造方法 |
US11/458,781 US20070018675A1 (en) | 2005-07-25 | 2006-07-20 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,377 US20070259459A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,437 US7573256B2 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,309 US20070254388A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,278 US7598730B2 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,449 US20070259461A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005214218A JP4178417B2 (ja) | 2005-07-25 | 2005-07-25 | 半導体装置の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008178234A Division JP4888666B2 (ja) | 2008-07-08 | 2008-07-08 | 半導体ウェハの検査方法および半導体チップの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007035772A JP2007035772A (ja) | 2007-02-08 |
JP4178417B2 true JP4178417B2 (ja) | 2008-11-12 |
Family
ID=37678477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005214218A Expired - Fee Related JP4178417B2 (ja) | 2005-07-25 | 2005-07-25 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
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US (6) | US20070018675A1 (ja) |
JP (1) | JP4178417B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008306105A (ja) * | 2007-06-11 | 2008-12-18 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JP4888666B2 (ja) * | 2008-07-08 | 2012-02-29 | セイコーエプソン株式会社 | 半導体ウェハの検査方法および半導体チップの製造方法 |
Family Cites Families (24)
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JPS5787145A (en) | 1980-11-20 | 1982-05-31 | Seiko Epson Corp | Semiconductor device |
JPS5923530A (ja) * | 1982-07-30 | 1984-02-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPS6386541A (ja) | 1986-09-30 | 1988-04-16 | Toshiba Corp | 半導体チツプの実装法 |
US6288561B1 (en) * | 1988-05-16 | 2001-09-11 | Elm Technology Corporation | Method and apparatus for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus |
US5556810A (en) * | 1990-06-01 | 1996-09-17 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating |
US5148266A (en) * | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
US6219908B1 (en) * | 1991-06-04 | 2001-04-24 | Micron Technology, Inc. | Method and apparatus for manufacturing known good semiconductor die |
JPH05283490A (ja) | 1992-04-02 | 1993-10-29 | Fuji Electric Co Ltd | 集積回路装置の試験方法 |
JP3383329B2 (ja) * | 1992-08-27 | 2003-03-04 | 株式会社東芝 | 半導体装置の製造方法 |
JPH07115113A (ja) * | 1993-08-25 | 1995-05-02 | Nec Corp | 半導体ウエハの試験装置および試験方法 |
US6258609B1 (en) * | 1996-09-30 | 2001-07-10 | Micron Technology, Inc. | Method and system for making known good semiconductor dice |
JPH10186393A (ja) * | 1996-12-19 | 1998-07-14 | Shin Etsu Polymer Co Ltd | 液晶表示パネルの表示検査用コネクタ及びその製造方法 |
US5836071A (en) * | 1996-12-26 | 1998-11-17 | Texas Instrument Incorporated | Method to produce known good die using temporary wire bond, die attach and packaging |
US5952840A (en) * | 1996-12-31 | 1999-09-14 | Micron Technology, Inc. | Apparatus for testing semiconductor wafers |
US6048750A (en) * | 1997-11-24 | 2000-04-11 | Micron Technology, Inc. | Method for aligning and connecting semiconductor components to substrates |
US6233184B1 (en) * | 1998-11-13 | 2001-05-15 | International Business Machines Corporation | Structures for wafer level test and burn-in |
JP2001091544A (ja) * | 1999-09-27 | 2001-04-06 | Hitachi Ltd | 半導体検査装置の製造方法 |
JP2002110751A (ja) * | 2000-10-03 | 2002-04-12 | Hitachi Ltd | 半導体集積回路装置の検査装置および製造方法 |
TW508987B (en) * | 2001-07-27 | 2002-11-01 | Phoenix Prec Technology Corp | Method of forming electroplated solder on organic printed circuit board |
JP3759909B2 (ja) * | 2002-02-22 | 2006-03-29 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP2003309050A (ja) | 2002-04-17 | 2003-10-31 | Hitachi Ltd | 半導体装置の製造方法 |
TWI236723B (en) * | 2002-10-02 | 2005-07-21 | Renesas Tech Corp | Probe sheet, probe card, semiconductor inspection device, and manufacturing method for semiconductor device |
US7160797B2 (en) * | 2004-05-12 | 2007-01-09 | Kulicke And Soffa Industries, Inc. | Method of bumping die pads for wafer testing |
US7279919B2 (en) * | 2005-01-14 | 2007-10-09 | Verigy (Singapore) Pte. Ltd. | Systems and methods of allocating device testing resources to sites of a probe card |
-
2005
- 2005-07-25 JP JP2005214218A patent/JP4178417B2/ja not_active Expired - Fee Related
-
2006
- 2006-07-20 US US11/458,781 patent/US20070018675A1/en not_active Abandoned
-
2007
- 2007-07-10 US US11/775,437 patent/US7573256B2/en not_active Expired - Fee Related
- 2007-07-10 US US11/775,449 patent/US20070259461A1/en not_active Abandoned
- 2007-07-10 US US11/775,278 patent/US7598730B2/en not_active Expired - Fee Related
- 2007-07-10 US US11/775,309 patent/US20070254388A1/en not_active Abandoned
- 2007-07-10 US US11/775,377 patent/US20070259459A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20070018675A1 (en) | 2007-01-25 |
US7598730B2 (en) | 2009-10-06 |
US7573256B2 (en) | 2009-08-11 |
US20070259458A1 (en) | 2007-11-08 |
US20070259460A1 (en) | 2007-11-08 |
US20070259459A1 (en) | 2007-11-08 |
US20070259461A1 (en) | 2007-11-08 |
JP2007035772A (ja) | 2007-02-08 |
US20070254388A1 (en) | 2007-11-01 |
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