US20070018675A1 - Semiconductor wafer examination method and semiconductor chip manufacturing method - Google Patents
Semiconductor wafer examination method and semiconductor chip manufacturing method Download PDFInfo
- Publication number
- US20070018675A1 US20070018675A1 US11/458,781 US45878106A US2007018675A1 US 20070018675 A1 US20070018675 A1 US 20070018675A1 US 45878106 A US45878106 A US 45878106A US 2007018675 A1 US2007018675 A1 US 2007018675A1
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- United States
- Prior art keywords
- wafer
- semiconductor
- electrode
- examination
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000003825 pressing Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 description 36
- 239000000523 sample Substances 0.000 description 19
- 230000008569 process Effects 0.000 description 12
- 238000009413 insulation Methods 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000012216 screening Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000011112 process operation Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- -1 e.g. Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2868—Complete testing stations; systems; procedures; software aspects
- G01R31/287—Procedures; Software aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2881—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to environmental aspects other than temperature, e.g. humidity or vibrations
Definitions
- the present invention relates to a semiconductor wafer examination method by wafer probing, and a semiconductor chip manufacturing method.
- a semiconductor wafer formed with a plurality of semiconductor chips is subjected to an electric examination on a semiconductor chip basis so that screening is performed to find any defective piece.
- Such an examination includes a probe examination by probing.
- the wafer is generally diced so that chips are formed. This thus may cause a failure to some semiconductor devices of the semiconductor chips if heat and pressure act on the electrodes of the semiconductor chips in the subsequent process of semiconductor chip implementation, for example.
- a failure detection is no sooner than semiconductor chip implementation, e.g., during the package check.
- An advantage of some aspects of the invention is to provide a semiconductor wafer examination method with which screening is performed at an earlier stage with high accuracy to find any possible failure.
- Another advantage of some aspects of the invention is to provide a semiconductor chip manufacturing method using the examination method of the invention.
- the invention is directed to a semiconductor wafer examination method that includes: a step of preparing a wafer formed with a chip area for use as a semiconductor chip; a first probe examination in which the wafer is examined by probing; a step of pressing an electrode of the wafer with a pressure member having a flat surface; and a second probe examination in which the wafer is examined by probing.
- any failure that is highly likely to occur to a semiconductor wafer e.g., at the time of semiconductor chip implementation, can be detected in advance so that screening can be performed with better reliability. This favorably leads to the reduction of failure occurrence so that the resulting semiconductor chip can be high in reliability.
- the electrode in the step of pressing the electrode, the electrode can be heated.
- an upper surface of the electrode in the step of pressing the electrode, an upper surface of the electrode can be made flat.
- the pressure member can use a bonding tool.
- a semiconductor device in the chip area, can be formed below the electrode.
- the invention is also directed to a semiconductor chip manufacturing method that includes: a step of preparing a wafer formed with a chip area for use as a semiconductor chip; a first probe examination in which the wafer is examined by probing; a step of pressing an electrode of the wafer with a pressure member having a flat surface; a second probe examination in which the wafer is examined by probing; and a step of forming the semiconductor chip by dicing the wafer.
- the resulting semiconductor chip manufactured by such an examination method can be less likely to cause a failure.
- FIG. 1 is a diagram showing the procedure in an embodiment of the invention.
- FIG. 2 is a diagram showing process operations in the embodiment of the invention.
- FIG. 3 is another diagram showing the process operations in the embodiment of the invention.
- FIG. 4 is a diagram showing the partial configuration of a semiconductor wafer in the embodiment of the invention.
- FIG. 1 is a diagram for illustrating a semiconductor wafer examination method of the embodiment.
- FIG. 2 is a cross sectional diagram schematically showing a process of the semiconductor wafer examination method.
- FIG. 3 is a schematic plan view of a wafer being an examination object.
- FIG. 4 is a schematic cross sectional view of a part of a chip area.
- a wafer is prepared for examination use. As shown in FIGS. 2 and 3 , this wafer is configured by a semiconductor substrate 10 formed with a plurality of chip areas 12 , which serve as semiconductor chips after wafer dicing.
- the chip areas 12 are provided with an integrated circuit that is not shown.
- the integrated circuit is not specifically defined by configuration, and may include an active element such as transistor or a passive element such as resistor, coil, or capacitor.
- the chip areas 12 are each provided with electrodes 14 for connection use.
- the electrode 14 can be electrically connected to the inside of each corresponding chip area 12 .
- the term electrode 14 may include any other electrodes not electrically connected to the chip areas 12 .
- the electrode 14 may be configured to include a pad 16 , and a bump 18 formed on the pad 16 .
- the bump 18 may be a gold bump, or a nickel bump with gold plating.
- the wafer is examined in the procedure of FIG. 1 .
- the wafer is first examined using a probe device by probing, i.e., a first probe examination (S 1 ).
- the probe examination is not specifically defined in manner, and any known technique will be adopted.
- the electrodes 14 formed to the chip areas 12 of the semiconductor wafer are brought in contact with a probe needle of a probe card for voltage application of a predetermined level from the probe needle.
- the chip areas 12 are then examined electrically using a tester, e.g., continuity test.
- the probe needle is brought in contact with the electrodes 14 on the basis of the chip area 12 or of a plurality of chip areas 12 so that the chip areas 12 can be examined sequentially as indicated by an arrow of FIG. 3 , for example.
- the electrodes 14 of the wafer are then pressed with a pressure member (S 2 ).
- a pressure member 20 having a flat surface 22 is moved downward with the flat surface 22 facing down, and the flat surface 22 is brought in contact with the upper surfaces of the electrodes 14 .
- the pressure member 20 is then moved downward again to press the electrodes 14 for application thereto of a predetermined level of pressure. If a user wants to check the influence as a result of heating of the electrodes 14 , the electrodes are to be pressed while the pressure member 20 is being heated.
- the electrodes 14 are pressed against the wiring section of the substrate while being heated using a bonding tool. If a user wants to check the resulting influence, the electrodes 14 may be pressed and heated in the process b with more strict requirements for implementation so that the influence can be checked with better reliability.
- COG Process b Load on Electrodes 14 30 MPa 45 MPa Temperature of Electrodes 14 300 degrees or lower 300 to 350 degrees
- the pressurization/heating operation in the process b can be applied on the basis of the chip area 12 or of a plurality of chip areas 12 .
- the bump 18 of each of the electrodes 14 is made flat on the upper surface.
- the pressure member 20 is not specifically restrictive as long as being adjustable at least for pressurization, preferably, being adjustable for both pressurization and heating.
- the pressure member 20 may serve also as a bonding tool for use for a collective connection between the wiring section of the substrate and the electrodes of the semiconductor chips.
- the wafer is then examined by probing, i.e., a second probe examination (S 3 ), similarly to the first probe examination.
- This probe examination enables to detect any failure occurred as a result of the probe examination, i.e., in the pressurization operation in the process b, or the pressurization/heating operation therein.
- the examination technique of this embodiment is applicable to a semiconductor wafer with semiconductor chips of a general type.
- the examination technique is useful also to examine a semiconductor wafer including a semiconductor unit of the following type.
- the semiconductor device is formed with semiconductor devices such as MIS (Metal Insulator Semiconductor) transistor 30 also below the electrode 14 .
- the semiconductor substrate 10 is formed with a device isolation insulation layer 20 .
- the device isolation insulation layer 20 can be formed by STI (Shallow Trench Isolation), LOCOS (Local Oxidation of Silicon), semi-recessed LOCOS, and others.
- the device isolation insulation layer 20 of FIG. 4 is the one formed by STI.
- the MIS transistor 30 is formed in an area 10 A directly below the electrode 14 .
- an MIS transistor 40 is provided similarly to the area 10 A.
- the MIS transistor 30 is configured to include a gate insulation layer 32 , a gate electrode 34 provided on the gate insulation layer 32 , and an impurity region 36 formed to the semiconductor substrate 10 .
- the impurity region 36 serves as a source or drain region.
- the MIS transistor 40 is configured similarly to the MIS transistor 30 , including a gate insulation layer 42 , a gate electrode 44 , and an impurity region 46 .
- the gate electrodes 34 and 44 are each configured by a polysilicon layer, a polycide layer, or others.
- the MIS transistors 30 and 40 may each include a sidewall insulation layer.
- a reference numeral 14 denotes a wiring layer.
- inter-layer insulation layers 50 and 60 are so formed in this order as to cover the MIS transistors 30 and 40 .
- the inter-layer insulation layers 50 and 60 are each made of a known general material.
- a wiring layer 52 of a predetermined pattern is formed, and an electrical connection is established by a contact layer 54 between the wiring layer 52 and the impurity region 36 of the MIS transistor 30 .
- the inter-layer insulation layer 60 is formed thereon with the pad 16 .
- the pad 16 establishes an electrical connection by the wiring layer 52 and a contact layer 64 .
- the pad 16 is formed by a metal such as aluminum or copper.
- the semiconductor unit may be also formed with a passivation layer 70 , which is formed with an aperture 72 from which at least a part of the pad 16 is exposed.
- the aperture 72 may be so formed as to expose therefrom only the center portion of the pad 16 . That is, the passivation layer 70 may be so formed as to cover the peripheral portion of the pad 16 .
- the passivation layer 70 may be formed by SiO 2 , SiN, polyimide resin, or others.
- the aperture 72 is formed with the bump 18 , i.e., the bump 18 is formed on the exposure surface of the pad 16 .
- the bump 18 is so formed as to reach over the passivation layer 70 .
- the bump 18 is formed by a single or a plurality of layers, and is made of a metal such as gold, nickel, or copper.
- the bump 18 is not specifically defined by outer shape, and may be formed rectangular (including square and rectangle), or formed circular. The outer dimension of the bump 18 may be smaller than that of the pad 16 . With this being the case, the bump 18 may be formed only in an area overlapping the pad 16 .
- a barrier layer may be formed at the bottom of the bump 18 .
- the barrier layer may serve to prevent material dissipation for both the pad 16 and the bump 18 .
- the barrier layer may be formed by a single or a plurality of layers, and may be formed by sputtering.
- the barrier layer may be also made to improve the adhesion between the pad 16 and the bump 18 .
- the barrier layer may include a titanium tungsten (TiW) layer.
- TiW titanium tungsten
- the top surface of the barrier layer may be an electroplated metal layer, e.g., Au layer, for deposition of the bump 18 .
- the MIS transistor 30 is formed below the electrode 14 , if the electrode 14 is pressurized and heated when being connected to any other component, not only the electrode 14 but also the components therebelow are affected thereby. As a result, this easily leads to failures of the devices compared with a case where the electrode 14 is formed therebelow with no device such as MIS transistor. With the examination method of this embodiment, however, the processes b and c enable to detect failures being highly likely to occur as a result of semiconductor chip implementation even prior to the implementation. This is surely applicable to a case where no MIS transistor is formed below the electrode 14 .
- the wafer is diced by any known dicing technique so that semiconductor chips can be formed.
- any failures that are highly likely to occur as a result of semiconductor chip implementation can be detected beforehand, e.g., in the form of semiconductor wafer, so that screening can be performed with better reliability with respect to the resulting semiconductor chips.
- This favorably reduces the failure frequency of the semiconductor chips for use, and the resulting semiconductor chips can be increased in reliability.
- Such characteristics are considered advantageous especially with a semiconductor wafer in which devices such as MIS transistors are formed below the electrodes.
- the upper surfaces of the electrodes 14 are pressed, preferably, pressed and heated so that the upper surface of the bump 18 of each of the electrodes 14 can be made flat.
- the bump 18 can be flat enough, and the electrodes 14 are highly reliable in terms of connection.
- the invention includes any configuration substantially the same as the configurations described in the embodiment, e.g., configurations leading to the same functions, methods, and results, or configurations leading to the same objects and effects.
- the invention also includes any configuration in which a component(s) are changed if not essential.
- the invention also includes any configuration leading to the same effects or achieving the same objects as those described in the embodiment.
- the invention also includes any configuration in which any known technique is taken into consideration for the configurations described in the embodiment.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Environmental & Geological Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/775,377 US20070259459A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,449 US20070259461A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,309 US20070254388A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,278 US7598730B2 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,437 US7573256B2 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005-214218 | 2005-07-25 | ||
JP2005214218A JP4178417B2 (ja) | 2005-07-25 | 2005-07-25 | 半導体装置の製造方法 |
Related Child Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/775,377 Division US20070259459A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,309 Division US20070254388A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,449 Division US20070259461A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,437 Division US7573256B2 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,278 Division US7598730B2 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
Publications (1)
Publication Number | Publication Date |
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US20070018675A1 true US20070018675A1 (en) | 2007-01-25 |
Family
ID=37678477
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/458,781 Abandoned US20070018675A1 (en) | 2005-07-25 | 2006-07-20 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,278 Expired - Fee Related US7598730B2 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,309 Abandoned US20070254388A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,377 Abandoned US20070259459A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,449 Abandoned US20070259461A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,437 Expired - Fee Related US7573256B2 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
Family Applications After (5)
Application Number | Title | Priority Date | Filing Date |
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US11/775,278 Expired - Fee Related US7598730B2 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,309 Abandoned US20070254388A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,377 Abandoned US20070259459A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,449 Abandoned US20070259461A1 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
US11/775,437 Expired - Fee Related US7573256B2 (en) | 2005-07-25 | 2007-07-10 | Semiconductor wafer examination method and semiconductor chip manufacturing method |
Country Status (2)
Country | Link |
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US (6) | US20070018675A1 (ja) |
JP (1) | JP4178417B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008306105A (ja) * | 2007-06-11 | 2008-12-18 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JP4888666B2 (ja) * | 2008-07-08 | 2012-02-29 | セイコーエプソン株式会社 | 半導体ウェハの検査方法および半導体チップの製造方法 |
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JPS5923530A (ja) * | 1982-07-30 | 1984-02-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPS6386541A (ja) | 1986-09-30 | 1988-04-16 | Toshiba Corp | 半導体チツプの実装法 |
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JP2003309050A (ja) | 2002-04-17 | 2003-10-31 | Hitachi Ltd | 半導体装置の製造方法 |
US7279919B2 (en) * | 2005-01-14 | 2007-10-09 | Verigy (Singapore) Pte. Ltd. | Systems and methods of allocating device testing resources to sites of a probe card |
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2005
- 2005-07-25 JP JP2005214218A patent/JP4178417B2/ja not_active Expired - Fee Related
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2006
- 2006-07-20 US US11/458,781 patent/US20070018675A1/en not_active Abandoned
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2007
- 2007-07-10 US US11/775,278 patent/US7598730B2/en not_active Expired - Fee Related
- 2007-07-10 US US11/775,309 patent/US20070254388A1/en not_active Abandoned
- 2007-07-10 US US11/775,377 patent/US20070259459A1/en not_active Abandoned
- 2007-07-10 US US11/775,449 patent/US20070259461A1/en not_active Abandoned
- 2007-07-10 US US11/775,437 patent/US7573256B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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JP4178417B2 (ja) | 2008-11-12 |
JP2007035772A (ja) | 2007-02-08 |
US20070259460A1 (en) | 2007-11-08 |
US7598730B2 (en) | 2009-10-06 |
US20070259461A1 (en) | 2007-11-08 |
US20070259459A1 (en) | 2007-11-08 |
US20070259458A1 (en) | 2007-11-08 |
US7573256B2 (en) | 2009-08-11 |
US20070254388A1 (en) | 2007-11-01 |
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