JP4101901B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP4101901B2
JP4101901B2 JP10867197A JP10867197A JP4101901B2 JP 4101901 B2 JP4101901 B2 JP 4101901B2 JP 10867197 A JP10867197 A JP 10867197A JP 10867197 A JP10867197 A JP 10867197A JP 4101901 B2 JP4101901 B2 JP 4101901B2
Authority
JP
Japan
Prior art keywords
film
silicon
titanium
titanium film
refractory metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10867197A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10303145A5 (https=
JPH10303145A (ja
Inventor
耕太郎 片岡
浩 岩田
雅行 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP10867197A priority Critical patent/JP4101901B2/ja
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to KR10-1998-0710275A priority patent/KR100399492B1/ko
Priority to EP98917666A priority patent/EP0928021B1/en
Priority to DE69837909T priority patent/DE69837909T2/de
Priority to PCT/JP1998/001892 priority patent/WO1998049724A1/ja
Priority to US09/202,714 priority patent/US6562699B1/en
Publication of JPH10303145A publication Critical patent/JPH10303145A/ja
Priority to US10/394,024 priority patent/US7135386B2/en
Publication of JPH10303145A5 publication Critical patent/JPH10303145A5/ja
Application granted granted Critical
Publication of JP4101901B2 publication Critical patent/JP4101901B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP10867197A 1997-04-25 1997-04-25 半導体装置の製造方法 Expired - Fee Related JP4101901B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP10867197A JP4101901B2 (ja) 1997-04-25 1997-04-25 半導体装置の製造方法
EP98917666A EP0928021B1 (en) 1997-04-25 1998-04-23 Process for manufacturing semiconductor device
DE69837909T DE69837909T2 (de) 1997-04-25 1998-04-23 Herstellungsverfahren für ein halbleiterbauelement
PCT/JP1998/001892 WO1998049724A1 (fr) 1997-04-25 1998-04-23 Procede de fabrication de dispositif a semi-conducteurs
KR10-1998-0710275A KR100399492B1 (ko) 1997-04-25 1998-04-23 실리콘층상에배선또는전극을가지는반도체장치및그배선또는전극의형성방법
US09/202,714 US6562699B1 (en) 1997-04-25 1998-04-23 Process for manufacturing semiconductor device
US10/394,024 US7135386B2 (en) 1997-04-25 2003-03-24 Process for fabricating a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10867197A JP4101901B2 (ja) 1997-04-25 1997-04-25 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JPH10303145A JPH10303145A (ja) 1998-11-13
JPH10303145A5 JPH10303145A5 (https=) 2005-03-17
JP4101901B2 true JP4101901B2 (ja) 2008-06-18

Family

ID=14490735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10867197A Expired - Fee Related JP4101901B2 (ja) 1997-04-25 1997-04-25 半導体装置の製造方法

Country Status (6)

Country Link
US (2) US6562699B1 (https=)
EP (1) EP0928021B1 (https=)
JP (1) JP4101901B2 (https=)
KR (1) KR100399492B1 (https=)
DE (1) DE69837909T2 (https=)
WO (1) WO1998049724A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4101901B2 (ja) * 1997-04-25 2008-06-18 シャープ株式会社 半導体装置の製造方法
GB2360292B (en) * 2000-03-15 2002-04-03 Murata Manufacturing Co Photosensitive thick film composition and electronic device using the same
US7721491B2 (en) * 2004-07-23 2010-05-25 Jennifer Appel Method and system for storing water inside buildings
US20060057853A1 (en) * 2004-09-15 2006-03-16 Manoj Mehrotra Thermal oxidation for improved silicide formation
TW200816312A (en) * 2006-09-28 2008-04-01 Promos Technologies Inc Method for forming silicide layer on a silicon surface and its use
JP5076557B2 (ja) * 2007-03-06 2012-11-21 富士通セミコンダクター株式会社 半導体装置の製造方法
US10446662B2 (en) * 2016-10-07 2019-10-15 Taiwan Semiconductor Manufacturing Co., Ltd. Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode
US10510851B2 (en) * 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Low resistance contact method and structure

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3095564B2 (ja) * 1992-05-29 2000-10-03 株式会社東芝 半導体装置及び半導体装置の製造方法
US3601666A (en) * 1969-08-21 1971-08-24 Texas Instruments Inc Titanium tungsten-gold contacts for semiconductor devices
US4629611A (en) * 1985-04-29 1986-12-16 International Business Machines Corporation Gas purifier for rare-gas fluoride lasers
JPS61258434A (ja) 1985-05-13 1986-11-15 Nec Corp 半導体装置の製造方法
JPH0682641B2 (ja) 1985-10-21 1994-10-19 日本電気株式会社 半導体集積回路装置の製造方法
US4690730A (en) * 1986-03-07 1987-09-01 Texas Instruments Incorporated Oxide-capped titanium silicide formation
US4981550A (en) * 1987-09-25 1991-01-01 At&T Bell Laboratories Semiconductor device having tungsten plugs
US4851358A (en) * 1988-02-11 1989-07-25 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing
US4981816A (en) * 1988-10-27 1991-01-01 General Electric Company MO/TI Contact to silicon
US5084417A (en) * 1989-01-06 1992-01-28 International Business Machines Corporation Method for selective deposition of refractory metals on silicon substrates and device formed thereby
JP2660359B2 (ja) * 1991-01-30 1997-10-08 三菱電機株式会社 半導体装置
KR970009867B1 (ko) * 1993-12-17 1997-06-18 현대전자산업 주식회사 반도체 소자의 텅스텐 실리사이드 형성방법
JPH08115890A (ja) 1994-10-17 1996-05-07 Fujitsu Ltd 半導体基板上への電極形成方法
JP2630290B2 (ja) * 1995-01-30 1997-07-16 日本電気株式会社 半導体装置の製造方法
JPH08213343A (ja) * 1995-01-31 1996-08-20 Sony Corp 半導体装置およびその製造方法
JPH08250463A (ja) 1995-03-07 1996-09-27 Nippon Steel Corp 半導体装置の製造方法
US5972790A (en) * 1995-06-09 1999-10-26 Tokyo Electron Limited Method for forming salicides
US5595784A (en) * 1995-08-01 1997-01-21 Kaim; Robert Titanium nitride and multilayers formed by chemical vapor deposition of titanium halides
US5830802A (en) * 1995-08-31 1998-11-03 Motorola Inc. Process for reducing halogen concentration in a material layer during semiconductor device fabrication
EP0793271A3 (en) * 1996-02-22 1998-12-02 Matsushita Electric Industrial Co., Ltd. Semiconductor device having a metal silicide film and method of fabricating the same
JPH09320990A (ja) * 1996-03-25 1997-12-12 Sharp Corp 半導体装置の製造方法
US5963828A (en) * 1996-12-23 1999-10-05 Lsi Logic Corporation Method for tungsten nucleation from WF6 using titanium as a reducing agent
JP4101901B2 (ja) * 1997-04-25 2008-06-18 シャープ株式会社 半導体装置の製造方法
KR19990041688A (ko) * 1997-11-24 1999-06-15 김규현 티타늄 샐리사이드 형성 방법

Also Published As

Publication number Publication date
EP0928021B1 (en) 2007-06-13
EP0928021A1 (en) 1999-07-07
EP0928021A4 (en) 2000-12-06
US7135386B2 (en) 2006-11-14
DE69837909D1 (de) 2007-07-26
KR20000016675A (ko) 2000-03-25
DE69837909T2 (de) 2008-02-14
KR100399492B1 (ko) 2003-12-24
US20030170967A1 (en) 2003-09-11
JPH10303145A (ja) 1998-11-13
US6562699B1 (en) 2003-05-13
WO1998049724A1 (fr) 1998-11-05

Similar Documents

Publication Publication Date Title
US6562718B1 (en) Process for forming fully silicided gates
KR100530401B1 (ko) 저저항 게이트 전극을 구비하는 반도체 장치
JP2008022027A (ja) 半導体装置のセルフアラインシリサイドの形成方法
JP2006516174A (ja) 半導体プロセスにシリサイドコンタクトを使用する方法
JPH0923003A (ja) 半導体装置、その製造方法、及びその製造装置
KR100396692B1 (ko) 반도체 소자의 제조방법
CN100524631C (zh) 具有硅化区的半导体器件的制造方法
JP4101901B2 (ja) 半導体装置の製造方法
US7344978B2 (en) Fabrication method of semiconductor device
JP3295931B2 (ja) 半導体装置の製造方法
JPH1154455A (ja) 半導体装置の製造方法
JP3129867B2 (ja) 半導体装置の製造方法
US6559018B1 (en) Silicon implant in a salicided cobalt layer to reduce cobalt-silicon agglomeration
KR100628225B1 (ko) 반도체 소자의 제조방법
JP2833530B2 (ja) 半導体装置の製造方法
JPH0611074B2 (ja) 半導体装置の製造方法
JP2004228351A (ja) 半導体装置及びその製造方法
JP3287621B2 (ja) 半導体装置の製造方法
KR100462667B1 (ko) 반도체장치 및 그의 제조방법
JP3094914B2 (ja) 半導体装置の製造方法
JP3639745B2 (ja) 半導体装置の製造方法
JPH10294459A (ja) 半導体装置の製造方法
JP2001203346A (ja) 半導体装置の製造方法
JPH05291181A (ja) 半導体装置の製造方法
TW531795B (en) Self-aligned metal silicide process using cobalt silicide

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040416

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040416

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20040416

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071225

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080221

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080318

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080321

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110328

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120328

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120328

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130328

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees