CN100524631C - 具有硅化区的半导体器件的制造方法 - Google Patents
具有硅化区的半导体器件的制造方法 Download PDFInfo
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- CN100524631C CN100524631C CNB2005800255118A CN200580025511A CN100524631C CN 100524631 C CN100524631 C CN 100524631C CN B2005800255118 A CNB2005800255118 A CN B2005800255118A CN 200580025511 A CN200580025511 A CN 200580025511A CN 100524631 C CN100524631 C CN 100524631C
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- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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Abstract
本发明提供了制造半导体器件的方法,以及制造包括半导体器件的集成电路的方法。所述制造半导体器件(100)的方法,除了其它步骤外,包括在衬底(110)之上形成栅结构(120)和在所述衬底(110)中紧邻着所述栅结构(120)形成源/漏区(190)。该方法进一步包括对所述栅结构(120)和衬底(110)进行干蚀刻工艺处理,以及在对所述栅结构(120)和衬底(110)进行干蚀刻工艺之后,在所述源/漏区中放置氟,以形成氟化源/漏极。此后,所述方法包括在所述栅结构(120)和所述氟化源/漏极中形成金属硅化物区(510、520)。
Description
技术领域
[0001]本发明涉及具有硅化栅电极层区和硅化源/漏区的半导体器件的制造方法,以及涉及包含所述半导体器件的集成电路的制造方法。
背景技术
[0002]常规的金属氧化物半导体(MOS)晶体管经常使用金属硅化物层来降低电阻。自对准硅化(silicidation)工艺(自对准硅化物(salicide))经常被用于在MOS晶体管的栅电极和源/漏区上形成硅化钛、硅化钴和硅化钨区。在该工艺中,覆盖金属膜被沉积在含有MOS晶体管结构的硅衬底上。然后,金属与下面的硅区反应,形成低电阻的金属硅化物。随后,采用对于残留的金属硅化物具有选择性的金属蚀刻工艺来除去残留在衬底上的任何未反应的金属。
[0003]在该工艺期间,关键的是将金属硅化物限制在源/漏区和栅区。在源/漏区的情况下,如果金属硅化物形成在晶体管侧壁结构之下,晶体管就可能变得不能工作。而且金属硅化物层应该与下面的源/漏区形成相对平整或光滑的界面。在金属硅化物源/漏界面中的任何不平将导致漏电流增大和击穿电压降低。
[0004]为了降低与金属硅化物区关联的电阻,在形成MOS晶体管中的金属硅化物区时越来越多地使用镍,尤其是对于物理栅长(gatelength)小于40nm的晶体管和/或具有超浅结(ultra-shallow junction)的MOS晶体管。镍在硅中具有非常高的扩散性,导致形成在晶体管侧壁结构之下延伸的硅化镍区。此外,使用已有的方法形成的硅化镍区与下面的P-型源/漏区具有非常粗糙的界面。如上所述,这导致晶体管具有较高的漏电流和降低的击穿电压。
[0005]因此,需要这样一种方法,该方法在MOS晶体管的栅电极和源/漏区上形成金属硅化物区,其与下面的源/漏区具有光滑界面,而且不在晶体管侧壁结构之下延伸。
发明内容
[0006]为了解决现有技术的上述缺陷,本发明提供了制造半导体器件的方法和制造包括所述半导体器件的集成电路的方法。除了其它步骤以外,所述制造半导体器件的方法包括在衬底之上形成栅结构,以及在衬底中邻近栅结构处形成源/漏区。该方法进一步包括使栅结构和衬底经历干蚀刻工艺,以及在栅结构和衬底经历干蚀刻工艺之后在源/漏区中放置氟,以形成氟化源/漏极。之后,所述方法包括在栅结构和氟化源/漏极中形成金属硅化物区。
[0007]除了上面讨论的步骤以外,制造所述集成电路的方法包括以下步骤:在位于衬底之上的介电层或绝缘层内形成互连,用于电接触半导体器件的步骤。此外,该方法包括在栅结构之上形成高性能电容器,其中在栅结构中形成的金属硅化物区被用作高性能电容器的底电极。
[0008]前述内容已概述了本发明优选的和可替换的特征,所以本领域的技术人员可以更好地理解以下的本发明的详细描述。本发明的附加特征将在下文中被描述,其形成本发明权利要求的主题。本领域的技术人员应该理解,他们可以容易地将所公开的概念和具体的实施例用作基础,用于设计和修改实现本发明相同目的的其它结构。本领域的技术人员也应认识到这样的等同构造不脱离本发明的范围。
附图说明
[0009]参考附图,对本发明的实施例进行描述,其中:
图1说明了根据本发明的原理制造的部分完成的半导体器件的横截面视图;
图2说明了在使栅结构和衬底经历干蚀刻工艺之后的图1所示部分完成的半导体器件的横截面视图;
图3说明了在源/漏区中放置氟以形成氟化源/漏极之后的图2所示部分完成的半导体器件的横截面视图;
图4说明了在栅电极层和源/漏区之上形成金属层之后的图3所示部分完成的半导体器件的横截面视图;
图5说明了在使金属层经历退火并因此导致金属层与下面的硅层反应而形成金属硅化物区之后的图4所示部分完成的半导体器件的横截面视图;
图6说明了并入根据本发明的原理构造的半导体器件的常规集成电路(IC)的截面图;和
图7说明了图6所示的IC的横截面视图,其包括位于至少一个半导体器件上的电容器。
具体实施方式
[0010]由于物理栅长在金属氧化物半导体(MOS)器件,尤其是那些40nm级以下的器件中连续缩短,因此必须克服某些障碍以连续使用镍作为与常规源/漏区接触的金属硅化物。这些障碍中的一个是在半导体器件的侧壁间隔物之下延伸的管道缺陷,其被认为是镍在硅中的相对容易扩散的函数。这些障碍的另一个是在p型掺杂的源/漏区上形成二硅化镍(NiSi2)刺突(spike),其被认为是部分由于p型掺杂硅上NiSi2的部位造成的。
[0011]对于这些障碍,本发明已经认识到对形成硅化镍的硅区域应用氟处理将最终大大减少管道缺陷并且有效消除二硅化镍(NiSi2)刺突的形成。遗憾的是,紧接在硅化镍区形成之前的常规干蚀刻预处理不能被执行,因为其将降低氟处理的效果。然而,如果不进行常规干蚀刻预处理,对于窄的多晶硅栅电极线会造成实质较高的薄层电阻。
[0012]因此,本发明独特地认识到在氟处理之前,可以在衬底的表面上以及栅结构上进行干蚀刻预处理。采用该工艺流程,根据本发明的原理制造的半导体器件就会获得与干蚀刻预处理和氟处理两者关联的益处。因此,使用发明的方法既能够既减少管道缺陷又有效消除二硅化镍刺突,同时对窄多晶硅栅电极线保持良好的薄层电阻。
[0013]现在转到图1-5,其说明了详细的制造步骤的横截面视图,所述制造步骤教导了在有利的实施例中如何根据本发明的原理制造半导体器件。图1中的部分完成的半导体器件100包括衬底110。在一个示例性的实施例中,衬底110可以是位于部分完成的半导体器件100中的任何层,包括晶片本身或位于晶片上面的层(例如,外延层)。
[0014]如图1所示,栅结构120形成在衬底110之上。在所示的实施例中,栅结构120包括栅介电层123以及栅电极层128。栅介电层123可以包括例如氧化物、热生长SiO2、氮化物、氧氮化物或其任意组合,并且优选具有约1nm到约20nm的厚度范围。使用介电常数大于约3.9的高K介电材料,也可以形成栅介电层123。高K介电材料的一些例子包括含铪电介质,例如氧化铪、氧氮化铪等。
[0015]如前所示,栅结构120还包括栅电极层128。一个有利的实施例中的栅电极层128包括形成于栅介电层123上的含硅材料层。优选地,这种含硅材料包括多晶硅(polycrystalline silicon),但其可以包括非晶硅、外延硅或任何其它合适的半导体材料。
[0016]位于衬底110内以及隔离区130之间的是阱区140。图1-5所示的衬底110中的阱区140可以是n型或p型的。在形成CMOS集成电路时,n型和p型阱区140形成在衬底110中。在p型阱区的情况下,将形成NMOS晶体管。对于n阱区,将以相似的方式形成PMOS晶体管。
[0017]有了采用标准的光刻法工艺和多晶硅蚀刻确定的栅结构120,例如,首先通过热生长约1nm到约5nm的氧化物,随后通过沉积约15nm的TEOS氧化物来形成间隔物150。在其它的实施例中,间隔物150可以包括氮化硅和/或氧化硅(生长或沉积的)层的组合。
[0018]对于阱区140包括p型阱一部分的NMOS晶体管,执行覆盖n型轻掺杂注入(blanket n-type lightly doped implant),导致产生轻掺杂n型延伸或扩展注入物(extension implant)160。n型轻掺杂扩展注入物160通常是指轻掺杂漏(LDD)或中掺杂漏(MDD)扩展区。n型轻掺杂扩展注入物160是常规地形成的,并且通常具有从约1E19原子/cm3到2E20原子/cm3的范围内的峰值掺杂浓度。
[0019]除了n型轻掺杂扩展注入物160以外,有时执行袋型注入(pocket implant)(未示出)。对于图1所示的半导体器件100是NMOS晶体管的情况,袋型注入物将包括p型掺杂物种类。在目前的集成电路技术中,袋型注入是指用于降低短的晶体管栅长对晶体管性质(例如阀电压)的影响的注入。然而,袋型注入的影响不限于阀电压。用于特定晶体管类型的袋型注入通常导致延伸超过晶体管的漏扩展区的掺杂分布(doping profile)。p型袋型注入物的种类可以由B、BF2、Ga、In或任何其它合适的p型掺杂物组成。轻掺杂扩展注入物160的种类可以由As、P、Sb或任何其它合适的n型掺杂物组成。注入的次序是有点任意的,并且轻掺杂扩展注入物160可以在袋型注入之前完成。
[0020]类似地,对于阱区140包括n型阱一部分的PMOS晶体管,执行覆盖p型轻掺杂注入,导致产生p型轻掺杂扩展注入物160。p型轻掺杂扩展注入物160也是以常规方式形成的,也通常具有范围从约1E19原子/cm3到2E20原子/cm3的峰值掺杂浓度。类似于NMOS晶体管,对于PMOS晶体管,除了p型轻掺杂扩展注入物160以外,有时也进行袋型注入。然而,在这种情况下,袋型注入物包括n型掺杂物种类。n型袋型注入物的种类可以由As、p或任何其它合适的n型掺杂物组成。p型轻掺杂扩展注入物160的种类可以由硼或任意其它合适的p型掺杂物组成。正如已陈述的,注入的次序是有点任意的,并且可以在p型轻掺杂扩展注入物160之前或之后进行袋型注入。
[0021]在完成轻掺杂扩展注入物160(以及袋型注入,如果执行的话),以及任何后续的处理之后,就形成侧壁结构170,如图1所示。在本发明的实施例中,侧壁结构170包括多个氧化硅和氮化硅介电层。侧壁结170通过首先沉积合适介电材料的覆盖层而形成。然后,利用各向异性蚀刻来形成侧壁结构170。采用单种合适的介电材料例如氮化硅或氧化硅,也可以形成侧壁结构170。
[0022]在侧壁结构170形成之后,形成重掺杂或高掺杂源/漏注入物180。对于NMOS晶体管,诸如砷和/或磷这样的n型掺杂物被注入到与侧壁结构170邻近的衬底110中,以形成重掺杂源/漏注入物180。对于PMOS晶体管,诸如硼这样的p型掺杂物被注入到与侧壁结构170邻近的衬底110中,以形成重掺杂源/漏注入物180。重掺杂源/漏注入物180是以常规方式形成的,并且通常具有范围从约1E18原子/cm3到1E21原子/cm3的峰值掺杂浓度。
[0023]在重掺杂源/漏注入物180形成之后,可以进行高温源/漏退火,以活化所注入的掺杂物并去除在离子注入工艺期间对衬底110产生的损伤。所得到的是源/漏区190。源/漏退火可以包括快速热退火(RTA)工艺,其中源/漏区190在800℃以上的温度被退火1秒到数分钟的时间。
[0024]现在转到图2,其说明了图1所示部分完成的半导体器件在栅结构120和衬底110经历干蚀刻工艺210之后的横截面视图。在一个示例性的实施例中,干蚀刻工艺210包括氩等离子溅射蚀刻或溅镀蚀刻。在该实施例中,氩气流会理想地处于从约15sccm到约100sccm的范围。此外,等离子体室压力将有利地在约0.1毫托到约50毫托的范围,并且功率水平将在约50瓦特到约100瓦特的范围。此外,约150瓦特到约450瓦特的RF功率可以被施加于晶片,用于偏压。但其它气体、流速、压力和功率水平也可以被使用。
[0025]在一个替代性实施例中,干蚀刻工艺210包括氧化物干蚀刻(oxide dry etch)工艺。氧化物干蚀刻工艺可以是任何类型的氧化物干蚀刻,然而,在本发明的一个示例性实施例中,氧化物干蚀刻与用于制造半导体器件的常规盖氧化物蚀刻(cap oxide etch)相类似。这个盖氧化物蚀刻通常使用含C和F的气体等离子体。在一个示例性的实施例中,使用了CF4/CHF3/Ar等离子体。这样的工艺可以包括在等离子体室中在约35毫托到约100毫托的范围的压力下、在约100瓦特到约300瓦特范围的功率水平下,以约2sccm到约10sccm流动的CF4、以约5sccm到约25sccm流动的CHF3和以约50sccm到约100sccm流动的Ar。
[0026]如果使用盖氧化物蚀刻,则可以进行可选的氧灰化和湿清洗(oxygen ash and wet clean)。在一个实施例中,湿清洗可以是大范围热SC1清洗(例如,过氧化氢、氢氧化铵和DI水)。大范围热SC1清洗可以在约50℃到约90℃的温度范围内进行一段时间,该段时间范围为从约2分钟到约15分钟。其它的灰化和清洗仍然在本发明的范围之内。
[0027]现在转到图3,其说明了图2所示的部分完成的半导体器件在源/漏区190中放置氟310以形成氟化源/漏极320之后的横截面视图。应该注意的是,氟化源/漏极320在所有源/漏退火工艺已经完成之后形成。氟化源/漏极320位于衬底110表面附近,具有大约0.5nm到约30nm的示例性深度,并且氟浓度范围为约1E17原子/cm3到约5E21原子/cm3。
[0028]在一个实施例中,通过将源/漏区190暴露于含氟的等离子体而形成氟化源/漏极320。这样的工艺可以包括在等离子体室中在范围为约50毫托到约100毫托的压力下以及范围为约75瓦特到约200瓦特的功率水平下,使NF3在约0.2sccm到约20sccm流动、使N2在约0sccm到约100sccm流动、使H2在约0sccm到约100sccm流动和/或使Ar在约0sccm到约100sccm流动。能够在等离子区中使用以形成含氟区的其它气体包括但不限于NF3/H2、NF3/NH3、NF3/N2、NF3/Ar、NF3/N2/H2、CF4/H2/Ar、C2F6/Ar和C2F6/H2。
[0029]应该将本发明的含氟等离子体工艺与用于蚀刻氧化物和/或进行其它类型的表面处理的其它含氟等离子体区分开来。这些工艺被优化,不会将氟加入到下面的硅区,并且事实上,这些工艺被优化成不留下任何含氟的残留物。在本发明之前,氟限制金属硅化物区形成的能力是未知的,并且使用等离子体形成氟的近表面区和在半导体领域中目前使用含氟等离子体是直观相反的。
[0030]在本发明的另一个实施例中,通过以约0.2KeV到约5KeV范围的能量和以约1E10原子/cm2到约1E16原子/cm2范围的剂量,将氟和/或含氟物质离子注入到源/漏区190中,能够形成氟化源/漏极320。本领域技术人员将理解,在氟等离子体工艺和氟注入工艺之间选择要求对被制造的具体器件进行分析。
[0031]在源/漏区190中形成氟化源/漏极320的过程期间,也可以在栅电极层128中形成氟化栅电极区330。栅电极层128中的氟化栅电极区330将理想地有助于随后形成硅化镍层,所述硅化镍层形成在栅电极层128中。在那些在栅电极层128中不需要氟化栅电极区330的实例中,能够使用阻挡层或屏蔽物,以在氟掺入工艺期间屏蔽栅电极层128。
[0032]现在转向图4,其说明了图3所示的部分完成的半导体器件在金属层410形成在栅电极层128和源/漏区190之上后的横截面视图。在本发明的一个实施例中,金属层包括镍。除了镍以外,其它金属包括钴、钼、铂等。对于镍被用于形成金属层410的情况,金属层410的厚度最好在约3nm和约40nm之间。可选的盖层(未示出)例如TiN可以被用于阻止周围气体的潜在负面影响。
[0033]现在转向图5,其说明了图4所示的部分完成的半导体器件在金属层410经过退火,并因此导致金属层410与下面的硅层反应而形成金属硅化物区510、520之后的横截面视图。应该注意的是,在金属层410和侧壁结构170之间未发生反应。在金属硅化物区510、520形成之后,未反应的金属被用化学方法去除,得到类似于图5所示的器件。
[0034]在镍被用于形成金属层410的情况下,通过在约250℃到约550℃范围的温度下退火镍金属层410,形成了单硅化镍(NiSi)510、520。在该实施例中,在硅化物形成过程期间,氟化源/漏极320如果不是全部被消耗,将至少部分被消耗。此外,在金属硅化物区510和源/漏区190的界面上通常将有氟堆积。在本发明的工艺之后,在金属硅化物区510和下面的源/漏区190之间的界面上测量的氟浓度将有利地在约1E17原子/cm3到5E21原子/cm3的范围之内。在源/漏区190中的金属硅化物区510形成期间,金属硅化物区520也可以在栅电极层128中同时形成。
[0035]在一些实例中,可以在具有单群集工具(single clustertool)的多个室中或者在单室中现场进行栅结构120和衬底110的干蚀刻工艺、氟化源/漏极320的形成以及随后的金属层410的形成。这样的群集工具可以通过Applied Materials公司购买,该公司地址为3050Avenue,Santa Clara,California 95054,商品名为Endura Mainframe。应该注意的是,等离子溅射蚀刻是对于该实施例最适合的干蚀刻。还应该注意的是,在该实施例中,不需要进行本文公开的可选清洗步骤。
[0036]在那些非现场(ex-situ)完成多种工艺步骤的实例中,在氟处理之后和在衬底110上形成金属层410和栅结构120之前,需要第二个可选的清洗步骤。此第二个可选的清洗步骤,除了其它操作,可以包括用SC1和氢氟酸清洗表面。该第二个清洗步骤被认为还钝化了衬底110,防止空气氧化。
[0037]上述的金属硅化物形成工艺可以被用于NMOS和PMOS晶体管。在NMOS晶体管的情况下,上述工艺使侧壁结构下延伸至沟道区的金属硅化物区的形成最少,并且得到金属硅化物区510到源/漏区190的光滑界面。在PMOS晶体管的情况下,上述工艺使金属硅化物区510到源/漏区190界面的不平最少,并且导致降低的漏电流和升高的击穿电压。
[0038]现在转向图6,其说明了装有根据本发明的原理构造的半导体器件610的常规集成电路(IC)600的截面图。IC 600可以包括器件,例如用于形成CMOS器件的晶体管、BiCMOS器件、双极器件或其它类型的器件。IC 600可进一步包括无源器件,例如电感器或电阻器,或者还可以包括光学器件或光电器件。本领域的技术人员熟知这些各种类型的器件及其制造。在图6所示的具体实施例中,IC 600包括其上设置有介电层620的半导体器件610。此外,互连结构630位于介电体层620中,以使各种器件互连,因此形成可工作的集成电路600。
[0039]最后参考图7,其说明了图6所示的IC 600的横截面视图;然而,图7的IC包括位于半导体器件610中的至少一个上的电容器710。在图7所示的具体实施例中,NiSi形成于多晶硅栅电极上,并且被用作高性能电容器710的底电极。然后,介电层(例如SiO2)被沉积在NiSi底电极之上,随后第二电极诸如TiN被沉积。然后,电容器叠(capacitor stack)被图案化,以形成所需的电容器710。
[0040]尽管已经具体描述了本发明,但是本领域的技术人员应该明白,他们可以进行多种变化、替代和改变而不脱离本发明最广形式的精神。
Claims (19)
1.一种制造半导体器件的方法,包括:
在衬底之上形成栅结构;
在所述衬底中邻近所述栅结构处形成源/漏区;
在形成源/漏区之后,使所述栅结构和衬底经历干蚀刻工艺;
在所述栅结构和衬底经历所述干蚀刻工艺之后,在所述源/漏区中放置氟,以形成氟化源/漏极;和
在所述栅结构中和所述氟化源/漏极中形成金属硅化物区,其中形成金属硅化物区包括在所述栅结构和所述氟化源/漏极之上形成金属层,以及使所述金属层与所述栅结构和所述氟化源/漏极反应,以在所述栅结构和所述氟化源/漏极中形成所述金属硅化物区。
2.如权利要求1所述的方法,其中使所述栅结构和衬底经历干蚀刻工艺包括使所述栅结构和衬底经历氩等离子溅射蚀刻。
3.如权利要求1所述的方法,其中使所述栅结构和衬底经历干蚀刻工艺包括使所述栅结构和衬底经历氧化物干蚀刻工艺,随后经历氧灰化和湿清洗。
4.如权利要求1所述的方法,其中通过将所述源/漏区暴露于含氟等离子体而形成所述氟化源/漏极,所述含氟等离子体包括在等离子体室中在50毫托到100毫托的压力下、以及在75瓦特到200瓦特的功率水平下,以0.2sccm到20sccm流动的NF3、以0sccm到100sccm流动的N2和以0sccm到100sccm流动的H2。
5.如权利要求1所述的方法,其中通过以0.2KeV到5KeV的能量和1E10原子/cm2到1E16原子/cm2的剂量将氟或含氟的物质离子注入到所述源/漏区,形成所述氟化源/漏极。
6.如权利要求1所述的方法,进一步包括在所述源/漏区中形成氟化源/漏极之后并在所述氟化源/漏极中形成金属硅化物区之前清洗所述衬底的表面。
7.如权利要求1所述的方法,其中使所述栅结构和衬底经历干蚀刻工艺、在所述源/漏区中形成氟化源/漏极以及在所述栅结构和所述氟化源/漏极中形成金属硅化物区在相同的处理设备中进行。
8.如权利要求1所述的方法,其中所述金属硅化物区是硅化镍区。
9.如权利要求1所述的方法,其中所述栅结构包括多晶硅栅电极层,并且其中在所述栅结构中形成金属硅化物区包括在所述多晶硅栅电极层中形成金属硅化物区。
10.一种制造集成电路的方法,该方法包括:
在衬底之上制造半导体器件,包括:
在衬底之上形成栅结构;
在所述衬底中邻近所述栅结构处形成源/漏区;
在形成源/漏区之后,使所述栅结构和衬底经历干蚀刻工艺;
在所述栅结构和衬底经历所述干蚀刻工艺之后,在所述源/漏区中放置氟,以形成氟化源/漏极;和
在所述栅结构和所述氟化源/漏极上形成金属硅化物区,其中形成金属硅化物区包括在所述栅结构和所述氟化源/漏极之上形成金属层,以及使所述金属层与所述栅结构和所述氟化源/漏极反应,以在所述栅结构和所述氟化源/漏极中形成所述金属硅化物区;以及
在位于所述衬底之上的介电层中形成互连,用于电接触所述半导体器件。
11.如权利要求10所述的方法,其中使所述栅结构和衬底经历干蚀刻工艺包括使所述栅结构和衬底经历氩等离子溅射蚀刻。
12.如权利要求10所述的方法,其中使所述栅结构和衬底经历干蚀刻工艺包括使所述栅结构和衬底经历氧化物干蚀刻工艺,随后经历氧灰化和湿清洗。
13.如权利要求10所述的方法,其中通过将所述源/漏区暴露于含氟等离子体而形成所述氟化源/漏极,所述含氟等离子体包括在等离子体室中在50毫托到100毫托的压力下、以及在75瓦特到200瓦特的功率水平下,以0.2sccm到20sccm流动的NF3、以0sccm到100sccm流动的N2和以0sccm到100sccm流动的H2。
14.如权利要求10所述的方法,其中通过以0.2KeV到5KeV的能量和1E10原子/cm2到1E16原子/cm2的剂量将氟或含氟的物质离子注入到所述源/漏区,形成所述氟化源/漏极。
15.如权利要求10所述的方法,进一步包括在所述源/漏区中形成氟化源/漏极之后并在所述氟化源/漏极中形成金属硅化物区之前清洗所述衬底的表面。
16.如权利要求10所述的方法,其中使所述栅结构和衬底经历干蚀刻工艺、在所述源/漏区中形成氟化源/漏极以及在所述栅结构和所述氟化源/漏极中形成金属硅化物区在相同的处理设备中进行。
17.如权利要求10所述的方法,其中所述金属硅化物区是硅化镍区。
18.如权利要求10所述的方法,其中所述栅结构包括多晶硅栅电极层,并且其中在所述栅结构中形成金属硅化物区包括在所述多晶硅栅电极层中形成金属硅化物区。
19.如权利要求10所述的方法,进一步包括在所述栅结构中形成高性能电容器,其中在所述栅结构之上形成的所述金属硅化物区被用作所述高性能电容器的底电极。
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US10/901,756 US7422968B2 (en) | 2004-07-29 | 2004-07-29 | Method for manufacturing a semiconductor device having silicided regions |
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US20060024882A1 (en) | 2006-02-02 |
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KR100918881B1 (ko) | 2009-09-23 |
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