JP4093818B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4093818B2
JP4093818B2 JP2002230409A JP2002230409A JP4093818B2 JP 4093818 B2 JP4093818 B2 JP 4093818B2 JP 2002230409 A JP2002230409 A JP 2002230409A JP 2002230409 A JP2002230409 A JP 2002230409A JP 4093818 B2 JP4093818 B2 JP 4093818B2
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Japan
Prior art keywords
groove
die pad
semiconductor element
conductive foil
insulating resin
Prior art date
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Expired - Fee Related
Application number
JP2002230409A
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English (en)
Japanese (ja)
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JP2004071898A (ja
Inventor
幸嗣 高橋
則明 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2002230409A priority Critical patent/JP4093818B2/ja
Priority to TW092118684A priority patent/TWI240603B/zh
Priority to KR1020030053069A priority patent/KR20040026129A/ko
Priority to CNB031526179A priority patent/CN100492632C/zh
Publication of JP2004071898A publication Critical patent/JP2004071898A/ja
Application granted granted Critical
Publication of JP4093818B2 publication Critical patent/JP4093818B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
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    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/732Location after the connecting process
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
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    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)
JP2002230409A 2002-08-07 2002-08-07 半導体装置の製造方法 Expired - Fee Related JP4093818B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2002230409A JP4093818B2 (ja) 2002-08-07 2002-08-07 半導体装置の製造方法
TW092118684A TWI240603B (en) 2002-08-07 2003-07-09 Manufacturing method of circuit device
KR1020030053069A KR20040026129A (ko) 2002-08-07 2003-07-31 회로 장치 및 그 제조 방법
CNB031526179A CN100492632C (zh) 2002-08-07 2003-08-01 电路装置及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002230409A JP4093818B2 (ja) 2002-08-07 2002-08-07 半導体装置の製造方法

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JP2004071898A JP2004071898A (ja) 2004-03-04
JP4093818B2 true JP4093818B2 (ja) 2008-06-04

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JP2002230409A Expired - Fee Related JP4093818B2 (ja) 2002-08-07 2002-08-07 半導体装置の製造方法

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JP (1) JP4093818B2 (zh)
KR (1) KR20040026129A (zh)
CN (1) CN100492632C (zh)
TW (1) TWI240603B (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100782225B1 (ko) * 2005-09-02 2007-12-05 엘에스전선 주식회사 함몰부가 형성된 다이패드를 구비한 리드프레임 및반도체 패키지
KR100672214B1 (ko) * 2005-12-30 2007-01-22 김대성 스텝머신기능을 구비한 자전거
US7836586B2 (en) * 2008-08-21 2010-11-23 National Semiconductor Corporation Thin foil semiconductor package
JP2010050491A (ja) * 2009-12-02 2010-03-04 Renesas Technology Corp 半導体装置の製造方法
CN105185752B (zh) * 2010-05-12 2019-03-19 瑞萨电子株式会社 半导体器件及其制造方法
US8390119B2 (en) 2010-08-06 2013-03-05 Mediatek Inc. Flip chip package utilizing trace bump trace interconnection
JP5533619B2 (ja) * 2010-12-14 2014-06-25 株式会社デンソー 半導体装置
US9385102B2 (en) 2012-09-28 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
JP2014203861A (ja) * 2013-04-02 2014-10-27 三菱電機株式会社 半導体装置および半導体モジュール
CN103716993A (zh) * 2014-01-07 2014-04-09 上海铁路通信有限公司 一种带垒坝保护层的印刷电路板
JP5939474B2 (ja) * 2014-07-02 2016-06-22 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
JP6430843B2 (ja) * 2015-01-30 2018-11-28 株式会社ジェイデバイス 半導体装置
JP6537866B2 (ja) * 2015-03-30 2019-07-03 株式会社フジクラ 半導体パッケージおよび圧力センサパッケージ
JP6500562B2 (ja) * 2015-03-31 2019-04-17 アイシン・エィ・ダブリュ株式会社 半導体モジュール
CN104779224B (zh) * 2015-04-15 2017-07-28 苏州聚达晟芯微电子有限公司 一种功率器件的qfn封装结构
JP6678506B2 (ja) 2016-04-28 2020-04-08 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及び半導体パッケージの製造方法
WO2018159464A1 (ja) 2017-03-03 2018-09-07 株式会社村田製作所 回路基板
JP6907671B2 (ja) * 2017-04-17 2021-07-21 富士電機株式会社 半導体装置
DE102017123278A1 (de) 2017-10-06 2019-04-11 Schott Ag Grundkörper mit angelötetem Massestift, Verfahren zu seiner Herstellung und seine Verwendungen
FR3094564A1 (fr) * 2019-03-28 2020-10-02 Stmicroelectronics (Grenoble 2) Sas Refroidissement de circuits électroniques
JP7235379B2 (ja) 2019-06-19 2023-03-08 住友電工デバイス・イノベーション株式会社 電子デバイスの製造方法
JP6753498B1 (ja) * 2019-09-19 2020-09-09 株式会社明電舎 エミッタ支持構造及び電界放射装置
CN113594051B (zh) * 2021-07-09 2024-02-20 苏州汉天下电子有限公司 半导体封装方法
CN117529804A (zh) * 2021-09-07 2024-02-06 华为技术有限公司 芯片封装结构和用于制备芯片封装结构的方法
CN114300423A (zh) * 2021-12-21 2022-04-08 中国电子科技集团公司第五十八研究所 一种防粘接材料扩散的封装结构及其制备方法
CN114975342A (zh) * 2022-04-18 2022-08-30 华为数字能源技术有限公司 一种功率模块及车载功率电路

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JPS5596666A (en) * 1979-01-18 1980-07-23 Mitsubishi Electric Corp Method of fabricating semiconductor device substrate
JPH0637122A (ja) * 1992-07-15 1994-02-10 Hitachi Ltd 半導体装置
JP3062691B1 (ja) * 1999-02-26 2000-07-12 株式会社三井ハイテック 半導体装置
JP3600131B2 (ja) * 2000-09-04 2004-12-08 三洋電機株式会社 回路装置の製造方法
JP2002110888A (ja) * 2000-09-27 2002-04-12 Rohm Co Ltd アイランド露出型半導体装置

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CN100492632C (zh) 2009-05-27
KR20040026129A (ko) 2004-03-27
TWI240603B (en) 2005-09-21
JP2004071898A (ja) 2004-03-04
TW200405779A (en) 2004-04-01
CN1501490A (zh) 2004-06-02

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