TWI240603B - Manufacturing method of circuit device - Google Patents
Manufacturing method of circuit device Download PDFInfo
- Publication number
- TWI240603B TWI240603B TW092118684A TW92118684A TWI240603B TW I240603 B TWI240603 B TW I240603B TW 092118684 A TW092118684 A TW 092118684A TW 92118684 A TW92118684 A TW 92118684A TW I240603 B TWI240603 B TW I240603B
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- aforementioned
- wafer
- circuit device
- pad
- bonding
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- H—ELECTRICITY
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Die Bonding (AREA)
Description
1240603 玖、發明說明 [發明所屬之技術領域] 本發明係關於-種可防止用以固接半導體元件之焊 材流出之電路裝置及其製造方法。 [先前技術] .以往安裝在電子機器飞冑路裝置是採用於行動電 話、攜帶式電腦等,因此力求小型化、薄型化及輕量化。 例如,以半導體裝置為例來說明電路裝置時,京尤—般的半 導體裝置而言’有以往通常以轉注成型法(transfer则⑷ 進行封裝之封裝型半導體裝置。如第η圖所示,該半導體 裝置係安裝在印刷基板ps。 且該封裝型半導體裝置61係以樹脂層63包覆半墓體 晶片62周圍,且從該樹脂層63側部導出外部連接用導線 端子64。但是,該封裝料導體裝置61因使導線端子μ 從樹脂層63露出在外面,整體尺 八丁季乂大,因此亚不能符合 :型化、薄型化及輕量化。因此,各公司為了實現小型化、 涛型化及化而競相開發各種構造,最近開發出一種稱 ==___队晶片尺寸封裝)之與晶片尺寸相 寺ΒΒ圓級CSP,或尺寸比晶片尺寸略大的CSP。 板,Γ2圖係用以表示採用破璃環氧基板…乍為支持基 見比曰日片尺寸略大之CSP66之干立m L ^ 在玻璃严-# i , 不忍圖。此處將說明 在瑗羊飞基板65上安裝有電晶體晶片丁者。 。亥破璃環氧基板6 5表面形成右… 極68及日 弟1電極67、第2電 久日日片ί干墊(dlepad)69,背面形 成有弟1背面電極70 314863 1240603 和第2背面電極71。 而使前述第1電極67 “ f過貝通孔(如,“— )ΤΗ 第2電極6δ盘第7北^ 1月面電極70作電性連接、使 ^ 一 月面電極71作電性1車;& ‘塾69固接有前述裸露的電晶 連接·。而且在晶片 72連接電晶體之射極 奴日日’且透過金屬細線 接—地々贫 電極67,透過金屬细岭72、車 “ Μ體之基極和第2電極6δ。再者,…V? 72連 丁的方式將樹脂層73执 伖现屯日日體晶片 二、. 3 S又在破璃環氧基板65上。
剛述CSP66係採用玻璃環氧基板6 不同,其從晶片丁到外邱、$ 4 仁共日日圓級CSP 之延伸構造簡單,::;=用之背面電極--為止 圖所示,前述心 廉價製造之優點。且如第11 I CSP66係安裝在印刷基板ps。 上裝設有構成電路之電極、配線,且以電性連接:固:有 :一、封裝型半導體裝置…片電=:?: 電容器CC等。然後,以該印刷基板構 二二 各種裝置中。 I路係女I在 融塗佈在晶 而固接電晶 上·日夺,會 和其他電極 但是,如上述之半導體裝置中,係藉由熔 片銲墊69上之銲錫等銲材之回流(ren〇w)步驟 體T。因而’將電晶體τ載置於已熔融之銲錫 銲錫從晶片鲜墊69上流出,而有晶片銲墊69 發生短路之問題。 錫到達第2 ,因此會導 再者,為了防止從晶片銲墊69流出之鲜 電極68,而使晶片銲墊69和第2電極68隔開 致整體裝置大型化。 [發明内容] 314863 1240603 本兔明係鏜於上述問題而研發者’纟發明之主 在於提供一接木& 聲目的 a±,=、^透過銲㈣半導^件安裝在晶片銲墊 ^方止杯材從晶片銲墊流出之電路裝置。 -丄1元t 具有··形成與透過銲“安裝 近接配置之二= '晶片銲塾;與前述晶片銲塾 的方式,二墊叫;以環繞前述半導體元件 出之溝道;以:墊:周邊部’且防止前述銲材流 而封裝二 則述晶片銲墊及前述接合墊之内面 片銲墊、前述接合墊及前述半導體元件。 之厚^淺^ W明之特徵為前述溝道形成比前述晶片銲墊 脂。 本t ^之特徵為前述溝道填充有前述絕緣性樹 本^月之知'徵為前述半導體裝置係IC晶片。 線而與二::::特徵為前述半導體元件係透過金屬細 :預期之則述導電圖案作電性連接。 二::發明之特徵為前述銲材係銲錫或銀(Ag)膠。 材。 "月之&说為使用絕緣性接著劑代替前述銲 弟8,本發明之特徵為在 圍繞之區域中再形成溝道。 $述日日片辉墊之前述溝道所 述日日片録塾之前述溝道所 〇 :準備導電薄片之步驟; 第9,本發明之特徵為在前 圍之區域是以袼子狀形成溝道 弟10,本發明之特徵為具有 314863 7 1240603 在前述導電薄片形成比 數個電路裝置部之曰/、厚度為淺的分隔溝而形成構成複 ^ 片銲墊及接合墊,同時以. 接之半導體元件之區域 、 M ¥以裱繞預定固 述分隔溝淺的溝道之+ _方式而在刚述晶片鲜塾形成比前 於前迷晶片銲墊之步驟·:過1于材而將半導體元件固接 接合塾進行打線接合(w.’/h 14半導體元件和預期之前述 包覆前述半導體元件,1e b〇ndlng)之步驟;以絕緣性樹脂 方式共同成型之步驟· ^充填於所述分隔溝及前述溝道之 述絕緣性樹脂為止之步/前,導電薄片之背面至露出前 方式而分隔成各電路& ’和错由切心述絕緣性樹脂之 吩衣置之步驟。 第11,本發明之特Μ β 淺。 破為前述溝道形成比前述晶片銲墊 :12本舍明之特徵為前述銲材 第13,本發明之特饩m 物次銀(Ag)膠。 材。 、政為使用絕緣性接著劑代替前述銲 [實施方式] (說明電路裝置10之構成的第!實施形態) 參照第1圖說明本發明之電路裝置10之 圖(A)係電路裝置1〇之俯視 ^視圖。 η圖(BH糸電路裝置10 參照第1圖(Α)及第1圖(Β),電路裝置1〇具有如下之 構成。亦即,電路裳置10係由:形成與透過薛材= 裝之半導體元件1 3大致同等大小之晶片 ,e . 心曰日片蚌墊1 1 ;與晶片 產干墊11近接設置之接合堅丨2;以環繞半導體元件13的方. 314863 8 !24〇6〇3 式形成在日日日>{銲墊11的周邊部,且防止銲材19流出之溝 ,a14,以及,使晶片銲墊11及接合墊12之背面露出而封 衣日日片鲜墊1 1、接合墊1 2及半導體元件1 3。以下說明上 述之各構成要素。
晶片銲墊11係安裝有半導體元件13之導電圖案,由 銅薄片等金屬構成,且使背面露出而埋設在絕緣性樹脂 6而且,晶片銲墊丨丨之平面大小形成地比所安裝的半導 ^元件略大,該周邊部形成有溝道14。該圖(A)中,晶片 2墊11形成在中央部,且透過銲材19而安裝有由⑴晶片 等構成之半導體元件13。而且,對應安裝有半導體元件U 之d域的晶片_ n纟面’形成有由銀(Ag)等構成之電 膜。 接合墊12係可搭接金屬細線15之導電圖案,且使背 面露出而埋設在絕緣性樹脂16。在此處,以環繞形成在裝 置中央部之晶片銲墊丨丨的方式形成有多數個圓狀接合墊 U。於該圖(A)中,形成在晶片銲墊n左右兩側之接合墊 1 2 A疋以電性獨立的方式設置。而且,形成在晶片銲墊1 1 上下兩側之接合墊12B係與晶片銲墊u相連形成,且亦 以電性方式連接。而且,在接合墊丨2表面為了提高所搭接 的金屬細線的接著性,而形成有由銀(Ag)等構成之電鍍 膜。 ·又 半導體元件1 3係透過銲材1 9而安裝在晶片銲墊工i 表面,在此是透過銲材19而安裝有在半導體元件中較為大 型之1C晶片。而且,形成在半導體元件]3表面的電極和 314863 9 1240603 接5墊u是透過金屬細線15而作電 性方式與晶片銲墊U連接之接合墊”。此外’以電 15而與半導體元件13作電性連接一疋透過金屬細線 使用銲錫或銀陳等導電性接著劑此::使用之輝材可 緣性樹脂將半導體元件13安 " ,亦可使用絕 文衣在日日片銲墊u 〇 溝道14係以圍繞半導體元件13 车日執1 1闽、息加 9方式而形成在晶片 紅墊11周邊部,而且充填絕緣 乃 丨工何乃日1 6。而且,渣请 的深度形成地比晶片銲墊丨丨的厚产%。 又火。如此,以環繞容壯 有半導體元件13之區域的方式形 一衣 本道辦-Μ , 成溝道14,藉此可在將 半V體7L件1 3安裝於已熔融之銲材 何19上部的步驟中,防 止銲材19從晶片銲墊u流出。 出具月豆而吕,即使銲材19 攸女I有半導體元件13之區域 X机出,鲜材1 9亦將貯存在 溝迢14。因而’溝道14係發揮作為防止銲材”從晶片鲜 墊11流出之阻止區域的功能。關於溝道14之製造方法將 =後述,但溝道14係藉由蝕刻(eichlng)而和分隔溝起 製造。因而,溝道14之剖面寬度係形成地比分隔溝9之寬 度窄。 、 絕緣性樹脂1 6係使晶片銲墊1丨及接合墊1 2之背面露 出,而將整體加以封裝。再者,形成在晶片銲墊丨丨表面之 溝道1 4亦填充有絕緣性樹脂丨6。在此係封裝半導體元件 13、金屬細線15、晶片銲墊11及接合墊ι2。·絕緣性樹脂 1 6之材料可採用藉由轉注成型法所形成之熱硬化性樹 脂’或藉由射出成型法所形成之熱可塑性樹脂。 銲材1 9係為銲錫或銀(Ag)膠等導電性膠漿(paste),具 10 314863 1240603 有接合半莫μ _ 如兀件1 3和晶片銲墊1 ]夕#田 係為導電性材料,因此半導… 用。由於銲材19 係以電性 Uhl件】3背面和^輝塾n 接合墊12B VI接。而且’形成在晶片銲墊η上下兩側之 i2B亦與晶片銲墊以 用金屬細線15將半導體元件13二二=妾。因而,使 接’藉此可使形成在半導 : 。墊12β相連 件」3背面作電性連接。 纟面的琶路和半導體元 參照第2圖,說明關於形成在北 極17。外部電極17係形& ^衣月面之外部電 合墊12的背面。再者,片銲墊11之接 個外邱+籽m ,于墊11的为面亦裝設有多數 敕侗〜 卜Ρ电極17係在電路裝置1〇背面的 域,以矩陣狀且等間隔裝設有複數個。藉此,透過 〜。$極17 ’將電路裝置1()安裝在母板(刪herb〇a 文裝基板時’可減少作用在外部電極口之應力。 , 荃照第2圖(B),藉由光阻劑18之開口部規限形成在 晶片鲜塾η背面之外部電極17的位置及大小。而且,形 成在接合墊u背面之外部電極㈣位置及大小係根據接 合整12的背面而形成。作為接合塾12之材料的銅等金屬 係濕潤性良好的材料’藉由該濕潤性規限外部電極17之位 置及大小。如& ’藉由利用接合塾12之濕潤性來規限形成 在接合誓12背面之外部電極17的位置及大小,即使光阻 劑18之開口部位置偏移,亦可精確度良好地形成外部電極 17 〇 的 本發明之特徵在於將溝道丨4以圍繞半導體元件】 314863 1240603 方式而形成在晶片銲墊u的周 13安裝在⑽融的銲材19時,,將半導體元件 13的重量等而往周圍.擴散, 會由於半導體元件 會貯在扃、羞卞η 士 田万、擴政到周圍的銲材19 曰打存在溝迢14中’因此可 的表面流出。因而,可防止 ’〒19從晶片銲墊11 1〇 , 止由於流出的銲材19盥接八執 1 2相接觸而引起銲塾彼 α墊 疋你 ^生短路的情形。·而且,藉此, 。使晶片銲墊11形成為與安曰 一 在/、日日片銲墊1 1之半導俨 兀件13大致同等。再者,可 牛^-且 19相u 7风便日日片銲墊11和接合墊 -相接近’而可縮小電路裝置1G之整體尺寸。再者 上述藉由在晶片銲墊丨丨表面, 彳…一 表面开,成溝運14,而使晶片銲墊 11和纟巴緣性樹脂丨6相接觸的 妒仇Μ 口面矛貝3曰加,因此可提高晶片 知墊1 1和絕緣性樹脂〗6的接著力。 麥照第3圖說明其
心 电%衣1 i ϋ Α。第3圖(A /丁、电路裝置10A之剖視圖,第3圖⑺)係第3圖(句之χ χ 線之剖視圖。電路裝置1GA具有與第丨圖所說日月之電路參 置1〇大致同樣之構成,在以形成於晶片銲墊21表面之溝 道14所環繞的區域,更以格子狀形成溝道“A。 彳 溝道14係以防止用以固接半導體元件13之銲材w 從晶片銲墊丨丨表面流出為目的,而裝設在晶片銲墊1 1的 周邊部。在此係在以溝道14環繞之區域復以格子狀形成溝 道14A。以袼子狀形成的溝道14A亦具有與溝道14相同 的剖面形狀。如此藉由以袼子狀形成溝道14的方式·,可使 更多量的銲材19貯存在溝道14,因此可防止銲材19從晶 片銲墊1 1表面流出。再者,由於可更加使晶片銲墊】1和 314863 !240603 硙緣性樹月旨16相接觸的面積增加,因此可提高晶片 11和、吧緣性樹脂1 6之密接性。 接著說明設置溝道14之進—步優點。可使用配料機 spenser)等供應銲材之機械,料材η塗佈在日日日片鲜塾 11的表面,但是該配料機可供應之銲材19最小塗 θ [5] / / 1 里 Τξ! =疋的。因而,配料機之最小塗佈量比將半導體元件η =在晶片㈣11時所需銲材19量較多時,銲材19恐有° 攸曰曰片鲜墊丨丨的表面流出之虞。因此’藉由裝設溝道1 4, 可防止銲材1 9流出。 (說明電路裝置10之製造方法的第2實施形態) 在本實施例中將說明電路裝置1〇之製造方法。本實 施形態中,係以如下述之步驟製造電路裝置1〇。亦即,^ 由:準備導電薄片40之步驟;在導電薄片4〇形成比其^ 度為淺的分隔溝9而形成構成複數個電路裝置部* 5之晶片 銲墊11及接合墊12,同時以環繞預定固接的半導體元件 1 3的區域的方式而在晶片辉塾〗丨形成比分隔溝9淺的溝 道14之步驟;透過銲材19而將半導體元件13固接於晶片 銲墊11之步驟;對半導體元件13和預期之接合墊丨2進行 打線接合(wire bonding)之步驟;以絕緣性樹脂a包覆半 導體元件13 ’且充填於分隔溝9及溝道M之方式共同成 型之步驟;去除導電薄片40之背面至露出絕緣性樹脂16 為止之步驟;以及,藉由切割絕緣性樹脂1 6而分隔成各電 路裝置]0之步驟所構成。以下參照第4圖至第丨〇圖說明 本發明之各步驟。 314863 13 1240603 如第4圖至第6圖所示,本發明之第!步驟係準備導 電薄片4〇,在導電薄片40形成比其厚度為淺的分隔溝9 而形成構成複數個電路裝置部45之晶片鮮墊Μ接合堅 1 2 ’同時以環繞預定固接 — u按冬千v肢兀件n之區域的方式而 在晶片鲜塾1 1形成比分隔溝9淺的溝道14。 在本步驟中,首先準備如第 _ ^ _ .圖(A)之潯板(sheet)狀導 兒潯片40。該導電薄片4〇係考 ^ /心奸材之附者性、接合性、 电鍍性來選擇其材料,材料係掠 違千一 材科如彳木用以銅(Cu)為主要材料之 〜兒涛片、以I呂(A1)為主要材料導帝 ( 4 丁十之¥兒潯片或由鐵(Fe)-鎳 kNl)寺合金所構成之導電薄片等。 導電薄月的厚度若考慮後續的蝕刻處理時,則以約 〇μ1Ώ至300叫為佳,但基本上3〇〇叫以上或1〇陶以下 、可。如後述,若形成比導電薄片4〇的厚度淺的分隔溝9 即可。 其中’涛板狀導電薄片4〇係準備成以特定寬度例如 5咖捲成滾筒狀,而將其運送到後述各步驟亦可,或是準 傷切割成特定大小之細長狀導電薄片4〇,而運送到後述各 歩驟亦可。 具肚而。如第4圖(Β)所示,在細長狀導電薄片4〇 間隔並'列4至5個形成有多數電路裝置部4 $之方塊〇。 各方塊42間設㈣:縫43,可吸收在成型步驟等因加熱處 硬而產生之導電薄片40的應力。且在導電薄片4〇上下周 ^以特定間隔設有索引孔(index h〇le)44 Μ吏用於各步驟之 定位。接著,形成導電圖案。 314863 14 1240603 首先,如第5圖所示’在導兩㊄ —兒〜片40上形成光阻劑(耐 敍刻光罩)PR,且以使除了成為 、.. ^ &為¥電圖案5 1之區域之外的 導電薄片40露出的方式佶 飞使光卩且劑PR進行圖案化 (patterning)。接著,如第 6 151 (A)所不,使導電薄片40選 擇性進行钱刻。在此,導雷m 、电圖木51形成各電路裝置部45 之晶片銲墊1 1及接合墊1 2。 參照第6圖(A),在形成右、、盖、蓄n ^ …战有溝逼1 4及分隔溝9之處設 有光阻劑之開口部。狹接,报士、女 y I…、设形成有溝道14之處的開口部寬 度會形成地比形成有公卩忌、、I Q + 一 ^ 成百刀隔溝9之處的寬度為窄。具體而 言,該寬度將形成不到一丰。由仏拉 ^ J千由於稭由蝕刻去除導電薄片 40係以寺方性進行,因此葬. 丁 u此精由上述將對應溝道μ的光阻 劑開口部形成較窄的方式,可將溝道14之深度形成地比分 隔溝9為淺。其中,上述姓刻步驟可藉由將導電薄片4〇 浸潰在姓刻液之方式進行。 第6圖(B)中表示形成晶片銲墊u及接合墊12之導電 圖案5卜本圖係與第4圖(B)所示之i個方塊“放大者相 對應。1個陰影線部分係為1個電路裝置部,1個方塊 42中以2列2行之矩陣(matrix)狀排列多數個電路裝置部 45,在每個電路裝置部45各設有相同的導電圖案$丨。各 方塊的周邊設有框形圖案46,與其略微間隔而在其内側設 有切d 0宁之疋位g己號4 7。框形圖案4 6係使用於與成型模 具嵌合時,且導電薄片40之背面於蝕刻後具有補強絕緣性 樹脂1 6之作用。此外,於各電路裝置部中,形成在晶片銲 塾1 1上下兩側之接合墊1 2係與晶W銲墊1 1 一體化,而且 15 314863 1240603 兩者亦以電性方式相連接。 如弟7圖所示,本於明〜 半導體元件接在久1^/ 2步料透過銲材19將 失^ , 各'路裝置部45之晶片銲墊U。 ,-弟7圖⑷,透過銲材19將半 本在此,銲材19係辑錫~^^ 藉由二在r:中,因為輝材晴_態,因此, 導沪从 載置於鲜材19上部,銲材19會因半 塾Γ二的重量等而擴散到周圍。在此,由於在晶片銲 成溝=部以環繞載置有半導體元件13之區域的方式形 出。\ 因此擴散的焊材19並不會從晶片銲塾U流 已到達溝這14之銲材19由於會形成流入溝道14之形 因此溝道Μ㈣揮作為阻止鮮錫流出之阻止區域的功 =。再者,亦可使用絕緣性樹脂將半導體元件丨3 片銲墊11。 π #曰曰 第8圖所示,本發明之第3步驟係對半導體元件υ 和預期的接合墊1 2進行打線接合。 具體而言,將安裝在各電路裝置部之半導體元件13 的電極和預期的接合墊12,利用藉由熱壓接進行之球形接 合(ball bonding)及藉由超音波進行之楔形接合 bonding)而總括進行打線接合。 如第9圖所示,本發明之第4 .步驟係以絕緣性樹脂包 覆半導體元件13,且填充在分隔溝9及溝道14之方式而 共同成型。 如第9圖(A)所示’在本步驟中,絕緣性樹脂I $完全 314863 1240603 地包覆半導體元件1 3、複數個晶片銲塾i i及接合塾1 2, h iWi /冓9及溝道1 4中填充有絕緣性樹脂1 6,且與分隔溝9 嵌合而強固地結合。然後,藉由絕緣性樹脂1 6支撐晶片銲 墊1 1及接合墊1 2。 且在本步驟中,可藉由轉注成型法(transfer m〇ld)、射 出成成型法(injection mold)或膠埋法(p〇tting)而實現。以 樹月曰材料而3,環氧樹脂等熱硬化性樹脂可藉由轉注成型 法而貫現,聚醯亞胺樹脂(polyimide resin)、聚笨硫醚0〇1乂 phenylene sulfide)等熱可塑性樹脂可藉由射出成型法而實 現。 、 士 .…一"人土仏%珂成型法 如第9圖(B)所示’各方塊係將電路裝置部收容在上個 共通的成型模具中,而以"固絕緣性樹脂Μ對每—方塊丘 同進行成型。因此,與習知之轉注 〜、 珉生去寻般,將各電路 I置部個別進行成型之方法相較, 脂量…。 了達成減少大量樹 本步驟之特徵為到包覆絕緣性 雪0為止,形成導 •51之導電…0係當作支持基板。在以往伶採用 原本亚不需要的支持基板來形成導+圖安 中,作為去梏其祐夕、曾十一 u 、圖木’但在本發明 作為支持基板之導電涛片4〇係作為 料。因此,具有在作章上可朽〜 之必要材 可實現降低成本。 +之k點,且 而且由於分隔溝9形成地比導兩 並未個別地分隔導電薄片40作為導"::厚度淺,因此 兒圖案51。因而其特 314863 17 l24〇6〇3 徵為作為薄板狀導 16進行成型時,運〜# ^ 40以14處理,且將絕緣性樹脂 易。 、到杈具、女裝到模具的作業非常地容 本發明之第5步驟係去除導電薄片……· 緣性樹脂為止。 兒厚片4〇月面至露出絕 本步驟係以化壤 -s而乂 个方式及/或物理方式去除導電薄片40 月面’而分隔作為導带 “ ^ ^ S Jn 40 雷射之金屬;ii發等弟:回* *由研磨、研削、蝕刻、 一甸…\寺來實施本步驟。 實驗中將導雷餐 ^ ^ ^ ^ ^ I ; 7a ;Γ)Τ§)^ ^ 的面。其結果係分隔形成; ㈣成導電圖案51之背面露出二果 亦即,填充在分Ρ、# π 巴、象1*生Μ月曰16之構造。 仕刀Ρί¥3溝9之絕緣性樹脂1 6 5]的表面係形成實質上相Α 的表面和導電圖案 乂貝貝上相一致之構造。 再者,進行導電圖案5丨 圖所示之最终構迕… 處理’例如後得第1 兩要…亦即’將銲錫等導電材料附著在基於 而要而路出之導電圖案51,且完成為電路裝置。“、 再者於本步驟中,將填充在 1 6 ^ Μ . „ ^ ^ M m 出在背面。 、,彖H树月曰1 6亚未露 μ 圖所不,本發明之第6步驟係對每一電路I …將絕緣性樹脂16藉由切割加以分隔。 路# 本步驟中,以直允七 置放台,以”刀4二: 2吸附在切割襄置之 。49 >D者各電路裝置部45間的切割線(鏈 !24〇6〇3 線)切割分隔溝9之絕緣性樹脂i6,而分隔成個別的電路 裝置。 本步驟中,切割刀49係以大致切開絕緣性樹脂1 6之 切削深度進行,從切割裝置取出方塊4 2後,以滾筒製作成 如巧克力塊即可。切割時,預先辨識在前述第1步驟中裝 設、之各方塊的定位記號4 7,將其當作基準進行切割。幕所 週知切割係朝向縱向切割所有的切割線後,9 0度旋轉置放 台再按照橫向切割線7 0進行切割。 [發明功效] 本發明可達成如以下所示之效果。 第1,本發明中,以圍繞半導體元件13的方式在接合 墊11周邊部裝設溝道1 4,由於防止用以固接半導體元件 13之銲材19流出,因此可防止流出之銲材19造成導電圖 案彼此發生短路。 第2,由於可藉由溝道14防止銲材19流出,因此可 使Ba片鲜墊1 1和接合墊i 2接近,而可使全體裝置小型化。 第 方、文衣半^體元件1 3之步驟中,裝設在晶片銲 塾1 2周邊部的溝道1 4發揮 λ坪TF為阻止|干材流出之阻止區域
的功能,可防止銲材1 9户Φ不丨J 一 ^ y机出到外部而造成導電圖案彼此發 [圖示簡單說明] 之電路裝置之俯視圖(Α),剖視圖 第1圖係說明本發明 (Β) 〇 第2圖係說明 本毛明之電路裝置之背面圖(Α),剖視圖 3]4863 】9 1240603 (B) (B) (A) 圖。 (A) (A) (A) (A) 9 1卜 13 15、 17 第J圖係說明本發明之灸 、 。 电路裝置之剖視圖(A),俯視圖 第4圖係說明本發明 ,俯視圖(B)。 笔路裝置之製造方法的剖視圖 第5圖係說明本發 之電路裝置之製造方法的剖視 第6圖係說明本發明之命 ,俯視圖(B)。 笔路裝置之製造方法的剖視圖 第7圖係說明本發明% ,俯視圖(B)。 兒路裝置之製造方法的剖視圖 第8圖係說明本發明 ,俯視圖(B)。 <兔路裝置之製造方法的剖視圖 第9圖係說明本發明略 ,俯視圖(B)。 兒路裝置之製造方法的剖視圖 卜 ^ 吩衮置之製造方法 第11圖係說明習知 <电路裝置之剖視圖 第1 2圖係說明習知 t电路裝置之剖視圖 分隔溝 、10A 電路裝置 69 晶片鲜墊 、12A、12B 接合墊 半導體元件 U、14A 溝道 72 金屬細線 1 6 絕緣性樹脂 外部電極 1 8 光阻劑 314863 20 1240603
19 銲材 40、 60 導電薄, 42 方塊 43 隙缝 44 索引孔 45 電路裝置部 46 框形圖案 47 定位記號 49 切割刀 5 1 導電圖案 61 封裝型半導體裝置 62 半導體晶片 63、 73 樹脂層 64 導線端子 65 玻磕環氧基板 6 6 CSP 67 第1電極 68 第2電極 70 第1背面電極 71 第2背面電極 CC 晶片電容器 CR 晶片電阻 PR 光阻劑 PS 印刷基板 T 電晶體晶片 TH 貫通孔 314863
Claims (1)
1240603 第92 1 1 8684號專利申請案 申凊專利範圍修正本 1. - if φ ^ ^ (94 年 3 月 31 曰) 種"路裝置之製造方法,其特徵為具有: 準備導電薄片之步驟; 在前述導電薄片形成 椹A、-批y X比具知度淺的分隔溝而形成 構成妓數個電路裝置部之 成 繞預定固接的半導㉛元株 墊’同時以圍 墊形成比一: 件之區域的方式在前述晶片銲 形成^則述分隔溝淺的溝道之步驟; 驟;在前述晶片料透過固接材而固接半導體元件之步 接合ίΐΐ半導體元件和預期之前述接合塾進行打線 以絕緣性樹脂包覆前述半導體元件日谊右私a 分隔溝及前述溝道之方式;兀件且填充於"述 万式共同成型之步驟; 去除前述導雷 為止之牛/片之月面至露出前述絕緣性樹脂 儿〈穸驟,以及 藉由切割前述絕緣性抖日t七七 裝置之步驟。 树知之方式而分隔成各電路 如申清專利範圍窜·| τ5 前述溝道的寬产"丨之電路裝置之製造方法’其中, 3. 如申請專利^ =比前述分隔溝窄。 前述固接材俜銲錫J之電路裝置之製造方法’其中, 4. 如申a Γ干錫或銀(Ag)膠。 、,中6月專利範圍第i項之雷 前述固接分私 凌置之‘造方法,其中, 接材‘絶緣性接著劑。 314863(修正版)
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KR100672214B1 (ko) * | 2005-12-30 | 2007-01-22 | 김대성 | 스텝머신기능을 구비한 자전거 |
US7836586B2 (en) * | 2008-08-21 | 2010-11-23 | National Semiconductor Corporation | Thin foil semiconductor package |
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JP3600131B2 (ja) * | 2000-09-04 | 2004-12-08 | 三洋電機株式会社 | 回路装置の製造方法 |
JP2002110888A (ja) * | 2000-09-27 | 2002-04-12 | Rohm Co Ltd | アイランド露出型半導体装置 |
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Also Published As
Publication number | Publication date |
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JP4093818B2 (ja) | 2008-06-04 |
CN1501490A (zh) | 2004-06-02 |
TW200405779A (en) | 2004-04-01 |
CN100492632C (zh) | 2009-05-27 |
KR20040026129A (ko) | 2004-03-27 |
JP2004071898A (ja) | 2004-03-04 |
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