JP2020505769A - 半導体構造用の支持体 - Google Patents

半導体構造用の支持体 Download PDF

Info

Publication number
JP2020505769A
JP2020505769A JP2019538671A JP2019538671A JP2020505769A JP 2020505769 A JP2020505769 A JP 2020505769A JP 2019538671 A JP2019538671 A JP 2019538671A JP 2019538671 A JP2019538671 A JP 2019538671A JP 2020505769 A JP2020505769 A JP 2020505769A
Authority
JP
Japan
Prior art keywords
support
layer
insulating layer
silicon
base substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2019538671A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020505769A5 (https=
Inventor
レノー パトリック
レノー パトリック
ブルーカート マルセル
ブルーカート マルセル
アリベール フレデリック
アリベール フレデリック
ヴェティズー クリステル
ヴェティズー クリステル
カペッロ ルチアナ
カペッロ ルチアナ
ベルトラン イザベル
ベルトラン イザベル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of JP2020505769A publication Critical patent/JP2020505769A/ja
Publication of JP2020505769A5 publication Critical patent/JP2020505769A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/30—Diffusion for doping of conductive or resistive layers
    • H10P32/302—Doping polycrystalline silicon or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1918—Preparing SOI wafers using bonding including charge trapping layers, e.g. polycrystalline materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Semiconductor Memories (AREA)
JP2019538671A 2017-01-26 2018-01-11 半導体構造用の支持体 Pending JP2020505769A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1750646 2017-01-26
FR1750646A FR3062238A1 (fr) 2017-01-26 2017-01-26 Support pour une structure semi-conductrice
PCT/EP2018/050677 WO2018137937A1 (en) 2017-01-26 2018-01-11 Support for a semiconductor structure

Publications (2)

Publication Number Publication Date
JP2020505769A true JP2020505769A (ja) 2020-02-20
JP2020505769A5 JP2020505769A5 (https=) 2020-12-24

Family

ID=59253590

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019538671A Pending JP2020505769A (ja) 2017-01-26 2018-01-11 半導体構造用の支持体

Country Status (9)

Country Link
US (2) US11373856B2 (https=)
EP (1) EP3574519B1 (https=)
JP (1) JP2020505769A (https=)
KR (1) KR20190108138A (https=)
CN (1) CN110199375A (https=)
FR (1) FR3062238A1 (https=)
SG (1) SG11201906017UA (https=)
TW (1) TW201841341A (https=)
WO (1) WO2018137937A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115777139A (zh) * 2020-07-28 2023-03-10 索泰克公司 将薄层转移到设有电荷俘获层的载体衬底的方法
WO2024134916A1 (ja) 2022-12-19 2024-06-27 新電元工業株式会社 半導体装置
EP4621851A1 (en) 2022-12-19 2025-09-24 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3062517B1 (fr) 2017-02-02 2019-03-15 Soitec Structure pour application radiofrequence
FR3098342B1 (fr) 2019-07-02 2021-06-04 Soitec Silicon On Insulator structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF
CN110687138B (zh) * 2019-09-05 2022-08-05 长江存储科技有限责任公司 半导体结构的测量与边界特征提取方法及其装置
FR3104322B1 (fr) * 2019-12-05 2023-02-24 Soitec Silicon On Insulator Procédé de formation d'un substrat de manipulation pour une structure composite ciblant des applications rf
FR3113184B1 (fr) * 2020-07-28 2022-09-16 Soitec Silicon On Insulator Procede de preparation d’un substrat support, et procede de report d’une couche mince sur ce substrat support
US11522516B2 (en) 2020-08-27 2022-12-06 RF360 Europe GmbH Thin-film surface-acoustic-wave filter using lithium niobate
WO2022141442A1 (zh) * 2020-12-31 2022-07-07 华为技术有限公司 一种集成电路、功率放大器及电子设备
FR3127588B1 (fr) 2021-09-28 2025-01-17 Lynred Procede de realisation d’au moins une fenetre optique, fenetre optique et detecteur infrarouge associes
EP4559018A1 (fr) * 2022-07-19 2025-05-28 Soitec Procédé de fabrication d'un substrat support pour application radiofréquences
FR3138239B1 (fr) * 2022-07-19 2024-06-21 Soitec Silicon On Insulator Procédé de fabrication d’un substrat support pour application radiofréquences
CN117594521A (zh) * 2023-12-25 2024-02-23 中国科学院微电子研究所 一种低衬底漏电的rfsoi晶圆及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014127590A (ja) * 2012-12-26 2014-07-07 Shin Etsu Handotai Co Ltd 高周波半導体装置及び高周波半導体装置の製造方法
WO2016081313A1 (en) * 2014-11-18 2016-05-26 Sunedison Semiconductor Limited A method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6910A (en) * 1849-11-27 Abraham johnson and henry johnson
US269976A (en) * 1883-01-02 John watters
US347597A (en) * 1886-08-17 habyey
US10A (en) * 1836-08-10 Bariah Swift Dye-wood and dye-stuff cutting and shaving machine
KR100701341B1 (ko) 1999-03-16 2007-03-29 신에쯔 한도타이 가부시키가이샤 실리콘 웨이퍼의 제조방법 및 실리콘 웨이퍼
CA2407154A1 (en) 2000-04-27 2001-11-01 Verion, Inc Zero order release and temperature-controlled microcapsules and process for the preparation thereof
FR2838865B1 (fr) 2002-04-23 2005-10-14 Soitec Silicon On Insulator Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee
FR2860341B1 (fr) 2003-09-26 2005-12-30 Soitec Silicon On Insulator Procede de fabrication de structure multicouche a pertes diminuees
US20070032040A1 (en) * 2003-09-26 2007-02-08 Dimitri Lederer Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses
FR2880189B1 (fr) 2004-12-24 2007-03-30 Tracit Technologies Sa Procede de report d'un circuit sur un plan de masse
US7217629B2 (en) * 2005-07-15 2007-05-15 International Business Machines Corporation Epitaxial imprinting
FR2911431B1 (fr) * 2007-01-16 2009-05-15 Soitec Silicon On Insulator Procede de fabrication de structures soi a couche isolante d'epaisseur controlee
FR2933233B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
US8252653B2 (en) * 2008-10-21 2012-08-28 Applied Materials, Inc. Method of forming a non-volatile memory having a silicon nitride charge trap layer
FR2953640B1 (fr) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
EP3734645B1 (en) 2010-12-24 2025-09-10 Qualcomm Incorporated Trap rich layer for semiconductor devices
FR2973158B1 (fr) * 2011-03-22 2014-02-28 Soitec Silicon On Insulator Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences
US8772059B2 (en) * 2011-05-13 2014-07-08 Cypress Semiconductor Corporation Inline method to monitor ONO stack quality
FR2985812B1 (fr) 2012-01-16 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de test de substrats semi-conducteurs pour applications radiofrequences
US9601591B2 (en) * 2013-08-09 2017-03-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US9768056B2 (en) 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
US9299736B2 (en) 2014-03-28 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding with uniform pattern density
FR3019373A1 (fr) 2014-03-31 2015-10-02 St Microelectronics Sa Procede de fabrication d'une plaque de semi-conducteur adaptee pour la fabrication d'un substrat soi et plaque de substrat ainsi obtenue
FR3024587B1 (fr) * 2014-08-01 2018-01-26 Soitec Procede de fabrication d'une structure hautement resistive
US9853133B2 (en) * 2014-09-04 2017-12-26 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity silicon-on-insulator substrate
FR3029682B1 (fr) 2014-12-04 2017-12-29 Soitec Silicon On Insulator Substrat semi-conducteur haute resistivite et son procede de fabrication
US9618474B2 (en) * 2014-12-18 2017-04-11 Edico Genome, Inc. Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids
US10006910B2 (en) * 2014-12-18 2018-06-26 Agilome, Inc. Chemically-sensitive field effect transistors, systems, and methods for manufacturing and using the same
US10283402B2 (en) * 2015-03-03 2019-05-07 Globalwafers Co., Ltd. Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
JP6344271B2 (ja) * 2015-03-06 2018-06-20 信越半導体株式会社 貼り合わせ半導体ウェーハ及び貼り合わせ半導体ウェーハの製造方法
US9881832B2 (en) * 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
FR3037438B1 (fr) * 2015-06-09 2017-06-16 Soitec Silicon On Insulator Procede de fabrication d'un element semi-conducteur comprenant une couche de piegeage de charges
KR101666753B1 (ko) 2015-06-18 2016-10-14 주식회사 동부하이텍 고비저항 기판 상에 형성된 반도체 소자 및 무선 주파수 모듈

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014127590A (ja) * 2012-12-26 2014-07-07 Shin Etsu Handotai Co Ltd 高周波半導体装置及び高周波半導体装置の製造方法
WO2016081313A1 (en) * 2014-11-18 2016-05-26 Sunedison Semiconductor Limited A method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115777139A (zh) * 2020-07-28 2023-03-10 索泰克公司 将薄层转移到设有电荷俘获层的载体衬底的方法
JP2023535319A (ja) * 2020-07-28 2023-08-17 ソイテック 電荷トラップ層が設けられたキャリア基板に薄層を転写するプロセス
JP7728326B2 (ja) 2020-07-28 2025-08-22 ソイテック 電荷トラップ層が設けられたキャリア基板に薄層を転写するプロセス
US12525483B2 (en) 2020-07-28 2026-01-13 Soitec Method for transferring a thin layer onto a support substrate provided with a charge-trapping layer
WO2024134916A1 (ja) 2022-12-19 2024-06-27 新電元工業株式会社 半導体装置
EP4621851A1 (en) 2022-12-19 2025-09-24 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
US11373856B2 (en) 2022-06-28
EP3574519A1 (en) 2019-12-04
EP3574519B1 (en) 2020-08-19
US20220301847A1 (en) 2022-09-22
FR3062238A1 (fr) 2018-07-27
SG11201906017UA (en) 2019-08-27
US20200020520A1 (en) 2020-01-16
WO2018137937A1 (en) 2018-08-02
KR20190108138A (ko) 2019-09-23
TW201841341A (zh) 2018-11-16
CN110199375A (zh) 2019-09-03

Similar Documents

Publication Publication Date Title
US20220301847A1 (en) Support for a semiconductor structure
US11251265B2 (en) Carrier for a semiconductor structure
US12424995B2 (en) Method for manufacturing a structure comprising a thin layer transferred onto a support provided with a charge trapping layer
KR101379409B1 (ko) 전기 손실들이 감소된 반도체 온 절연체 타입 구조의 제조 공정 및 대응 구조
KR102172705B1 (ko) Rf 애플리케이션들을 위한 반도체 온 절연체 기판
JP2014512091A (ja) ハンドルウエハ内に高抵抗率領域を有するシリコン・オン・インシュレータ構造体およびそのような構造体の製法
KR102652250B1 (ko) 집적 무선 주파수 디바이스를 위한 기판 및 이를 제조하기 위한 방법
US10510531B2 (en) Method of fabrication of a semiconductor element comprising a highly resistive substrate
KR102484156B1 (ko) 전하를 트랩핑하기 위한 층을 포함하는 반도체 엘리먼트의 제조를 위한 프로세스
KR102612754B1 (ko) 반도체 구조물을 위한 지지체의 제조 방법
US10361114B2 (en) Method for preparing substrate with carrier trapping center
KR102026506B1 (ko) 다층 반도체 디바이스들의 제조에서의 저온 층 전이를 위한 방법
JP6070487B2 (ja) Ｓｏｉウェーハの製造方法、ｓｏｉウェーハ、及び半導体デバイス
KR20240101836A (ko) 전하-트래핑 층이 구비된 지지 기판을 제조하기 위한 프로세스
US20180182662A1 (en) Method for preparing substrate with carrier trapping center
TW202329362A (zh) 製造裝配有電荷捕捉層之載體基板之方法
KR20250141690A (ko) 오염 제한 전하 트래핑 층이 제공된 캐리어에 부착된 표면 층을 포함하는 구조체 및 제조 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20201111

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20201111

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20211202

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20211214

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20220712