FR3098342B1 - structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF - Google Patents

structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF Download PDF

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Publication number
FR3098342B1
FR3098342B1 FR1907328A FR1907328A FR3098342B1 FR 3098342 B1 FR3098342 B1 FR 3098342B1 FR 1907328 A FR1907328 A FR 1907328A FR 1907328 A FR1907328 A FR 1907328A FR 3098342 B1 FR3098342 B1 FR 3098342B1
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FR
France
Prior art keywords
semiconductor structure
layer
applications
porous layer
buried porous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1907328A
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English (en)
Other versions
FR3098342A1 (fr
Inventor
Emmanuel Augendre
Frédéric Gaillard
Thomas Lorne
Emmanuel Rolland
Christelle Veytizou
Isabelle Bertrand
Frédéric Allibert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Soitec SA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1907328A priority Critical patent/FR3098342B1/fr
Priority to TW109109850A priority patent/TW202103320A/zh
Priority to PCT/EP2020/058316 priority patent/WO2021001066A1/fr
Priority to JP2021578062A priority patent/JP7464631B2/ja
Priority to EP20712591.5A priority patent/EP3994722A1/fr
Priority to KR1020227003597A priority patent/KR20220025892A/ko
Priority to US17/623,499 priority patent/US20220359272A1/en
Priority to CN202080048789.1A priority patent/CN114424332A/zh
Publication of FR3098342A1 publication Critical patent/FR3098342A1/fr
Application granted granted Critical
Publication of FR3098342B1 publication Critical patent/FR3098342B1/fr
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Porous Artificial Stone Or Porous Ceramic Products (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

L’invention concerne une structure semi-conductrice (10) pour applications radiofréquences comprenant : - un substrat support (2) en silicium comportant une couche méso-poreuse (3), - une couche diélectrique (4) disposée sur la couche méso-poreuse (3), - une couche superficielle (5) disposée sur la couche diélectrique (4). La structure (10) est remarquable en ce que : - la couche méso-poreuse (3) comporte des pores creux dont les parois internes sont majoritairement tapissées d’oxyde, et présente une épaisseur comprise entre 3 et 40 microns et une résistivité supérieure à 20 kohm.cm sur toute son épaisseur, - le substrat support (2) présente une résistivité comprise entre 0.5 et 4 ohm.cm. L’invention concerne également un procédé de fabrication d’une structure semi-conductrice (10). Figure à publier avec l’abrégé : F igure 1
FR1907328A 2019-07-02 2019-07-02 structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF Active FR3098342B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR1907328A FR3098342B1 (fr) 2019-07-02 2019-07-02 structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF
TW109109850A TW202103320A (zh) 2019-07-02 2020-03-24 供無線射頻應用之包含埋置多孔層之半導體結構
JP2021578062A JP7464631B2 (ja) 2019-07-02 2020-03-25 高周波アプリケーション用の埋め込みポーラス層を含む半導体構造
EP20712591.5A EP3994722A1 (fr) 2019-07-02 2020-03-25 Structure semi-conductrice comprenant une couche poreuse enterree, pour applications rf
PCT/EP2020/058316 WO2021001066A1 (fr) 2019-07-02 2020-03-25 Structure semi-conductrice comprenant une couche poreuse enterree, pour applications rf
KR1020227003597A KR20220025892A (ko) 2019-07-02 2020-03-25 Rf 응용들을 위한 매립된 다공성 층을 포함하는 반도체 구조물
US17/623,499 US20220359272A1 (en) 2019-07-02 2020-03-25 Semiconductor structure comprising an underground porous layer, for rf applications
CN202080048789.1A CN114424332A (zh) 2019-07-02 2020-03-25 用于射频应用的包括埋置多孔层的半导体结构

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1907328A FR3098342B1 (fr) 2019-07-02 2019-07-02 structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF
FR1907328 2019-07-02

Publications (2)

Publication Number Publication Date
FR3098342A1 FR3098342A1 (fr) 2021-01-08
FR3098342B1 true FR3098342B1 (fr) 2021-06-04

Family

ID=68138491

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1907328A Active FR3098342B1 (fr) 2019-07-02 2019-07-02 structure semi-conductrice comprenant une couche poreuse enterrée, pour applications RF

Country Status (8)

Country Link
US (1) US20220359272A1 (fr)
EP (1) EP3994722A1 (fr)
JP (1) JP7464631B2 (fr)
KR (1) KR20220025892A (fr)
CN (1) CN114424332A (fr)
FR (1) FR3098342B1 (fr)
TW (1) TW202103320A (fr)
WO (1) WO2021001066A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230108712A1 (en) * 2021-10-05 2023-04-06 Globalfoundries U.S. Inc. Ic structure including porous semiconductor layer under trench isolation

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4708577B2 (ja) * 2001-01-31 2011-06-22 キヤノン株式会社 薄膜半導体装置の製造方法
US20040262686A1 (en) * 2003-06-26 2004-12-30 Mohamad Shaheen Layer transfer technique
JP5673170B2 (ja) 2011-02-09 2015-02-18 信越半導体株式会社 貼り合わせ基板、貼り合わせ基板の製造方法、半導体デバイス、及び半導体デバイスの製造方法
FR2977070A1 (fr) 2011-06-23 2012-12-28 Soitec Silicon On Insulator Procede de fabrication d'un substrat semi-conducteur comprenant du silicium poreux, et substrat semi-conducteur
FR2977075A1 (fr) * 2011-06-23 2012-12-28 Soitec Silicon On Insulator Procede de fabrication d'un substrat semi-conducteur, et substrat semi-conducteur
FR2985812B1 (fr) 2012-01-16 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de test de substrats semi-conducteurs pour applications radiofrequences
FR3024587B1 (fr) * 2014-08-01 2018-01-26 Soitec Procede de fabrication d'une structure hautement resistive
US10290533B2 (en) * 2015-03-17 2019-05-14 Globalwafers Co., Ltd. Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures
FR3040108B1 (fr) 2015-08-12 2017-08-11 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice avec collage direct temporaire exploitant une couche poreuse
US10181428B2 (en) 2015-08-28 2019-01-15 Skyworks Solutions, Inc. Silicon on porous silicon
FR3062238A1 (fr) 2017-01-26 2018-07-27 Soitec Support pour une structure semi-conductrice
CN108807284B (zh) * 2017-04-28 2020-06-26 环球晶圆股份有限公司 一种外延接合基板及其制造方法

Also Published As

Publication number Publication date
FR3098342A1 (fr) 2021-01-08
CN114424332A (zh) 2022-04-29
EP3994722A1 (fr) 2022-05-11
TW202103320A (zh) 2021-01-16
KR20220025892A (ko) 2022-03-03
WO2021001066A1 (fr) 2021-01-07
JP7464631B2 (ja) 2024-04-09
JP2022538463A (ja) 2022-09-02
US20220359272A1 (en) 2022-11-10

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