WO2022141442A1 - 一种集成电路、功率放大器及电子设备 - Google Patents

一种集成电路、功率放大器及电子设备 Download PDF

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Publication number
WO2022141442A1
WO2022141442A1 PCT/CN2020/142258 CN2020142258W WO2022141442A1 WO 2022141442 A1 WO2022141442 A1 WO 2022141442A1 CN 2020142258 W CN2020142258 W CN 2020142258W WO 2022141442 A1 WO2022141442 A1 WO 2022141442A1
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Prior art keywords
material layer
integrated circuit
sic
crystal
resistivity
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PCT/CN2020/142258
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English (en)
French (fr)
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丁瑶
胡彬
赫然
段焕涛
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华为技术有限公司
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Priority to CN202080108231.8A priority Critical patent/CN116783719A/zh
Priority to PCT/CN2020/142258 priority patent/WO2022141442A1/zh
Publication of WO2022141442A1 publication Critical patent/WO2022141442A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to an integrated circuit, a power amplifier and an electronic device.
  • High-electron-mobility transistors are mainly used in power amplifiers in electronic devices.
  • the power of the radio frequency signal generated in the radio frequency modulation circuit of electronic equipment is very small, and it needs to go through a series of amplification to obtain enough radio frequency power before it can be fed to the antenna for radiation.
  • the radio frequency power amplifier In order to obtain enough radio frequency power, the radio frequency power amplifier must be used to amplify the power of the radio frequency signal.
  • RF power amplifiers are widely used in radar, wireless communication, navigation, satellite communication, electronic countermeasures and other systems equipment, and are the key components of modern wireless communication.
  • the fifth generation of mobile communication technologies HEMTs based on gallium nitride (GaN) have broad application prospects with high performance characteristics.
  • GaN gallium nitride
  • the present application provides an integrated circuit, a power amplifier and an electronic device, which realizes a new type of composite substrate, which effectively improves the flexibility of design and has greater flexibility in cost control.
  • an integrated circuit in a first aspect, includes a substrate, wherein the substrate is covered with transistors, the substrate includes: a first material layer and a second material layer covered on the first material layer, wherein the transistor is covered on the second material layer;
  • the second material layer includes silicon carbide SiC, and the resistivity of the second material layer is different from that of the first material layer.
  • the composite substrate of the integrated circuit is mainly formed by two material layers of different resistivities, wherein the second material layer covers the first material layer, and the second material layer contains silicon carbide SiC, due to the different resistance
  • the composite substrate of the integrated circuit formed by the two material layers at a high rate enables the mass production of the composite substrate, and the performance adjustment of SiC is also more flexible, and there is greater flexibility in cost control.
  • the silicon carbide includes a single crystal form of silicon carbide, for example, the second material layer includes a first crystal form of silicon carbide, and the first crystal form can be 4H or 6H.
  • the reason for using single crystal type 4H or 6H silicon carbide is to facilitate the lattice adaptation of each structural layer of the transistor epitaxially grown on the substrate, for example, 4H-SiC or 6H-SiC and GaN have less lattice loss match.
  • the second material layer is bonded to the first material layer.
  • the second material layer is directly bonded to the first material layer, or the second material layer is bonded to the first material layer through an intermediate dielectric layer.
  • the second material layer may also be epitaxially grown on the first material layer. It should be noted that the epitaxial growth process has higher environmental requirements, while the bonding process has lower environmental requirements. It is only necessary to use the physical vapor transport process (PVT) process to obtain SiC crystals, which are obtained by cutting SiC crystals. After the slices are bonded to the first material layer, subsequent conventional thinning processing can be performed on the slices.
  • PVT physical vapor transport process
  • the first material layer is an insulating material; or, the first material layer is a conductive material, and the resistivity of the first material layer is lower than that of the second material layer.
  • the conductive properties of the material of the first material layer are not limited, so that the selectivity of the material of the first material layer can be enriched.
  • the material of the first material layer can be at least any one of the following silicon carbide SiC, aluminum nitride AlN, aluminum oxide Al 2 O 3 and silicon Si.
  • conductive SiC can be used.
  • the first material layer can also be made of AlN or Al 2 O 3 , for example, polymorphic AlN or Al 2 O 3 , whose resistivity is >1e5ohm.cm.
  • the first material layer can also be made of single crystal silicon or polycrystalline silicon, wherein when single crystal silicon or polycrystalline silicon is used, the resistivity of the first material layer is not limited.
  • the first material layer may also be a material layer with other indicators that do not meet the standards, and specific indicators such as non-uniform resistivity, crystal declination, and quality of micropipes do not meet the standards.
  • the off-angle between the axial direction [0001] of the SiC unit cell of the second material layer and the direction perpendicular to the second material layer is less than 4°.
  • the vertical surface of the second material layer 311 adopts the [0001] crystal axis of the SiC crystal, or is close to the [0001] crystal axis, that is, the axial deflection angle ⁇ is 0 to 4 degrees.
  • the smaller the axial deflection angle the better the lattice adaptation of each material layer, especially GaN, in the transistor.
  • the first material layer contains at least one crystal form.
  • the number and types of crystal forms contained in the first material layer are not limited, especially when the first material layer contains multiple crystal forms, the requirements for the manufacturing process are reduced, and the cost can be effectively reduced.
  • the first material layer is doped with impurities that reduce the resistivity of the first material layer
  • the second material layer is doped with impurities that increase the resistivity of the second material layer.
  • the first material layer is doped with impurities that provide carriers to reduce the resistivity of the first material layer.
  • the specific first material layer can be an N-type substrate with relatively low fabrication cost (for example, doped with nitrogen N element), and generally, an N-type substrate has lower requirements on raw materials and production processes than a high-purity substrate. Taking the growth of N-type SiC crystal as an example, the growth of N-type SiC crystal has no special requirements for the raw materials used, that is, both ordinary SiC powder and high-purity SiC powder are applicable.
  • the formation of the lower resistivity of the N-type SiC crystal is mainly due to the control of the nitrogen composition of the growth system, so that a large amount of nitrogen is successfully injected into the crystal, forming a high concentration of shallow donor energy levels in the SiC crystal, thereby providing a large number of freely mobile electrons as Therefore, there are no special requirements for the presence of other low-concentration ( ⁇ 1e18/cm3) impurities in the growth system and raw materials.
  • the second material layer is doped with a transition metal, so as to improve the resistivity of the second material layer. Transition metals include transition metal elements such as vanadium V or iron Fe.
  • the transition metal impurities in the SiC crystal can be used as the deep energy level compensation center, and the unintentionally doped nitrogen N and boron B in the SiC crystal can be compensated.
  • Semi-insulating properties of the second material layer are an ideal deep-level impurity, and the current SiC crystal doped with vanadium V exhibits high resistance characteristics.
  • the principle is that vanadium V can form a deep compensation energy level in the SiC crystal, which is located near the center of the forbidden band, and can be used as a deep main impurity to compensate for nitrogen, or as a deep donor impurity to compensate for boron, which can effectively bind carriers.
  • the role of SiC crystals can show semi-insulating properties at room temperature.
  • the doping concentration of the transition metal in the second material layer is 1e14 cm ⁇ -3 to 1e17 cm ⁇ -3.
  • Such a doping concentration is close to the concentration of impurities such as nitrogen N and boron B unintentionally doped in the SiC crystal, which can effectively compensate for the unintentionally doped nitrogen N and boron B in the SiC crystal.
  • the resistivity of the second material layer is greater than 1e5 ⁇ cm. In this way, the second material layer has a higher resistivity, and the second material layer exhibits semi-insulator properties, which is beneficial to the fabrication of transistors.
  • the concentration of the impurity providing carriers doped in the second material layer is less than 1e17cm ⁇ -3, and the impurities providing carriers at least include one or more of the following: nitrogen N, boron B, Al al.
  • the impurities of the second material layer are mainly unintentional doping, wherein the concentration of the impurities that provide carriers doped in the second material layer is less than 1e17cm ⁇ -3, and the impurities that provide carriers include at least one or more of the following nitrogen N, boron B, aluminum AL.
  • the second material layer produced in this way is a high-purity SiC crystal, which has the properties of a semi-insulator and can be adapted to the fabrication of transistors.
  • the thickness of the second material layer is greater than 1 ⁇ m, for example, the thickness of the second material layer is 1 to 100 ⁇ m.
  • a method for fabricating an integrated circuit includes: fabricating a second material layer on a first material layer, the second material layer comprising silicon carbide (SiC), the second material layer and the first material layer The materials of the layers differ in resistivity; transistors are fabricated on the second layer of material.
  • SiC silicon carbide
  • fabricating the second material layer on the first material layer includes: bonding a third material layer on the first material layer, the third material layer comprising silicon carbide SiC, and the third material layer The resistivity of the material layer is different from that of the first material layer; the third material layer is thinned to form the second material layer.
  • the method before the bonding of the third material layer on the first material layer, includes: performing a cutting process on the third material layer to form a pre-cut in contact with the first material layer layer; bonding a third material layer on the first material layer; comprising: bonding a third material layer on the first material layer, wherein the pre-cut layer is in contact with the first material layer; the pairing of the Thinning the third material layer to form the second material layer includes: peeling off the part of the third material layer except the pre-cut layer.
  • thinning the third material layer to form the second material layer includes: thinning the surface of the third material layer away from the first material layer to form second material layer.
  • the thinning process includes at least one or more of the following: grinding process and polishing process.
  • a power amplifier including an integrated circuit and a package structure, wherein the integrated circuit is packaged inside the package structure.
  • an electronic device including a power amplifier and an antenna, the power amplifier is used to amplify a radio frequency signal and output it to the antenna for outward radiation, and the power amplifier includes the above-mentioned power amplifier.
  • a non-transitory computer-readable storage medium for use with a computer having software for designing integrated circuits, the computer-readable storage medium having stored thereon one or more computer-readable data structures , a process facility fabricates the integrated circuits provided above using one or more of the computer-readable data structures described above.
  • FIG. 1 is a schematic structural diagram of a hexagonal crystal system provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a terminal according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a base station according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a substrate provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a substrate according to another embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a method for fabricating an integrated circuit provided by an embodiment of the present application.
  • FIG. 8 is a first structural schematic diagram in a manufacturing process of an integrated circuit according to an embodiment of the present application.
  • FIG. 9 is a second structural schematic diagram in a manufacturing process of an integrated circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram 3 in a manufacturing process of an integrated circuit provided by an embodiment of the present application.
  • FIG. 11 is a fourth schematic structural diagram in a manufacturing process of an integrated circuit provided by an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of an integrated circuit provided by another embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a power amplifier provided by an embodiment of the present application.
  • FIG. 14 is a fifth structural schematic diagram in a manufacturing process of an integrated circuit provided by an embodiment of the present application.
  • FIG. 15 is a sixth schematic structural diagram in a manufacturing process of an integrated circuit provided by an embodiment of the present application.
  • 16 is a schematic diagram of electrical performance simulation of a HEMT provided by an embodiment of the application.
  • 17 is a schematic diagram of electrical performance simulation of a HEMT provided by another embodiment of the application.
  • FIG. 18 is a schematic diagram of thermal performance simulation of a HEMT provided by an embodiment of the application.
  • FIG. 19 is a schematic diagram of thermal performance simulation of a HEMT provided by another embodiment of the present application.
  • Crystal form refers to the crystal structure, that is, the microscopic structure of the crystal, and refers to the specific arrangement of the actual particles (atoms, ions or molecules) in the crystal.
  • the hexagonal crystal system refers to the assignment of crystals in which there are hexagonal or hexagonal characteristic symmetry elements in the main axis direction of the c-crystal axis which only has a higher-order axis.
  • the hexagonal crystal system also known as "hexagonal galaxy", belongs to the intermediate crystal family.
  • the crystal orientation refers to the direction of the point array in the spatial lattice (the direction of the straight line connecting any node row in the lattice).
  • the crystal orientation is used to represent certain directions in the crystal, involving the position of atoms in the crystal, the direction of the atomic column, and the orientation of a group of parallel lines with the same direction.
  • a crystal plane refers to a plane passing through any lattice point in the spatial lattice (a plane composed of nodes in the lattice).
  • the crystal plane in the hexagonal system is used to represent the plane of the atoms in the crystal.
  • the crystal orientation of the c-axis is [0001]
  • the crystal orientation of the a1-axis is
  • the crystal orientation of the a2 axis is
  • the crystal orientation of the a3 axis is Also shown in Figure 1 are two crystal planes and
  • the white dots in Figure 1 are silicon Si atoms, and the black dots are carbon C atoms.
  • a semiconductor is a material whose electrical conductivity is between conductors and insulators at room temperature; among them, semiconductors include intrinsic semiconductors and impurity semiconductors.
  • Semiconductors doped with a certain amount of impurities are called impurity semiconductors or extrinsic semiconductors.
  • the impurities doped in the impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons, and the impurity semiconductors doped with impurities that provide electrons (such as 5-valent phosphorus element) are also called electron-type semiconductors or N-type semiconductors.
  • impurity semiconductors that are doped with impurities that provide holes are also called hole type semiconductors or P (positive, positive) type semiconductors), can improve the intrinsic semiconductor Generally speaking, the higher the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity.
  • this type of impurity semiconductor is also called conductive type semiconductor, for example, conductive type SiC , the doped impurities are nitrogen N, boron B, aluminum Al and so on.
  • the impurities doped in the impurity semiconductor can compensate the impurity semiconductor, the donor electrons are just enough to fill the acceptor energy level, but cannot provide electrons and holes in the conduction band and valence band, so that the semiconductor material with a wider band gap has Resistivity similar to that of an insulator.
  • the impurity compensation of SiC is realized by doped transition metal to SiC, thereby improving the resistivity of SiC.
  • This type of impurity semiconductor is also called semi-insulating semiconductor or semi-insulator, or has semi-insulator characteristic.
  • At least one (a) of a, b or c may represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be It can be single or multiple.
  • words such as “first” and “second” do not limit the quantity and order.
  • orientation terms such as “upper” and “lower” are defined relative to the orientation in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, and they are used for relative In the description and clarification of the drawings, it may change correspondingly according to the change of the orientation in which the components are placed in the drawings.
  • the technical solutions of the present application can be applied to electronic devices, which are different types of terminals such as computers, mobile phones, tablet computers, wearable devices, and in-vehicle devices; the electronic devices can also be network devices such as base stations.
  • the electronic equipment may also be a device such as a power amplifier used in the above electronic equipment.
  • the embodiments of the present application do not specifically limit the specific form of the above electronic device.
  • FIG. 2 shows a schematic structural diagram of the terminal 100 .
  • the terminal 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, Mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, sensor module 180, camera 193 and display screen 194, etc.
  • USB universal serial bus
  • the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the terminal 100 .
  • the terminal 100 may include more or less components than shown, or some components may be combined, or some components may be separated, or different component arrangements.
  • the illustrated components may be implemented in hardware, software, or a combination of software and hardware.
  • the processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural-network processing unit (neural-network processing unit, NPU), etc. Wherein, different processing units may be independent devices, or may be integrated in one or more processors.
  • application processor application processor, AP
  • modem processor graphics processor
  • ISP image signal processor
  • controller video codec
  • digital signal processor digital signal processor
  • baseband processor baseband processor
  • neural-network processing unit neural-network processing unit
  • a memory may also be provided in the processor 110 for storing instructions and data.
  • the memory in processor 110 is cache memory. This memory may hold instructions or data that have just been used or recycled by the processor 110 . If processor 110 needs to use the instruction or data again, it can be called directly from the memory. Repeated accesses are avoided and the latency of the processor 110 is reduced, thereby increasing the efficiency of the system.
  • the processor 110 may include one or more interfaces.
  • the interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transceiver (universal asynchronous transmitter) receiver/transmitter, UART) interface, mobile industry processor interface (MIPI), general-purpose input/output (GPIO) interface, subscriber identity module (SIM) interface, and / or universal serial bus (universal serial bus, USB) interface, etc.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • PCM pulse code modulation
  • UART universal asynchronous transceiver
  • MIPI mobile industry processor interface
  • GPIO general-purpose input/output
  • SIM subscriber identity module
  • USB universal serial bus
  • the charging management module 140 is used to receive charging input from the charger.
  • the charger may be a wireless charger or a wired charger.
  • the charging management module 140 may receive charging input from the wired charger through the USB interface 130 .
  • the charging management module 140 may receive wireless charging input through the wireless charging coil of the terminal 100 . While the charging management module 140 charges the battery 142 , it can also supply power to the terminal through the power management module 141 .
  • the power management module 141 is used for connecting the battery 142 , the charging management module 140 and the processor 110 .
  • the power management module 141 receives input from the battery 142 and/or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the display screen 194, the camera 193, and the wireless communication module 160.
  • the power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle times, battery health status (leakage, impedance).
  • the power management module 141 may also be provided in the processor 110 .
  • the power management module 141 and the charging management module 140 may also be provided in the same device.
  • the wireless communication function of the terminal 100 may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modulation and demodulation processor, the baseband processor, and the like.
  • Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals.
  • Each antenna in terminal 100 may be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization.
  • the antenna 1 can be multiplexed as a diversity antenna of the wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.
  • the mobile communication module 150 may provide a wireless communication solution including 2G/3G/4G/5G, etc. applied on the terminal 100 .
  • the mobile communication module 150 may include one or more filters, switches, power amplifiers, low noise amplifiers (LNAs), and the like.
  • the mobile communication module 150 can receive electromagnetic waves from the antenna 1, filter and amplify the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation.
  • the mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and then turn it into an electromagnetic wave for radiation through the antenna 1 .
  • at least part of the functional modules of the mobile communication module 150 may be provided in the processor 110 .
  • at least part of the functional modules of the mobile communication module 150 may be provided in the same device as at least part of the modules of the processor 110 .
  • the modem processor may include a modulator and a demodulator.
  • the modulator is used to modulate the low frequency baseband signal to be sent into a medium and high frequency signal.
  • the demodulator is used to demodulate the received electromagnetic wave signal into a low frequency baseband signal. Then the demodulator transmits the demodulated low-frequency baseband signal to the baseband processor for processing.
  • the low frequency baseband signal is processed by the baseband processor and passed to the application processor.
  • the application processor outputs sound signals through audio devices (not limited to the speaker 170A, the receiver 170B, etc.), or displays images or videos through the display screen 194 .
  • the modem processor may be a stand-alone device. In other embodiments, the modem processor may be independent of the processor 110, and be provided in the same device as the mobile communication module 150 or other functional modules.
  • the wireless communication module 160 can provide applications on the terminal 100 including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field communication technology (near field communication, NFC), infrared technology (infrared, IR) and other wireless communication solutions.
  • WLAN wireless local area networks
  • BT Bluetooth
  • GNSS global navigation satellite system
  • frequency modulation frequency modulation
  • FM near field communication technology
  • NFC near field communication technology
  • IR infrared technology
  • the wireless communication module 160 may be one or more devices integrating one or more communication processing modules.
  • the wireless communication module 160 receives electromagnetic waves via the antenna 2 , frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110 .
  • the wireless communication module 160 can also receive the signal to be sent from the processor 110 , perform frequency modulation on it, amplify it, and convert it into electromagnetic waves for radiation
  • the antenna 1 of the terminal 100 is coupled with the mobile communication module 150, and the antenna 2 is coupled with the wireless communication module 160, so that the terminal 100 can communicate with the network and other devices through wireless communication technology.
  • the wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), broadband Code Division Multiple Access (WCDMA), Time Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC , FM, and/or IR technology, etc.
  • the GNSS may include global positioning system (global positioning system, GPS), global navigation satellite system (global navigation satellite system, GLONASS), Beidou navigation satellite system (beidou navigation satellite system, BDS), quasi-zenith satellite system (quasi -zenith satellite system, QZSS) and/or satellite based augmentation systems (SBAS).
  • global positioning system global positioning system, GPS
  • global navigation satellite system global navigation satellite system, GLONASS
  • Beidou navigation satellite system beidou navigation satellite system, BDS
  • quasi-zenith satellite system quadsi -zenith satellite system, QZSS
  • SBAS satellite based augmentation systems
  • the terminal 100 implements a display function through a GPU, a display screen 194, an application processor, and the like.
  • the GPU is a microprocessor for image processing, and is connected to the display screen 194 and the application processor.
  • the GPU is used to perform mathematical and geometric calculations for graphics rendering.
  • Processor 110 may include one or more GPUs that execute program instructions to generate or alter display information.
  • Display screen 194 is used to display images, videos, and the like.
  • Display screen 194 includes a display panel.
  • the display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (active-matrix organic light).
  • LED organic light-emitting diode
  • AMOLED organic light-emitting diode
  • FLED flexible light-emitting diode
  • Miniled MicroLed, Micro-oLed, quantum dot light-emitting diode (quantum dot light emitting diodes, QLED) and so on.
  • the terminal 100 may include one or N display screens 194 , where N is a positive integer greater than one.
  • the terminal 100 can realize the shooting function through the ISP, the camera 193, the video codec, the GPU, the display screen 194 and the application processor.
  • the ISP is used to process the data fed back by the camera 193 .
  • the shutter is opened, the light is transmitted to the camera photosensitive element through the lens, the light signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to the ISP for processing, and converts it into an image visible to the naked eye.
  • ISP can also perform algorithm optimization on image noise, brightness, and skin tone.
  • ISP can also optimize the exposure, color temperature and other parameters of the shooting scene.
  • the ISP may be provided in the camera 193 .
  • Camera 193 is used to capture still images or video.
  • the object is projected through the lens to generate an optical image onto the photosensitive element.
  • the photosensitive element may be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor.
  • CMOS complementary metal-oxide-semiconductor
  • the photosensitive element converts the optical signal into an electrical signal, and then transmits the electrical signal to the ISP to convert it into a digital image signal.
  • the ISP outputs the digital image signal to the DSP for processing.
  • DSP converts digital image signals into standard RGB, YUV and other formats of image signals.
  • the terminal 100 may include 1 or N cameras 193 , where N is a positive integer greater than 1.
  • the external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the terminal 100.
  • the external memory card communicates with the processor 110 through the external memory interface 120 to realize the data storage function. For example to save files like music, video etc in external memory card.
  • Internal memory 121 may be used to store one or more computer programs including instructions.
  • the processor 110 may execute the above-mentioned instructions stored in the internal memory 121, thereby causing the terminal 100 to execute the methods provided in some embodiments of the present application, as well as various functional applications and data processing.
  • the internal memory 121 may include a storage program area and a storage data area.
  • the stored program area may store the operating system; the stored program area may also store one or more application programs (such as gallery, contacts, etc.) and the like.
  • the storage data area may store data (such as photos, contacts, etc.) created during the use of the electronic device 101 and the like.
  • the internal memory 121 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic disk storage devices, flash memory devices, universal flash storage (UFS), and the like.
  • the processor 110 causes the terminal 100 to execute the methods provided in the embodiments of the present application by executing the instructions stored in the internal memory 121 and/or the instructions stored in the memory provided in the processor, and Various functional applications and data processing.
  • the terminal 100 may implement audio functions through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, an application processor, and the like. Such as music playback, recording, etc.
  • the audio module 170 is used for converting digital audio information into analog audio signal output, and also for converting analog audio input into digital audio signal. Audio module 170 may also be used to encode and decode audio signals. In some embodiments, the audio module 170 may be provided in the processor 110 , or some functional modules of the audio module 170 may be provided in the processor 110 .
  • Speaker 170A also referred to as a "speaker" is used to convert audio electrical signals into sound signals.
  • the terminal 100 can listen to music through the speaker 170A, or listen to a hands-free call.
  • the receiver 170B also referred to as "earpiece" is used to convert audio electrical signals into sound signals.
  • the voice can be answered by placing the receiver 170B close to the human ear.
  • the microphone 170C also called “microphone” or “microphone” is used to convert sound signals into electrical signals.
  • the user can make a sound by approaching the microphone 170C through a human mouth, and input the sound signal into the microphone 170C.
  • the terminal 100 may be provided with one or more microphones 170C.
  • the terminal 100 may be provided with two microphones 170C, which can implement a noise reduction function in addition to collecting sound signals.
  • the terminal 100 may further be provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify sound sources, and implement directional recording functions.
  • the earphone jack 170D is used to connect wired earphones.
  • the earphone interface 170D can be the USB interface 130, or can be a 3.5mm open mobile terminal platform (OMTP) standard interface, a cellular telecommunications industry association of the USA (CTIA) standard interface.
  • OMTP open mobile terminal platform
  • CTIA cellular telecommunications industry association of the USA
  • the sensor module 180 may include a pressure sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.
  • the touch sensor is also referred to as a "touch device”.
  • the touch sensor may be disposed on the display screen 194, and the touch sensor and the display screen 194 form a touch screen, also referred to as a "touch screen”.
  • a touch sensor is used to detect touch operations on or near it.
  • the touch sensor can pass the detected touch operation to the application processor to determine the type of touch event.
  • Visual output associated with touch operations can be provided through the display.
  • the touch panel provided with a touch sensor array formed by a plurality of touch sensors may also be provided on the surface of the display panel in the form of an overhang.
  • the touch sensor may also be located at a different location than the display screen 194 .
  • the form of the touch sensor is not limited in the embodiments of the present application, for example, it may be a device such as a capacitor or a piezoresistor.
  • the above-mentioned terminal 100 may also include one or more components such as buttons, motors, indicators, and a subscriber identification module (subscriber identification module, SIM) card interface, which is not limited in this embodiment of the present application.
  • SIM subscriber identification module
  • the electronic equipment provided by the embodiments of this application takes a 5G base station as an example.
  • the 5G base station can be divided into a baseband unit (baseband unit, BBU)-active antenna unit (active antenna unit, AAU), a centralized unit-distributed unit (central unit) -distribute unit, CU-DU)-AAU, BBU-remote radio unit (RRU)-antenna, CU-DU-RRU-Antenna, integrated 5G base station (5G node base station, gNB) etc. different architectures. Taking the base station of the BBU-RRU architecture as an example, as shown in FIG.
  • the base station includes the BBU21, the RRU22 and the antenna 23; the BBU21 and the RRU22 are connected by optical fibers, and the interface between the two is based on the open CPRI (common public radio interface). Common public radio interface) and OBSAI (open base station architecture initiative open base station architecture).
  • the BBU21 processes the generated baseband signal through the RRU22 and sends it to the antenna 23 for transmission.
  • the RRU 22 includes a digital intermediate frequency module 221 , a transceiver module 222 , a power amplifier 223 (power amplifier, PA) and a filter 224 .
  • the digital intermediate frequency module 221 is used for the modulation and demodulation, digital up-conversion, D/A conversion (digital to analog converter, digital-to-analog conversion) of the baseband signal transmitted by the optical fiber to form the intermediate frequency signal;
  • the transceiver module 222 completes the intermediate frequency signal to the The transformation of the radio frequency signal;
  • the power amplifier 223 is used to power amplify the low power radio frequency signal;
  • the filter 224 is used to filter the radio frequency signal, and then transmit the radio frequency signal through the antenna 23 .
  • the power amplifier provided in the embodiments of the present application can be applied to the power amplifier in the mobile communication module 150 or the wireless communication module 160 in the terminal 100 provided in FIG. 2 , or the power amplifier in the RRU 22 in the base station provided in FIG. 3 .
  • the specific application scenarios are not limited to the terminal shown in FIG. 2 and the base station shown in FIG. 3 . It can be understood that any of the above electronic devices that need to use a power amplifier to amplify signals belong to the application scenarios of the embodiments of the present application.
  • the embodiments of the present application provide a power amplifier including an integrated circuit and a package structure, wherein the integrated circuit is packaged inside the package structure.
  • the integrated circuit may be formed by connecting one or more transistors fabricated on a substrate.
  • the integrated circuit 30 mainly includes a substrate 31 and a transistor 32 covering the substrate 31 .
  • the transistor 32 mainly includes a nucleation layer 321 , a buffer layer 322 , an insertion layer 323 , a barrier layer 324 , and electrodes of the barrier layer 324 , such as a gate electrode 325 , a source electrode 326 and a drain electrode, which are disposed on the substrate 31 .
  • electrode 327; the electrode is covered with a passivation layer 328.
  • the transistor is a high electron mobility transistor (HEMT) as an example.
  • the nucleation layer 321 in the transistor is usually made of aluminum nitride (AlN)
  • the buffer layer 322 is usually made of GaN
  • the insertion layer 323 is usually made of nitride.
  • the barrier layer 324 is usually aluminum gallium nitride (AlGaN)
  • the electrode is usually metal.
  • the source electrode 326 and the drain electrode 327 respectively form conductive ohmic contact with the barrier layer 324 , and the gate electrode 325 and the barrier layer 324 form Schottky contact.
  • the dotted line in the buffer layer 322 represents the two-dimensional electron gas (2DEG) generated in the heterostructure formed by the buffer layer 322 and the barrier layer 324 in the HEMT, and the two-dimensional electron gas is along the horizontal direction (as shown in FIG. 3 ).
  • the mobility is very high and is the basis of HEMT operation.
  • the function of the insertion layer 323 is to improve the density, localization degree and mobility of the two-dimensional electron gas, thereby improving the performance of the device, such as excellent switching performance, etc.; therefore, the insertion layer 323 is an optional structure, in HEMT When the insertion layer 323 is not provided in the device, the performance of the device will be degraded.
  • the nucleation layer 321 is also an optional structure, and its main function is to serve as a transition when the crystal structures of the materials of the buffer layer 322 and the substrate 31 are quite different.
  • a nucleation layer 321 with a smaller crystal structure difference from the substrate 31 may be epitaxially grown on the substrate first, and then the nucleation layer 321 may be epitaxially formed on the substrate.
  • the buffer layer 322 is epitaxially formed.
  • GaN-based HEMTs are usually fabricated by epitaxial growth on high-purity SiC substrates. Because high-purity silicon carbide substrate has high resistance, small lattice mismatch with GaN, and good heat dissipation performance, it is the preferred substrate for GaN epitaxy.
  • High-purity silicon carbide substrates are usually made of high-purity SiC. The formation process of such substrates is mainly based on high-purity SiC powder. Under the temperature condition of 2000 degrees, SiC crystal is obtained by high temperature sublimation, and a high purity growth environment should be maintained during the growth of SiC crystal (need to isolate nitrogen in the air). The SiC crystal is then processed by wire cutting, grinding and polishing to obtain a SiC substrate.
  • High-purity SiC powder is mainly obtained by the reaction of high-purity carbon C powder and high-purity silicon Si powder after purification.
  • the substrate produced in this way is an intrinsic semiconductor (or an intrinsic state semiconductor) with a thickness of 500um ⁇ 25 ⁇ m, the substrate has a relatively high resistivity, usually the resistivity is greater than 1e5 ⁇ cm (ohm ⁇ cm), and the substrate has Relatively high thermal conductivity (at a temperature of 298K, the thermal conductivity is about 390W/cm ⁇ K). It can be seen that the processing technology of high-purity silicon carbide substrates is complex and the conditions are harsh, resulting in very high substrate costs, which in turn leads to high device costs, limiting the wider application of HEMT devices.
  • the substrate 31 of the integrated circuit adopts a composite substrate.
  • the substrate 31 includes: a first material layer 311 and a second material layer 312 covering the first material layer 311 , wherein the transistor 32 is covered on the second material layer 312; the second material layer 312 includes silicon carbide SiC, and the resistivity of the second material layer is different from that of the first material layer.
  • the composite substrate of the integrated circuit is mainly formed by two material layers with different resistivities, wherein the second material layer covers the first material layer, and the second material layer contains silicon carbide SiC capable of making transistors, Since the composite substrate of the integrated circuit is formed by two material layers with different resistivities, the composite substrate can be mass-produced, and the performance adjustment of SiC is also more flexible, and there is greater flexibility in cost control.
  • the second material layer may be bonded to the first material layer, for example, the second material layer is directly bonded to the first material layer, or the second material layer is bonded to the first material layer through an intermediate dielectric layer.
  • the second material layer may also be epitaxially grown on the first material layer. It should be noted that the epitaxial growth process has higher environmental requirements, while the bonding process has lower environmental requirements. Only the SiC crystal obtained by PVT needs to be used, and the slice obtained by cutting the SiC crystal is bonded to the first material layer. Follow-up conventional thinning processing can be performed.
  • the first material layer 311 is an insulating material; or, the first material layer 311 is a conductive material, and when the first material layer 311 is a conductive material, the resistivity of the first material layer 311 is lower than that of the second material layer.
  • the material conductive properties of the first material layer are not limited, so that the material selectivity of the first material layer can be enriched.
  • the material of the first material layer 311 can be at least any one of the following silicon carbide SiC, silicon nitride AlN, aluminum oxide Al 2 O 3 and silicon Si.
  • conductive type SiC may be used.
  • the resistivity of the second material layer 312 is greater than that of the first material layer 311 .
  • the resistivity of the first material layer 311 is less than 0.03 ⁇ cm, and the thickness of the first material layer 311 is greater than 1 ⁇ m.
  • the first material layer 311 can also be AlN or Al 2 O 3 , for example, polymorphic AlN or Al 2 O 3 , and its resistivity is >1e5ohm.cm.
  • the first material layer 311 can also be made of single crystal silicon Si or polycrystalline silicon Si. When single crystal silicon or polycrystalline silicon is used, the resistivity of the first material layer is not limited.
  • the first material layer 311 may also be a material layer with other indicators that do not meet the standards, and specific indicators such as non-uniform resistivity, crystal declination, and quality of micropipes do not meet the standards.
  • the first material layer 311 may be formed using a PVT process.
  • the formation process of the first material layer 311 is mainly to use SiC powder, obtain SiC crystal by high temperature sublimation by PVT method, and then obtain the SiC crystal by cutting.
  • the first material layer 311 is doped with impurities for reducing the resistivity of the first material layer 311 .
  • the manufacturing process of the first material layer 311 has low requirements on the raw materials and environment for crystal growth, for example, the first material layer 311 is doped with a carrier to provide
  • the specific first material layer 311 can use an N-type substrate with relatively low production cost (for example, using nitrogen N element doping), generally, the N-type substrate requires relatively high-purity substrates for raw materials and production processes. Bottom is low.
  • the growth of N-type SiC crystal has no special requirements for the raw materials used, that is, both ordinary SiC powder and high-purity SiC powder are applicable.
  • the formation of the lower resistivity of the N-type SiC crystal is mainly due to the control of the nitrogen composition of the growth system, so that a large amount of nitrogen is successfully injected into the crystal, and a high concentration of shallow donor energy levels is formed in the SiC crystal, thereby providing a large number of freely mobile electrons as Therefore, there are no special requirements for the presence of other low-concentration ( ⁇ 1e18/cm3) impurities in the growth system and raw materials.
  • the first material layer 311 includes at least one crystal type.
  • the first material layer 311 at least includes one or more of the following crystal types: 4H-SiC, 6H-SiC, 3C-SiC (3-cubic, 3-layer carbon-silicon atomic cubic crystal system), 15R-SiC (15 -rhombohedron, a 15-layer carbon-silicon atom rhombic hexahedron).
  • crystal types 4H-SiC, 6H-SiC, 3C-SiC (3-cubic, 3-layer carbon-silicon atomic cubic crystal system), 15R-SiC (15 -rhombohedron, a 15-layer carbon-silicon atom rhombic hexahedron).
  • the second material layer 312 can be obtained by using a SiC crystal obtained by PVT, and further processed from the SiC crystal.
  • the difference is that the second material layer 312 has higher requirements on the manufacturing process, and it is necessary to control the second material layer 312 to mainly contain silicon carbide of one crystal type, and the first crystal type is 4H Or 6H, for example, 4H-SiC (4-hexagonal-SiC, 4-layer carbon-silicon atomic hexagonal system) or 6H-SiC.
  • the reason why the second material layer mainly adopts single crystal 4H or 6H silicon carbide is to facilitate the lattice adaptation of each structural layer of the transistor epitaxially grown on the substrate, such as 4H-SiC or 6H- SiC has a small lattice mismatch with GaN.
  • the impurities of the second material layer 312 are mainly unintentional doping, wherein the concentration of the impurities that provide carriers doped in the second material layer 312 is less than 1e17cm ⁇ -3, and the impurities that provide carriers include at least one of the following Or more nitrogen N, boron B, aluminum AL.
  • the second material layer 312 produced in this way is a high-purity SiC crystal with the properties of a semi-insulator, which can be adapted to the fabrication of transistors.
  • the resistivity of the second material layer 312 is greater than 1e5 ⁇ cm.
  • the second material layer 312 can also be a semi-insulator obtained by doping.
  • the second material layer 312 can also be doped with a transition metal to realize a semi-insulator, so as to improve the resistance of the second material layer. rate; transition metals include transition metal elements such as vanadium V or iron Fe.
  • the transition metal impurity in the SiC crystal can be used as a deep level compensation center, which can compensate for the unintentionally doped nitrogen N and boron B in the SiC crystal, so as to realize the semi-insulating property of the second material layer 312 .
  • the transition metal vanadium V is an ideal deep-level impurity, and the current SiC crystal doped with vanadium V exhibits high resistance characteristics.
  • the principle is that vanadium V can form a deep compensation energy level in the SiC crystal, which is located near the center of the forbidden band, and can be used as a deep main impurity to compensate for nitrogen, or as a deep donor impurity to compensate for boron, which can effectively bind carriers.
  • the role of SiC crystals can show semi-insulating properties at room temperature.
  • the doping concentration of the transition metal in the second material layer 312 is 1e14 cm ⁇ -3 to 1e17 cm ⁇ -3. Such a doping concentration is close to the concentration of impurities such as nitrogen N and boron B unintentionally doped in the SiC crystal, which can effectively compensate for the unintentionally doped nitrogen N and boron B in the SiC crystal.
  • the thickness of the second material layer 312 is greater than 1 ⁇ m, for example, the thickness of the second material layer may be 1 to 100 ⁇ m.
  • the process of further processing the SiC crystal into the second material layer 312 may be one or more methods of wire cutting, ion beam cutting, laser glass, or mechanical thinning.
  • the second material layer 312 is bonded on the second material layer 311, for example, the bonding between the two can be realized by a surface activated bonding (SAB) technology (specifically, low temperature plasma bonding). Therefore, it is not required that the crystal orientation of the second material layer 312 and the SiC crystal in the first material layer 311 be kept in the same direction. As shown in FIG. 6 , the vertical surface of the second material layer 311 adopts the [0001] crystal axis of the SiC crystal, or is close to the [0001] crystal axis, such as the axis [0001] of the SiC unit cell of the second material layer.
  • SAB surface activated bonding
  • the axial off-angle ⁇ is 0 to 4 degrees.
  • the smaller the axial deflection angle the better the lattice adaptation of each material layer, especially GaN, in the transistor.
  • the first material layer in the embodiments of the present application mainly uses materials with different resistivity than the second material layer, for example, polymorphic SiC, silicon Si, AlN or Al 2 O 3 is used in the embodiments of the present application
  • the first material layer is formed, or the first material layer is formed by using impurity-doped conductivity type SiC or silicon Si that can provide carriers, or the first material layer is formed by using a material layer that does not meet the standard;
  • Type SiC forms a second material layer with semi-insulator properties.
  • the substrate of the present application uses a composite of the first material layer and the second material layer.
  • the substrate form can reduce the usage of high-purity eigenstate SiC.
  • the material form of the first material layer determines that the growth process of the first material layer requires relatively high-purity intrinsic state SiC, which will be much lower; In the production process of the first material layer, the requirements for the purity of the SiC powder and the growth environment are relatively low, for example: the first material layer adopts an N-type substrate with relatively low production cost (using nitrogen N element doping) In this way, N-type substrates generally have lower requirements on raw materials and production processes than high-purity substrates. Taking the growth of N-type SiC crystal as an example, the growth of N-type SiC crystal has no special requirements for the raw materials used, that is, both ordinary SiC powder and high-purity SiC powder are applicable.
  • the first material layer may be SiC with polytypes.
  • the first material layer may contain defective single crystal SiC, such as mixed with other crystal types. In this way, when the SiC crystal grows, the difficulty of the process is reduced, and the cost is effectively controlled.
  • an embodiment of the present application provides a method for fabricating an integrated circuit, as shown in FIG. 7 , including the following steps:
  • the second material layer includes silicon carbide SiC, and the resistivity of the second material layer is different from that of the first material layer.
  • the second material layer may be bonded on the first material layer, for example, the second material layer may be directly bonded to the first material layer, or the second material layer may be bonded to the first material layer through an intermediate dielectric layer. on a material layer.
  • the second material layer may also be epitaxially grown on the first material layer by epitaxy. It should be noted that the epitaxial growth process has higher environmental requirements, while the bonding process has lower environmental requirements. It is only necessary to use PVT to obtain high-purity SiC crystals, and the slices obtained by cutting the SiC crystals are bonded to the first material layer. The slices can be subjected to subsequent conventional thinning processing.
  • Step 101 specifically includes:
  • the third material layer includes silicon carbide SiC, and the resistivity of the material of the third material layer is different from that of the first material layer.
  • the third material layer includes SiC of a first crystal type.
  • the first crystal type is 4H, or 6H.
  • the first material layer is an insulating material; or, the first material layer is a conductive material, and when the first material layer is a conductive material, the resistivity of the first material layer is lower than that of the third material layer.
  • the material conductive properties of the first material layer are not limited, so that the material selectivity of the first material layer can be enriched.
  • the material of the first material layer can be at least any of the following SiC, AlN, Al 2 O 3 and Si.
  • the first material layer is a conductive material
  • conductive SiC can be used.
  • the resistivity of the third material layer is greater than that of the first material layer.
  • the resistivity of the first material layer is less than 0.03 ⁇ cm, and the thickness of the first material layer is greater than 1 ⁇ m.
  • the first material layer 311 can also be made of AlN or Al 2 O 3 , for example, polymorphic AlN or Al 2 O 3 , whose resistivity is >1e5ohm.cm.
  • the first material layer can also be made of single crystal silicon or polycrystalline silicon, wherein when single crystal silicon or polycrystalline silicon is used, the resistivity of the first material layer is not limited.
  • the first material layer may also be a material layer with other indicators that do not meet the standards, and specific indicators such as non-uniform resistivity, crystal declination, and quality of micropipes do not meet the standards.
  • the first material layer may be formed using a PVT process.
  • the formation process of the first material layer is mainly to use SiC powder, obtain SiC crystal by high temperature sublimation by PVT method, and then obtain SiC crystal by cutting.
  • the first material layer is doped with impurities for reducing the resistivity of the first material layer. For example, when the resistivity of the first material layer is required to be low, the production process of the first material layer has low requirements on the raw materials and environment for crystal growth.
  • the first material layer is doped with impurities that provide carriers
  • the specific first material layer can be an N-type substrate with relatively low fabrication cost (for example, doped with nitrogen N element), and generally, an N-type substrate has lower requirements on raw materials and production processes than a high-purity substrate.
  • N-type SiC crystal the growth of N-type SiC crystal has no special requirements for the raw materials used, that is, both ordinary SiC powder and high-purity SiC powder are applicable.
  • the formation of the lower resistivity of the N-type SiC crystal is mainly due to the control of the nitrogen composition of the growth system, so that a large amount of nitrogen is successfully injected into the crystal, and a high concentration of shallow donor energy levels is formed in the SiC crystal, thereby providing a large number of freely mobile electrons as Therefore, there are no special requirements for the presence of other low-concentration ( ⁇ 1e18/cm3) impurities in the growth system and raw materials.
  • the first material layer contains at least one crystal form.
  • the first material layer at least includes one or more of the following crystal forms: 4H-SiC, 6H-SiC, 3C-SiC (3-cubic, 3-layer carbon-silicon atomic cubic crystal system), 15R-SiC (15- rhombohedron, a 15-layer carbon-silicon rhombic hexahedron).
  • the number and types of crystal forms contained in the first material layer are not limited, especially when the first material layer contains multiple crystal forms, the requirements for the manufacturing process are reduced, and the cost can be effectively reduced.
  • the third material layer can be obtained by high-temperature sublimation of the PVT method to obtain a high-purity SiC crystal, and then the SiC crystal can be obtained by wire cutting.
  • the specific method can refer to the description of the above-mentioned first material layer, the difference is that the third material layer has higher requirements on the production process, and it is necessary to control the third material layer to mainly contain silicon carbide of one crystal type, and the first crystal type is 4H or 6H, For example, 4H-SiC (4-hexagonal-SiC, 4 layers of carbon and silicon atoms hexagonal) or 6H-SiC.
  • the reason why the third material layer mainly adopts single crystal 4H or 6H silicon carbide is to facilitate the lattice adaptation of each structural layer of the transistor epitaxially grown on the substrate, such as 4H-SiC or 6H- SiC has a small lattice mismatch with GaN.
  • the impurities in the third material layer are mainly unintentional doping, wherein the concentration of the impurities providing carriers doped in the third material layer is less than 1e17cm ⁇ -3, and the impurities providing carriers at least include one or more of the following Item nitrogen N, boron B, aluminum AL.
  • the third material layer 312 fabricated in this way is a high-purity SiC crystal, which has the properties of a semi-insulator, and can be adapted to the fabrication of transistors.
  • the resistivity of the third material layer 312 is greater than 1e5 ⁇ cm.
  • the third material layer can also be a semi-insulator obtained by doping, for example, the third material layer can also be doped with a transition metal to achieve a semi-insulator, so as to improve the resistivity of the third material layer; the transition metal includes vanadium V or iron transition metal elements such as Fe.
  • the transition metal impurity in the SiC crystal can be used as a deep level compensation center, which can compensate for the unintentionally doped nitrogen N and boron B in the SiC crystal to realize the semi-insulating characteristics of the third material layer.
  • the transition metal vanadium V is a As an ideal deep-level impurity, the current V-doped SiC crystal shows high resistance characteristics.
  • the principle is that vanadium V can form a deep compensation energy level in the SiC crystal, which is located near the center of the forbidden band, and can be used as a deep main impurity to compensate for nitrogen, or as a deep donor impurity to compensate for boron, which can effectively bind carriers.
  • the role of SiC crystals can show semi-insulating properties at room temperature.
  • the doping concentration of the transition metal in the third material layer is 1e14cm ⁇ -3 to 1e17cm ⁇ -3, which is close to the unintentional doping concentration of nitrogen N, boron B and other impurities in the SiC crystal, which can effectively reduce the The unintentionally doped nitrogen N and boron B in the SiC crystal are compensated.
  • the thickness of the third material layer 313 is not limited here, and it may be 1 to 100 ⁇ m, or thicker.
  • the third material layer is bonded on the first material layer, for example, the bonding of the two can be realized by surface activated bonding (SAB) technology. Therefore, it is not required that the crystal orientation of the third material layer and the SiC crystal in the first material layer be kept in the same direction.
  • the vertical surface of the third material layer adopts the [0001] crystal axis of the SiC crystal, or is close to the [0001] crystal axis, such as the axis [0001] of the SiC unit cell of the third material layer and perpendicular to the third material layer.
  • the off-angle of the direction of the layers is less than 4° (the axial off-angle ⁇ is 0 to 4 degrees). Among them, the smaller the axial deflection angle, the better the lattice adaptation of each material layer, especially GaN, in the transistor.
  • the nucleation layer 321 , the buffer layer 322 , the insertion layer 323 , and the barrier layer 324 as shown in FIG. 5 are epitaxially grown through the MOCVD process. Then, through a device processing process, electrodes for forming transistors are obtained to form transistors.
  • Embodiments of the present application provide a method for fabricating an integrated circuit, as shown in Figures 8-11, including the following steps:
  • the third material layer 313 includes SiC.
  • the manufacturing process of the third material layer 313 and the first material layer 311 can be referred to the description of the above step 101 and will not be repeated.
  • a pre-cut layer may be formed inside the third material layer 313 by means of laser cutting (wherein the thickness of laser cutting is 10-100um) or ion cutting (wherein the thickness of ion-cutting is 1-5um) 314 , as shown in FIG. 9 , a pre-cut layer 314 may be formed inside the third material layer 313 by controlling the depth of ion implantation.
  • the third material layer can be bonded on the first material layer 311 mainly through surface activated bonding SAB technology (specifically, low temperature plasma bonding).
  • step 203 the cutting and peeling of the third material layer other than the pre-cut layer can be achieved by heating at a high temperature, so that a part of the third material layer 313 (ie the pre-cut layer 314 or the second The material layer 312) is left on the first material layer 311 with a thickness of 1-100um, and the other part can be reused.
  • the nucleation layer 321 , the buffer layer 322 , the insertion layer 323 , and the barrier layer 324 are epitaxially formed by the MOCVD process. Then, through a device processing process, electrodes for forming transistors are obtained to form transistors.
  • the method further includes thinning the back surface of the first material layer 311 , for example, performing one or more of grinding and polishing on the surface of the first material layer 311 away from the second material layer 312 . , in order to thin or remove the first material layer 311 , for example, thin the first material layer 311 from 500um to 100um to meet the requirements for the overall thickness of the device or heat dissipation.
  • backside processing is performed on the surface of the first material layer 311 away from the second material layer 312 (as shown in FIG. 12 ), for example A via hole is formed, an insulating layer is deposited on the surface of the via hole, and a backside electrode 33 connected to the source electrode 326 is formed, so as to facilitate the backside installation of the device.
  • the packaging structure specifically includes: a heat dissipation substrate 41, wherein in order to improve the heat dissipation substrate 41, the heat dissipation substrate 41 can be made of composite materials, such as a laminated structure formed by Cu/Mo/Cu; the heat dissipation substrate 41 is bonded to the heat dissipation substrate 41 by sintering silver, and the integrated circuit, the source 326 of the transistor 32 of the integrated circuit is connected to the heat dissipation substrate 41 through the back electrode 33; in addition, the drain 328 and the gate 325 are respectively connected to the pins through gold wire wire bonding, and the pins are arranged on the insulating layer On (for example, insulating ceramics), the insulating layer is bonded to the heat dissipation substrate 41 by an insulating adhesive.
  • the insulating layer is bonded to the heat dissipation substrate 41 by an insulating adhesive.
  • the package structure includes a package package 42, the package package 42 is bonded to the heat dissipation substrate 41 by an insulating adhesive, and one end of the pin is exposed from the package structure and connected to other circuits, wherein the integrated circuit 30 is arranged in the package package 42. in the space surrounded by the heat dissipation substrate 41 .
  • step 301 reference may be made to the production process of step 201, and details are not repeated here.
  • Thinning includes one or more of grinding and polishing.
  • steps 301-302 do not use cutting and peeling processes, but directly thin the front substrate on the bonded third material layer 313, so that a relatively flat second material can be directly obtained.
  • the thickness of the second material layer can be arbitrarily controlled, and any thickness from 5-350um can be achieved without being limited by the ion cutting and laser cutting processes (usually ion cutting can generally obtain a thickness of 1 -5um material layer, laser cutting can achieve 10-100um thickness cutting).
  • the thinning of the front substrate may specifically be to use a grinding process to remove the thickness of 10-50um for the third material layer 313, and then the surface of the third material layer 313 away from the first material layer 311 is subjected to chemical mechanical polishing (chemical mechanical polishing CMP), CMP mainly
  • CMP chemical mechanical polishing mainly
  • the purpose is to obtain a surface with relatively low roughness, such as roughness ⁇ 0.5nm.
  • the nucleation layer 321 , the buffer layer 322 , the insertion layer 323 , and the barrier layer 324 are epitaxially formed by the MOCVD process. Then, through a device processing process, electrodes for forming transistors are obtained to form transistors. In an example, it also includes backside thinning and backside processing on the first material layer 311 .
  • the electrical and thermal properties of the HEMT device formed by the composite substrate bonded with the first material layer with a thickness of 80 ⁇ m were simulated; in scheme 4, the electrical and thermal properties of the HEMT device formed by the second material layer with a thickness of 100 ⁇ m as the substrate were simulated. Thermal properties were simulated.
  • Figure 16 shows the four schemes of the HEMT when the gate voltage Vg (gate voltage) is 0V, -1V, -2V or -3V, respectively, the drain current (drain current, Id (Ampere A)) - drain voltage ( drain voltage, Vd (volt V)) curve, among which, the curves of scheme 2, scheme 3 and scheme 4 are relatively close at a fixed gate voltage, and the curve of scheme 1 at a fixed gate voltage is quite different from the curves of other schemes.
  • the material of the substrate has a great influence on the electrical performance Id-Vd of the HEMT, while the thickness of the second material layer has little effect on the electrical performance Id-Vd of the HEMT.
  • FIG. 17 shows drain current (Id (Ampere A)) versus gate voltage Vg (gate voltage) curves of the HEMTs of the four schemes.
  • Id Ampere A
  • Vg gate voltage
  • the thickness of the bonded second material layer has little effect on the electrical properties of the HEMT.
  • Figure 18 provides the effect of scheme 1, scheme 4 and composite substrate (with different thicknesses of the second material layer) on the peak junction (PN junction) temperature of the HEMT device (the power of a single HEMT is 5W).
  • the peak junction temperature of the HEMT gradually decreases.
  • the peak junction temperature of the HEMT is 231.25 degrees (dotted line), and the substrates are all used
  • the peak junction temperature of the HEMT is 249.45 degrees (solid line), mainly because the thermal conductivity of the first material layer is lower than that of the second material layer.
  • the peak junction temperature of the HEMT is increased by 10.74 degrees.
  • the peak junction temperature of the HEMT only increases by 2.15 degrees.
  • a non-transitory computer-readable storage medium for use with a computer having software for designing integrated circuits, the computer-readable storage medium having stored thereon one or more Computer-readable data structures, a process facility using one or more of the computer-readable data structures described above to manufacture the integrated circuits provided above.

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Abstract

本申请的实施例提供一种集成电路、功率放大器及电子设备，涉及半导体技术领域，实现了一种基于新型复合衬底的集成电路，有效控制了成本。该衬底用于晶体管，包括衬底，其中衬底上覆盖有晶体管，衬底包括：第一材料层以及覆盖于第一材料层上的第二材料层，其中，晶体管覆盖在第二材料层上；第二材料层包含碳化硅SiC，第二材料层与第一材料层的材料的电阻率不同。

Description

一种集成电路、功率放大器及电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种集成电路、功率放大器及电子设备。
背景技术
高电子迁移率晶体管(high-electron-mobility transistor，HEMT)主要用于电子设备中的功率放大器。例如，在电子设备的射频调制电路中所产生的射频信号功率很小，需要经过一系列的放大，获得足够的射频功率以后，才能馈送到天线上辐射出去。为了获得足够大的射频功率，必须采用射频功率放大器对射频信号进行功率放大。射频功率放大器在雷达、无线通信、导航、卫星通讯、电子对抗等系统的设备中有着广泛的应用，是现代无线通信的关键器件。
尤其在第五代移动通信技术5G(generation of wireless communications technologies，5G)时代，基于氮化镓(GaN)的HEMT以高性能特点具有广泛应用的前景。但是昂贵的成本使得基于GaN在商用中面临巨大挑战。
发明内容
本申请提供一种集成电路、功率放大器及电子设备,实现了一种基于新型复合衬底，有效提升了设计的灵活性，在成本管控上有更大的灵活度。
第一方面，提供一种集成电路。该集成电路，包括衬底，其中衬底上覆盖有晶体管，衬底包括：第一材料层以及覆盖于第一材料层上的第二材料层，其中，晶体管覆盖在第二材料层上；第二材料层包含碳化硅SiC，第二材料层与第一材料层的材料的电阻率不同。在该方案中，主要通过不同电阻率的两个材料层形成集成电路的复合衬底，其中第二材料层覆盖于第一材料层上，并且第二材料层包含碳化硅SiC，由于通过不同电阻率的两个材料层形成集成电路的复合衬底使得复合衬底实现可量产化，并且SiC性能调节也更加灵活，在成本管控上有更大的灵活度。
在一种可能的实现方式中，碳化硅包括可以使用单一晶型的碳化硅，例如第二材料层包含第一晶型的碳化硅，第一晶型可以选用4H或6H。采用单一晶型4H或6H的碳化硅的原因是有利于在衬底上外延生成的晶体管的各结构层的晶格适配，例如4H-SiC或6H-SiC与GaN具有较小的晶格失配。
在一种可能的实现方式中，第二材料层键合于第一材料层上。例如第二材料层是直接键合于第一材料层上，或者第二材料层通过中间介质层键合于第一材料层上。在一些示例中，第二材料层也可以通过外延生长于第一材料层上。需要说明的是，外延生长的工艺对环境要求较高，而键合工艺环境要求较低，只需要采用物理气相传输法(physical vapor transport process，PVT)工艺得到SiC晶体，由SiC晶体切割得到的切片与第一材料层键合后对切片进行后续常规的减薄加工即可。
在一种可能的实现方式中，第一材料层为绝缘材料；或者，第一材料层为导电材料，第一材料层的电阻率小于第二材料层的电阻率。本申请的实施例中第一材料层的材料的导电特性不做限制，这样可以丰富第一材料层的材料的选择性。具体的，第一材料层的材料至少可以采用以下任一碳化硅SiC、氮化铝AlN、氧化铝Al 2O 3及硅Si。例 如，第一材料层为导电材料时，可以采用导电型的SiC。则，第二材料层的电阻率大于第一材料层的电阻率，第一材料层的电阻率小于0.03Ω·cm。第一材料层也可以采用AlN或Al 2O 3，例如采用多晶型的AlN或Al 2O 3，其电阻率>1e5ohm.cm。第一材料层也可以采用单晶硅或多晶硅，其中采用单晶硅或多晶硅时，对第一材料层的电阻率不做限定。第一材料层还可以是其他指标不达标的材料层，具体指标例如：电阻率不均匀、晶体偏角、微管等质量不达标。
在一种可能的实现方式中，第二材料层的SiC的晶胞的轴向[0001]与垂直于第二材料层的方向的偏角小于4°。例如第二材料层311垂直表面采用SiC晶体的[0001]晶体轴向，或者是接近于[0001]晶体轴向，即轴向偏角α为0到4度。其中，轴向偏转角度越小越有利于晶体管中各个材料层尤其是GaN的晶格适配。
在一种可能的实现方式中，第一材料层包含至少一种晶型。例如：至少包括以下晶型的碳化硅中的一种或多种：4H-SiC，6H-SiC，3C-SiC(3-cubic，3层碳硅原子立方晶系)，15R-SiC(15-rhombohedron，15层碳硅原子菱形六面体)。这样，对于第一材料层包含的晶型的数量和种类不做限定，尤其第一材料层包含多种晶型时，对制作工艺要求降低，能够有效降低成本。
在一种可能的实现方式中，第一材料层掺杂有降低第一材料层的电阻率的杂质，第二材料层掺杂有提高第二材料层的电阻率的杂质。例如：第一材料层掺杂有提供载流子的杂质，用于降低第一材料层的电阻率。具体的第一材料层可以采用制作成本相对较低的N型衬底(例如，采用氮N元素掺杂)，通常N型衬底对原料和生产工艺的要求相对高纯度的衬底较低。以N型SiC晶体的生长为例，N型SiC晶体的生长对所用原料没有特别要求，即普通SiC粉以及高纯的SiC粉均可适用。N型SiC晶体较低的电阻率的形成主要在于对生长体系氮气成分的控制，使大量氮成功注入晶体，在SiC晶体中形成高浓度的浅施主能级，从而提供大量可自由移动的电子作为载流子，因此对生长体系以及原料中存在其他较低浓度(<1e18/cm3)杂质没有特别要求。第二材料层采用过渡金属掺杂，用于提升第二材料层的电阻率。过渡金属包括钒V或铁Fe等过渡金属元素。具体的，第二材料层主要采用第一晶型的SiC时，SiC晶体中过渡金属杂质能作为深能级补偿中心,可以把SiC晶体中非故意掺杂的氮N、硼B补偿掉，实现第二材料层的半绝缘特性。其中，过渡金属钒V是一种理想的深能级杂质，目前掺钒V的SiC晶体显示出了高阻特性。其原理为，钒V在SiC晶体中可以形成深补偿能级，位于禁带中央附近，可作为深受主杂质补偿氮，或作为深施主杂质补偿硼，能够起到很好地束缚载流子的作用，使SiC晶体在室温下即可显示半绝缘特性。
在一种可能的实现方式中，第二材料层中过渡金属的掺杂浓度为1e14cm^-3至1e17cm^-3。这样的掺杂浓度与SiC晶体中非故意掺杂的氮N、硼B等杂质的浓度接近，能够有效把SiC晶体中非故意掺杂的氮N、硼B补偿掉。
在一种可能的实现方式中，第二材料层的电阻率大于1e5Ω·cm。这样，第二材料层具有较高的电阻率，第二材料层呈现半绝缘体特性有利于晶体管的制作。
在一种可能的实现方式中，第二材料层掺杂的提供载流子的杂质的浓度小于1e17cm^-3，提供载流子的杂质至少包括以下一项或多项氮N、硼B、铝AL。第二材料层的杂质主要为非故意掺杂，其中第二材料层掺杂的提供载流子的杂质的浓度小于 1e17cm^-3，提供载流子的杂质至少包括以下一项或多项氮N、硼B、铝AL。这样制作的第二材料层为高纯度的SiC晶体，具有半绝缘体的特性，能够适应晶体管的制作。
在一种可能的实现方式中，为降低高纯度的碳化硅的使用量，第二材料层的厚度大于1μm，例如，第二材料层的厚度为1到100μm。
第二方面，一种集成电路的制作方法，该制作方法包括：在第一材料层上制作第二材料层，所述第二材料层包含碳化硅SiC，所述第二材料层与第一材料层的材料的电阻率不同；在所述第二材料层上制作晶体管。
在一种可能的实现方式中，在第一材料层上制作第二材料层包括：在第一材料层上键合第三材料层，所述第三材料层包含碳化硅SiC，所述第三材料层与第一材料层的材料的电阻率不同；对所述第三材料层进行减薄处理形成第二材料层。
在一种可能的实现方式中，所述在第一材料层上键合第三材料层之前，包括：对所述第三材料层进行切割处理，形成与所述第一材料层接触的预切割层；在第一材料层上键合第三材料层；包括：在第一材料层上键合第三材料层，其中所述预切割层与所述第一材料层接触；所述对所述第三材料层进行减薄处理形成第二材料层，包括：将所述第三材料层中除所述预切割层以外的部分剥离。
在一种可能的实现方式中，对所述第三材料层进行减薄处理形成第二材料层，包括：对所述第三材料层远离所述第一材料层的表面进行减薄加工，形成第二材料层。
在一种可能的实现方式中，所述减薄加工至少包括一下一种或多种：研磨加工以及抛光加工。
第三方面，提供一种功率放大器，包括集成电路以及封装结构，其中所述集成电路封装于所述封装结构内部。
第四方面，提供一种电子设备，包括功率放大器及天线，所述功率放大器用于将射频信号放大后输出至所述天线向外辐射，所述功率放大器包括上述的功率放大器。
第五方面，提供一种与计算机一起使用的非瞬时性计算机可读存储介质，该计算机具有用于设计集成电路的软件，该计算机可读存储介质上存储有一个或多个计算机可读数据结构，工艺设备使用上述一个或多个计算机可读数据结构制造上文所提供的集成电路。
其中，第二方面至第五方面中任一种可能的实现方式所带来的技术效果可参见上述第一方面中不同实现方式所带来的技术效果，此处不再赘述。
附图说明
图1为本申请的实施例提供的一种六方晶系的结构示意图；
图2为本申请的实施例提供的一种终端的结构示意图；
图3为本申请的实施例提供的一种基站的结构示意图；
图4为本申请的实施例提供的一种集成电路的结构示意图；
图5为本申请的实施例提供的一种衬底的结构示意图；
图6为本申请的另一实施例提供的一种衬底的结构示意图；
图7为本申请的实施例提供的一种集成电路的制作方法的流程示意图；
图8为本申请的实施例提供的一种集成电路的制作过程中的结构示意图一；
图9为本申请的实施例提供的一种集成电路的制作过程中的结构示意图二；
图10为本申请的实施例提供的一种集成电路的制作过程中的结构示意图三；
图11为本申请的实施例提供的一种集成电路的制作过程中的结构示意图四；
图12为本申请的另一实施例提供的一种集成电路的结构示意图；
图13为本申请的实施例提供的一种功率放大器的结构示意图；
图14为本申请的实施例提供的一种集成电路的制作过程中的结构示意图五；
图15为本申请的实施例提供的一种集成电路的制作过程中的结构示意图六；
图16为本申请的实施例提供的一种HEMT的电学性能仿真示意图；
图17为本申请的另一实施例提供的一种HEMT的电学性能仿真示意图；
图18为本申请的实施例提供的一种HEMT的热学性能仿真示意图；
图19为本申请的另实施例提供的一种HEMT的热学性能仿真示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下对本申请的实施例中的技术术语说明如下：
晶型，指晶体结构即晶体的微观结构，是指晶体中实际质点(原子、离子或分子)的具体排列情况。本申请的实施例中六方(hexagonal)晶系，是指在唯一具有高次轴的c晶轴主轴方向存在六重轴或六重反轴特征对称元素的晶体归属。六方晶系也称作“六角星系”，属于中级晶族。如图1所示，在六方晶系中通常采用a1、a2、a3以及c四个晶轴标定晶面指数和晶向指数，以反映六方晶系原子的晶向和晶面。其中，晶向指空间点阵中个点阵列的方向(连接点阵中任意节点列的直线方向)。在六方晶系中晶向用于表示晶体中的某些方向，涉及晶体中原子的位置、原子列方向，标识一组相互平行、方向一致的直线的指向。晶面指通过空间点阵中任意阵点的平面(在点阵中由节点构成的平面)。六方晶系中晶面用于表示晶体中原子构成的平面。例如在图1中以SiC的六方晶系结构为例，c轴的晶向为[0001]，a1轴的晶向为
Figure PCTCN2020142258-appb-000001
a2轴的晶向为
Figure PCTCN2020142258-appb-000002
a3轴的晶向为
Figure PCTCN2020142258-appb-000003
图1中还示出了两个晶面
Figure PCTCN2020142258-appb-000004
及
Figure PCTCN2020142258-appb-000005
其中图1中白点为硅Si原子，黑点为碳C原子。
半导体：半导体是一种常温下导电性能介于导体与绝缘体之间的材料；其中，半导体包括本征半导体和杂质半导体。不含杂质和缺陷的纯净半导体，其内部电子和空穴浓度相等，称为本征半导体。掺入一定量杂质的半导体称为杂质半导体或非本征半导体。其中，杂质半导体中掺入的杂质能够提供一定浓度的载流子(如空穴或电子，其中掺杂提供电子的杂质(如5价的磷元素)的杂质半导体也称作电子型半导体或N(negative，负)型半导体，掺杂提供空穴的杂质(如3价的硼元素)的杂质半导体也称作空穴型半导体或P(positive，正)型半导体)时，能够改善本征半导体的导电性，通常载流子浓度越大，半导体的电阻率越低，导电性也越好，在本申请的实施例中，这一类杂质半导体也称为导电型半导体，例如，导电型SiC，掺杂的杂质为氮N、硼B、铝Al等。此外，杂质半导体中掺入的杂质能够对杂质半导体进行杂质补偿时，施主电子刚好够填充受主能级，但是不能向导带和价带提供电子和空穴，使禁带较宽的半导体材料具有与绝缘体相近的电阻率。例如，在本申请的实施例中，对SiC掺杂过渡金属实现对SiC的杂质补偿，从而提高SiC的电阻率，这一类杂质半导体也称为 半绝缘型半导体或半绝缘体，或者具有半绝缘体特性。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
此外，本申请中，“上”、“下”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请的技术方案可以应用于电子设备，该电子设备该电子设备为计算机、手机、平板电脑、可穿戴设备和车载设备等不同类型的终端；该电子设备还可以为基站等网络设备。电子设备也可以是用于上述电子设备中的功率放大器等装置。本申请实施例对上述电子设备的具体形式不做特殊限制。
图2示出了终端100的结构示意图。终端100可以包括处理器110，外部存储器接口120，内部存储器121，通用串行总线(universal serial bus，USB)接口130，充电管理模块140，电源管理模块141，电池142，天线1，天线2，移动通信模块150，无线通信模块160，音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，传感器模块180，摄像头193以及显示屏194等。
可以理解的是，本发明实施例示意的结构并不构成对终端100的具体限定。在本申请另一些实施例中，终端100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
处理器110可以包括一个或多个处理单元，例如：处理器110可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
处理器110中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器110中的存储器为高速缓冲存储器。该存储器可以保存处理器110刚用过或循环使用的指令或数据。如果处理器110需要再次使用该指令或数据，可从所述存储器中直 接调用。避免了重复存取，减少了处理器110的等待时间，因而提高了系统的效率。
在一些实施例中，处理器110可以包括一个或多个接口。接口可以包括集成电路(inter-integrated circuit，I2C)接口，集成电路内置音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口，用户标识模块(subscriber identity module，SIM)接口，和/或通用串行总线(universal serial bus，USB)接口等。
充电管理模块140用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器。在一些有线充电的实施例中，充电管理模块140可以通过USB接口130接收有线充电器的充电输入。在一些无线充电的实施例中，充电管理模块140可以通过终端100的无线充电线圈接收无线充电输入。充电管理模块140为电池142充电的同时，还可以通过电源管理模块141为终端供电。
电源管理模块141用于连接电池142，充电管理模块140与处理器110。电源管理模块141接收电池142和/或充电管理模块140的输入，为处理器110，内部存储器121，显示屏194，摄像头193，和无线通信模块160等供电。电源管理模块141还可以用于监测电池容量，电池循环次数，电池健康状态(漏电，阻抗)等参数。在其他一些实施例中，电源管理模块141也可以设置于处理器110中。在另一些实施例中，电源管理模块141和充电管理模块140也可以设置于同一个器件中。
终端100的无线通信功能可以通过天线1，天线2，移动通信模块150，无线通信模块160，调制解调处理器以及基带处理器等实现。
天线1和天线2用于发射和接收电磁波信号。终端100中的每个天线可用于覆盖单个或多个通信频带。不同的天线还可以复用，以提高天线的利用率。例如：可以将天线1复用为无线局域网的分集天线。在另外一些实施例中，天线可以和调谐开关结合使用。
移动通信模块150可以提供应用在终端100上的包括2G/3G/4G/5G等无线通信的解决方案。移动通信模块150可以包括一个或多个滤波器，开关，功率放大器，低噪声放大器(low noise amplifier，LNA)等。移动通信模块150可以由天线1接收电磁波，并对接收的电磁波进行滤波，放大等处理，传送至调制解调处理器进行解调。移动通信模块150还可以对经调制解调处理器调制后的信号放大，经天线1转为电磁波辐射出去。在一些实施例中，移动通信模块150的至少部分功能模块可以被设置于处理器110中。在一些实施例中，移动通信模块150的至少部分功能模块可以与处理器110的至少部分模块被设置在同一个器件中。
调制解调处理器可以包括调制器和解调器。其中，调制器用于将待发送的低频基带信号调制成中高频信号。解调器用于将接收的电磁波信号解调为低频基带信号。随后解调器将解调得到的低频基带信号传送至基带处理器处理。低频基带信号经基带处理器处理后，被传递给应用处理器。应用处理器通过音频设备(不限于扬声器170A，受话器170B等)输出声音信号，或通过显示屏194显示图像或视频。在一些实施例中，调制解调处理器可以是独立的器件。在另一些实施例中，调制解调处理器可以独立于 处理器110，与移动通信模块150或其他功能模块设置在同一个器件中。
无线通信模块160可以提供应用在终端100上的包括无线局域网(wireless local area networks，WLAN)(如无线保真(wireless fidelity，Wi-Fi)网络)，蓝牙(Bluetooth，BT)，全球导航卫星系统(global navigation satellite system，GNSS)，调频(frequency modulation，FM)，近距离无线通信技术(near field communication，NFC)，红外技术(infrared，IR)等无线通信的解决方案。无线通信模块160可以是集成一个或多个通信处理模块的一个或多个器件。无线通信模块160经由天线2接收电磁波，将电磁波信号调频以及滤波处理，将处理后的信号发送到处理器110。无线通信模块160还可以从处理器110接收待发送的信号，对其进行调频，放大，经天线2转为电磁波辐射出去。
在一些实施例中，终端100的天线1和移动通信模块150耦合，天线2和无线通信模块160耦合，使得终端100可以通过无线通信技术与网络以及其他设备通信。所述无线通信技术可以包括全球移动通讯系统(global system for mobile communications，GSM)，通用分组无线服务(general packet radio service，GPRS)，码分多址接入(code division multiple access，CDMA)，宽带码分多址(wideband code division multiple access，WCDMA)，时分码分多址(time-division code division multiple access，TD-SCDMA)，长期演进(long term evolution，LTE)，BT，GNSS，WLAN，NFC，FM，和/或IR技术等。所述GNSS可以包括全球卫星定位系统(global positioning system，GPS)，全球导航卫星系统(global navigation satellite system，GLONASS)，北斗卫星导航系统(beidou navigation satellite system，BDS)，准天顶卫星系统(quasi-zenith satellite system，QZSS)和/或星基增强系统(satellite based augmentation systems，SBAS)。
终端100通过GPU，显示屏194，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏194和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。处理器110可包括一个或多个GPU，其执行程序指令以生成或改变显示信息。
显示屏194用于显示图像，视频等。显示屏194包括显示面板。显示面板可以采用液晶显示屏(liquid crystal display，LCD)，有机发光二极管(organic light-emitting diode，OLED)，有源矩阵有机发光二极体或主动矩阵有机发光二极体(active-matrix organic light emitting diode的，AMOLED)，柔性发光二极管(flex light-emitting diode，FLED)，Miniled，MicroLed，Micro-oLed，量子点发光二极管(quantum dot light emitting diodes，QLED)等。在一些实施例中，终端100可以包括1个或N个显示屏194，N为大于1的正整数。终端100可以通过ISP，摄像头193，视频编解码器，GPU，显示屏194以及应用处理器等实现拍摄功能。
ISP用于处理摄像头193反馈的数据。例如，拍照时，打开快门，光线通过镜头被传递到摄像头感光元件上，光信号转换为电信号，摄像头感光元件将所述电信号传递给ISP处理，转化为肉眼可见的图像。ISP还可以对图像的噪点，亮度，肤色进行算法优化。ISP还可以对拍摄场景的曝光，色温等参数优化。在一些实施例中，ISP可以设置在摄像头193中。
摄像头193用于捕获静态图像或视频。物体通过镜头生成光学图像投射到感光元件。感光元件可以是电荷耦合器件(charge coupled device，CCD)或互补金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)光电晶体管。感光元件把光信号转换成电信号，之后将电信号传递给ISP转换成数字图像信号。ISP将数字图像信号输出到DSP加工处理。DSP将数字图像信号转换成标准的RGB，YUV等格式的图像信号。在一些实施例中，终端100可以包括1个或N个摄像头193，N为大于1的正整数。
外部存储器接口120可以用于连接外部存储卡，例如Micro SD卡，实现扩展终端100的存储能力。外部存储卡通过外部存储器接口120与处理器110通信，实现数据存储功能。例如将音乐，视频等文件保存在外部存储卡中。
内部存储器121可以用于存储一个或多个计算机程序，该一个或多个计算机程序包括指令。处理器110可以通过运行存储在内部存储器121的上述指令，从而使得终端100执行本申请一些实施例中所提供的方法，以及各种功能应用和数据处理等。内部存储器121可以包括存储程序区和存储数据区。其中，存储程序区可存储操作系统；该存储程序区还可以存储一个或多个应用程序(比如图库、联系人等)等。存储数据区可存储电子设备101使用过程中所创建的数据(比如照片，联系人等)等。此外，内部存储器121可以包括高速随机存取存储器，还可以包括非易失性存储器，例如一个或多个磁盘存储器件，闪存器件，通用闪存存储器(universal flash storage，UFS)等。在另一些实施例中，处理器110通过运行存储在内部存储器121的指令，和/或存储在设置于处理器中的存储器的指令，来使得终端100执行本申请实施例中提供的方法，以及各种功能应用和数据处理。
终端100可以通过音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，以及应用处理器等实现音频功能。例如音乐播放，录音等。
音频模块170用于将数字音频信息转换成模拟音频信号输出，也用于将模拟音频输入转换为数字音频信号。音频模块170还可以用于对音频信号编码和解码。在一些实施例中，音频模块170可以设置于处理器110中，或将音频模块170的部分功能模块设置于处理器110中。
扬声器170A，也称“喇叭”，用于将音频电信号转换为声音信号。终端100可以通过扬声器170A收听音乐，或收听免提通话。
受话器170B，也称“听筒”，用于将音频电信号转换成声音信号。当终端100接听电话或语音信息时，可以通过将受话器170B靠近人耳接听语音。
麦克风170C，也称“话筒”，“传声器”，用于将声音信号转换为电信号。当拨打电话或发送语音信息时，用户可以通过人嘴靠近麦克风170C发声，将声音信号输入到麦克风170C。终端100可以设置一个或多个麦克风170C。在另一些实施例中，终端100可以设置两个麦克风170C，除了采集声音信号，还可以实现降噪功能。在另一些实施例中，终端100还可以设置三个，四个或更多麦克风170C，实现采集声音信号，降噪，还可以识别声音来源，实现定向录音功能等。
耳机接口170D用于连接有线耳机。耳机接口170D可以是USB接口130，也可以是3.5mm的开放移动电子设备平台(open mobile terminal platform，OMTP)标准接口， 美国蜂窝电信工业协会(cellular telecommunications industry association of the USA，CTIA)标准接口。
传感器模块180可以包括压力传感器，陀螺仪传感器，气压传感器，磁传感器，加速度传感器，距离传感器，接近光传感器，指纹传感器，温度传感器，触摸传感器，环境光传感器，骨传导传感器等。
在本申请的实施例中，触摸传感器，也称“触控器件”。触摸传感器可以设置于显示屏194，由触摸传感器与显示屏194组成触摸屏，也称“触控屏”。触摸传感器用于检测作用于其上或附近的触摸操作。触摸传感器可以将检测到的触摸操作传递给应用处理器，以确定触摸事件类型。可以通过显示屏提供与触摸操作相关的视觉输出。在另一些实施例中，也可以设置有多个触摸传感器形成的触控传感器阵列的触控面板以外挂形式设置于显示面板的表面。在另一些实施例中，触摸传感器也可以与显示屏194所处的位置不同。本申请的实施例中对触控传感器的形式不做限定，例如可以是电容、或压敏电阻等器件。
另外，上述终端100中还可以包括按键、马达、指示器以及用户标识模块(subscriber identification module，SIM)卡接口等一种或多种部件，本申请实施例对此不做任何限制。
本申请的实施例提供的电子设备以5G基站为例，5G基站可分为基带处理单元(baseband unit，BBU)-有源天线单元(active antenna unit，AAU)、集中单元-分布单元(central unit-distribute unit，CU-DU)-AAU、BBU-射频拉远单元(remote radio unit，RRU)-天线(antenna)、CU-DU-RRU-Antenna、一体化5G基站(5G node base station，gNB)等不同的架构。以BBU-RRU架构的基站为例，参照图3所示，基站：包括BBU21、RRU22和天线23；其中BBU21与RRU22通过光纤连接，两者之间的接口是基于开放式CPRI(common public radio interface通用公共射频接口)及OBSAI(open base station architecture initiative开放式基站架构)。其中，BBU21将生成的基带信号通过RRU22处理后发送至天线23进行发射。RRU22包括数字中频模块221、收发信机模块222、功率放大器223(power amplifier，PA)以及滤波器224。其中，数字中频模块221用于光纤传输的基带信号的调制解调、数字上下变频、D/A转换(digital to analog converter，数字模拟转换)等形成中频信号；收发信机模块222完成中频信号到射频信号的变换；功率放大器223用于将小功率的射频信号进行功率放大；滤波器224用于对射频信号进行滤波，然后将射频信号通过天线23发射出去。
当然本申请的实施例提供的功率放大器可以应用于图2提供的终端100中移动通信模块150或无线通信模块160中的功率放大器，或者上述图3提供的基站中RRU22中的功率放大器。当然具体应用场景不限于上述图2示出的终端、图3示出的基站，可以理解的是，任意需要使用功率放大器对信号进行放大的上述电子设备均属于本申请的实施例的应用场景。
其中，本申请的实施例提供一种功率放大器，包括集成电路以及封装结构，其中集成电路封装于封装结构内部。其中该集成电路可以是在衬底上制作的一个或多个晶体管连接形成。如图4所示，集成电路30主要包括衬底31以及覆盖于衬底31上的晶 体管32。其中，晶体管32主要包括设置于衬底31上的成核层321、缓冲层322、插入层323、势垒层324、以及势垒层324的电极，如：栅极325、源极326和漏极327；电极上覆盖有钝化层328。其中，晶体管以高电子迁移率晶体管(high electron mobility transistor，HEMT)为例，晶体管中的成核层321通常采用氮化铝(AlN)，缓冲层322通常采用GaN，插入层323通常采用氮化铝(AlN)，势垒层324通常采用铝镓氮(AlGaN)，电极通常采用金属。其中，源极326和漏极327分别与势垒层324形成导电欧姆接触，栅极325与势垒层324形成肖特基接触。缓冲层322中虚线代表HEMT中缓冲层322与势垒层324形成的异质结构中产生的二维电子气(two-dimensional electron gas，2DEG)，二维电子气沿着水平方向(如图3中，在缓冲层322中的虚线)的迁移率非常高，是HEMT工作的基础。插入层323的作用是可以提高二维电子气的密度、局域化程度及其迁移率，从而提高器件的性能，比如可以获得优异的开关性能等；所以插入层323是可选结构，在HEMT中不设插入层323时，器件性能会降低。另外，成核层321也是可选的结构，其主要作用是在缓冲层322与衬底31的材料的晶体结构差异比较大时用作过渡作用。例如：在缓冲层322与衬底31的材料的晶体结构差异比较大时，可以先在衬底上外延生成与衬底31的晶体结构差异较小的成核层321，然后在成核层321上外延形成缓冲层322。
目前，基于氮化镓的HEMT通常是通过外延生长制作于高纯度的碳化硅SiC衬底上的。由于高纯度的碳化硅衬底具有高电阻，与GaN具有较小的晶格失配，散热性能好等特征，是GaN外延的首选衬底。高纯度的碳化硅衬底通常是全部采用高纯度的SiC，这样的衬底的形成过程主要是采用高纯的SiC粉，通过物理气相传输法(physical vapor transport process，PVT)的方法，在超过2000度的温度条件下，高温升华得到SiC晶体，在SiC晶体生长过程中也要保持较高的纯度生长环境(需要隔绝空气中氮气)。再将SiC晶体再通过线切割，研磨和抛光等工艺加工得到SiC衬底。高纯的SiC粉主要是通过高纯碳C粉和高纯硅Si粉提纯后反应得到，对材料纯度要求高，一般纯度要大于99.999％。这样制作的衬底为本征半导体(或本征态的半导体)，厚度为500um±25μm，衬底具有比较高的电阻率，通常电阻率大于1e5Ω·cm(欧姆·厘米)，并且衬底具有比较高的导热率(在温度为298K时，导热率约为390W/cm·K)。可见，高纯度的碳化硅衬底加工工艺复杂，条件要求苛刻，导致衬底成本非常高，进而导致器件成本也高，限制了HEMT器件在更大范围的应用。
在本申请的实施例中，集成电路的衬底31采用复合衬底，如图5所示，衬底31包括：第一材料层311以及覆盖于第一材料层311上的第二材料层312，其中，晶体管32覆盖在于第二材料层312上；第二材料层312包含碳化硅SiC，第二材料层与第一材料层的材料的电阻率不同。在该方案中，主要通过不同电阻率的两个材料层形成集成电路的复合衬底，其中第二材料层覆盖于第一材料层上，并且第二材料层包含能够制作晶体管的碳化硅SiC，由于通过不同电阻率的两个材料层形成集成电路的复合衬底使得复合衬底实现可量产化，并且SiC性能调节也更加灵活，在成本管控上有更大的灵活度。
其中，第二材料层可以键合于第一材料层上，例如第二材料层是直接键合于第一材料层上，或者第二材料层通过中间介质层键合于第一材料层上。在一些示例中，第二材料层也可以通过外延生长于第一材料层上。需要说明的是，外延生长的工艺对环 境要求较高，而键合工艺环境要求较低，只需要采用PVT得到的SiC晶体，由SiC晶体切割得到的切片与第一材料层键合后对切片进行后续常规的减薄加工即可。
第一材料层311为绝缘材料；或者，第一材料层311为导电材料，第一材料层311为导电材料时第一材料层311的电阻率小于第二材料层的电阻率。本申请的实施例中第一材料层的材料导电特性不做限制，这样可以丰富第一材料层的材料的选择性。例如：第一材料层311的材料至少可以采用以下任一碳化硅SiC,氮化硅AlN，氧化铝Al 2O 3以及硅Si。例如，第一材料层311为导电材料时，可以采用导电型的SiC。则，第二材料层312的电阻率大于第一材料层311的电阻率。第一材料层311的电阻率小于0.03Ω·cm，第一材料层311的厚度为大于1μm，例如第一材料层的厚度可以为1-100μm，直径为100mm，150mm或者200mm。第一材料层311也可以AlN或Al 2O 3，例如采用多晶型的AlN或Al 2O 3，其电阻率>1e5ohm.cm。第一材料层311也可以采用单晶硅Si或多晶硅Si，其中采用单晶硅或多晶硅时，对第一材料层的电阻率不做限定。第一材料层311还可以是其他指标不达标的材料层，具体指标例如：电阻率不均匀、晶体偏角、微管等质量不达标。在一种方案中，第一材料层311可以采用PVT工艺形成。例如：第一材料层311的形成过程主要是采用SiC粉，通过PVT的方法高温升华得到SiC晶体，再将SiC晶体通过切割得到。在一些实施例中，第一材料层311掺杂有用于降低第一材料层311的电阻率的杂质。例如：对于第一材料层311的电阻率要求较低时，第一材料层311的制作工艺中对晶体生长的原料及环境要求较低，如：第一材料层311掺杂有提供载流子的杂质，具体的第一材料层311可以采用制作成本相对较低的N型衬底(例如，采用氮N元素掺杂)，通常N型衬底对原料和生产工艺的要求相对高纯度的衬底较低。以N型SiC晶体的生长为例，N型SiC晶体的生长对所用原料没有特别要求，即普通SiC粉以及高纯的SiC粉均可适用。N型SiC晶体较低的电阻率的形成主要在于对生长体系氮气成分的控制，使大量氮成功注入晶体，在SiC晶体中形成高浓度的浅施主能级，从而提供大量可自由移动的电子作为载流子，因此对生长体系以及原料中存在其他较低浓度(<1e18/cm3)杂质没有特别要求。其中，第一材料层311包含至少一种晶型。例如：第一材料层311至少包括以下晶型中的一种或多种4H-SiC，6H-SiC，3C-SiC(3-cubic，3层碳硅原子立方晶系)，15R-SiC(15-rhombohedron，15层碳硅原子菱形六面体)。这样，对于第一材料层包含的晶型的数量和种类不做限定，尤其第一材料层包含多种晶型时，对制作工艺要求降低，能够有效降低成本。
第二材料层312可以采用PVT得到的SiC晶体，再由SiC晶体进一步加工得到。具体方式可以参照上述第一材料层311的描述，区别为第二材料层312对制作工艺要求较高，需要控制第二材料层312主要包含一种晶型的碳化硅，第一晶型为4H或6H，例如，4H-SiC(4-hexagonal-SiC，4层碳硅原子六方晶系)或6H-SiC。需要说明的是，第二材料层主要采用单一晶型4H或6H的碳化硅的原因是有利于在衬底上外延生成的晶体管的各结构层的晶格适配，例如4H-SiC或6H-SiC与GaN具有较小的晶格失配。其中，第二材料层312的杂质主要为非故意掺杂，其中第二材料层312掺杂的提供载流子的杂质的浓度小于1e17cm^-3，提供载流子的杂质至少包括以下一项或多项氮N、硼B、铝AL。这样制作的第二材料层312为高纯度的SiC晶体，具有半绝缘体的特性， 能够适应晶体管的制作。第二材料层312的电阻率大于1e5Ω·cm。此外，在另一个实施例中，第二材料层312也可以采用掺杂得到的半绝缘体，如，第二材料层312也可以采用过渡金属掺杂实现半绝缘体，以提升第二材料层的电阻率；过渡金属包括钒V或铁Fe等过渡金属元素。SiC晶体中过渡金属杂质能作为深能级补偿中心,可以把SiC晶体中非故意掺杂的氮N、硼B补偿掉，实现第二材料层312的半绝缘特性。其中，过渡金属钒V是一种理想的深能级杂质，目前掺钒V的SiC晶体显示出了高阻特性。其原理为，钒V在SiC晶体中可以形成深补偿能级，位于禁带中央附近，可作为深受主杂质补偿氮，或作为深施主杂质补偿硼，能够起到很好地束缚载流子的作用，使SiC晶体在室温下即可显示半绝缘特性。第二材料层312中过渡金属的掺杂浓度为1e14cm^-3至1e17cm^-3。这样的掺杂浓度与SiC晶体中非故意掺杂的氮N、硼B等杂质的浓度接近，能够有效把SiC晶体中非故意掺杂的氮N、硼B补偿掉。第二材料层312的厚度大于1μm，例如，第二材料层的厚度可以为1到100μm。此外，对SiC晶体进一步加工为第二材料层312的工艺可以是线切割、离子束切割、激光玻璃、或者机械减薄等中的一种或多种方法。
第二材料层312是键合在第二材料层311上的，例如，可以通过表面活化键合(surface activated bonding，SAB)技术(具体可以是低温等离子键合)实现两者的键合。因此，并不要求第二材料层312与第一材料层311中的SiC晶体的晶向保持同向。如图6所示，第二材料层311垂直表面采用SiC晶体的[0001]晶体轴向，或者是接近于[0001]晶体轴向，如第二材料层的SiC的晶胞的轴向[0001]与垂直于第二材料层的方向的偏角小于4°(轴向偏角α为0到4度)。其中，轴向偏转角度越小越有利于晶体管中各个材料层尤其是GaN的晶格适配。
这样，本申请的实施例中的第一材料层主要采用与第二材料层电阻率不同的材料，例如在本申请的实施例中采用多晶型的SiC、硅Si、AlN或Al 2O 3形成第一材料层，或者采用能够提供载流子的杂质掺杂的导电型的SiC或硅Si形成第一材料层，或者采用其他指标不达标的材料层形成第一材料层；采用第一晶型的SiC形成具有半绝缘体特性的第二材料层，相对于现有技术全部使用高纯度的本征态的SiC衬底，本申请的衬底使用了第一材料层和第二材料层的复合衬底形式，可以降低对高纯度的的本征态的SiC的使用量。第一材料层的材料形式，决定第一材料层的生长工艺要求相对高纯度的本征态的SiC会降低很多；如：第一材料层可以为导电型的SiC(即采用能够提供载流子的杂质掺杂)；在第一材料层的制作工艺中对SiC粉的纯度以及生长环境要求较低，例如：第一材料层采用制作成本相对较低的N型衬底(采用氮N元素掺杂)；这样，通常N型衬底对原料和生产工艺的要求相对高纯度的衬底较低。以N型SiC晶体的生长为例，N型SiC晶体的生长对所用原料没有特别要求，即普通SiC粉以及高纯的SiC粉均可适用。又例如，第一材料层可以是带有多型的SiC，例如，第一材料层中可以包含有缺陷的单晶SiC，如混有其他晶型。这样，SiC晶体生长时，工艺难度降低，有效控制了成本。
在一种实施方式中，本申请的实施例提供一种集成电路的制作方法，参照图7所示，包括如下步骤：
101、在第一材料层上制作第二材料层。
其中，第二材料层包含碳化硅SiC，第二材料层与第一材料层的材料的电阻率不同。在步骤101中可以在第一材料层上键合第二材料层，例如直接将第二材料层是直接键合于第一材料层上，或者将第二材料层通过中间介质层键合于第一材料层上。在一些示例中，也可以通过外延生长在第一材料层上外延第二材料层。需要说明的是，外延生长的工艺对环境要求较高，而键合工艺环境要求较低，只需要采用PVT得到高纯度的SiC晶体，由SiC晶体切割得到的切片与第一材料层键合后对切片进行后续常规的减薄加工即可。
步骤101具体包括：
S1：在第一材料层上键合第三材料层。
第三材料层包含碳化硅SiC，第三材料层与第一材料层的材料的电阻率不同。具体的，第三材料层包含第一晶型的SiC，在一种实施方式中，第一晶型为4H，或6H。第一材料层为绝缘材料；或者，第一材料层为导电材料，第一材料层为导电材料时第一材料层的电阻率小于第三材料层的电阻率。本申请的实施例中第一材料层的材料导电特性不做限制，这样可以丰富第一材料层的材料的选择性。第一材料层的材料至少可以采用以下任一SiC,AlN，Al 2O 3以及Si。例如，第一材料层为导电材料时，可以采用导电型的SiC。则，第三材料层的电阻率大于第一材料层的电阻率。第一材料层的电阻率小于0.03Ω·cm，第一材料层的厚度大于1μm，例如第一材料层的厚度可以为1-100μm，直径为100mm，150mm或者200mm。第一材料层311也可以采用AlN或Al 2O 3，例如采用多晶型的AlN或Al 2O 3，其电阻率>1e5ohm.cm。第一材料层也可以采用单晶硅或多晶硅，其中采用单晶硅或多晶硅时，对第一材料层的电阻率不做限定。第一材料层还可以是其他指标不达标的材料层，具体指标例如：电阻率不均匀、晶体偏角、微管等质量不达标。在一种方案中，第一材料层可以采用PVT工艺形成。例如：第一材料层的形成过程主要是采用SiC粉，通过PVT的方法高温升华得到SiC晶体，再将SiC晶体通过切割得到。在一些实施例中，第一材料层掺杂有用于降低第一材料层的电阻率的杂质。例如：对于第一材料层的电阻率要求较低时，第一材料层的制作工艺中对晶体生长的原料及环境要求较低，例如：第一材料层掺杂有提供载流子的杂质，具体的第一材料层可以采用制作成本相对较低的N型衬底(例如，采用氮N元素掺杂)，通常N型衬底对原料和生产工艺的要求相对高纯度的衬底较低。以N型SiC晶体的生长为例，N型SiC晶体的生长对所用原料没有特别要求，即普通SiC粉以及高纯的SiC粉均可适用。N型SiC晶体较低的电阻率的形成主要在于对生长体系氮气成分的控制，使大量氮成功注入晶体，在SiC晶体中形成高浓度的浅施主能级，从而提供大量可自由移动的电子作为载流子，因此对生长体系以及原料中存在其他较低浓度(<1e18/cm3)杂质没有特别要求。其中，第一材料层包含至少一种晶型。例如：第一材料层至少包括以下晶型中的一种或多种4H-SiC，6H-SiC，3C-SiC(3-cubic，3层碳硅原子立方晶系)，15R-SiC(15-rhombohedron，15层碳硅原子菱形六面体)。这样，对于第一材料层包含的晶型的数量和种类不做限定，尤其第一材料层包含多种晶型时，对制作工艺要求降低，能够有效降低成本。
第三材料层可以采用PVT的方法高温升华得到高纯度的SiC晶体，再将SiC晶体再通过线切割得到。具体方式可以参照上述第一材料层的描述，区别为第三材料层对 制作工艺要求较高，需要控制第三材料层主要包含一种晶型的碳化硅，第一晶型为4H或6H，例如，4H-SiC(4-hexagonal-SiC，4层碳硅原子六方晶系)或6H-SiC。需要说明的是，第三材料层主要采用单一晶型4H或6H的碳化硅的原因是有利于在衬底上外延生成的晶体管的各结构层的晶格适配，例如4H-SiC或6H-SiC与GaN具有较小的晶格失配。其中，第三材料层的杂质主要为非故意掺杂，其中第三材料层掺杂的提供载流子的杂质的浓度小于1e17cm^-3，提供载流子的杂质至少包括以下一项或多项氮N、硼B、铝AL。这样制作的第三材料层312为高纯度的SiC晶体，具有半绝缘体的特性，能够适应晶体管的制作。例如：第三材料层312的电阻率大于1e5Ω·cm。此外，第三材料层也可以采用掺杂得到的半绝缘体，如，第三材料层也可以采用过渡金属掺杂实现半绝缘体，以提高第三材料层的电阻率；过渡金属包括钒V或铁Fe等过渡金属元素。SiC晶体中过渡金属杂质能作为深能级补偿中心,可以把SiC晶体中非故意掺杂的氮N、硼B补偿掉，实现第三材料层的半绝缘特性，其中，过渡金属钒V是一种理想的深能级杂质，目前掺钒V的SiC晶体显示出了高阻特性。其原理为，钒V在SiC晶体中可以形成深补偿能级，位于禁带中央附近，可作为深受主杂质补偿氮，或作为深施主杂质补偿硼，能够起到很好地束缚载流子的作用，使SiC晶体在室温下即可显示半绝缘特性。第三材料层中过渡金属的掺杂浓度为1e14cm^-3至1e17cm^-3，这样的掺杂浓度与SiC晶体中非故意掺杂的氮N、硼B等杂质的浓度接近，能够有效把SiC晶体中非故意掺杂的氮N、硼B补偿掉。这里对第三材料层313的厚度不做限定，其可以为1到100μm，或者更厚。
此外，第三材料层是通过键合在第一材料层上的，例如，可以通过表面活化键合(SAB)技术实现两者的键合。因此，并不要求第三材料层与第一材料层中的SiC晶体的晶向保持同向。第三材料层垂直表面采用SiC晶体的[0001]晶体轴向，或者是接近于[0001]晶体轴向，如第三材料层的SiC的晶胞的轴向[0001]与垂直于第三材料层的方向的偏角小于4°(轴向偏角α为0到4度)。其中，轴向偏转角度越小越有利于晶体管中各个材料层尤其是GaN的晶格适配。
S2、对第三材料层进行减薄处理形成第二材料层。
102、在第二材料层上制作晶体管。
其中具体是，通过MOCVD工艺外延如图5所示的成核层321、缓冲层322、插入层323、势垒层324。再经过器件加工工艺得到形成晶体管的电极以形成晶体管。
具体的以下分别以对第三材料层不同的减薄处理工艺说明如下：
参照图本申请的实施例提供一种集成电路的制作方法，参照图8-图11所示，包括如下步骤：
201、对第三材料层313进行切割处理，形成与第一材料层311接触的预切割层314。
其中，如步骤101所述，参照图8所示，第三材料层313包含SiC。第三材料层313以及第一材料层311的制作过程可以参照上述步骤101的描述不再赘述。在步骤201中，可以通过激光切割(其中激光切割的切割厚度10-100um)或者离子切割(其中离子切割的切割厚度1-5um)的方式在第三材料层313的内部形成一层预切割层314，参照图9所示，可以通过控制离子注入的深度在第三材料层313的内部形成一层预切 割层314。
202、在第一材料层311上键合第三材料层313，其中预切割层314与第一材料层311接触。
参照图10所示，在步骤202中主要可以通过表面活化键合SAB技术(具体可以是低温等离子键合)实现在第一材料层311上键合第三材料层。
203、将第三材料层313中除预切割层314以外的部分剥离。
如图11所示，在步骤203中，可以通过高温加热实现第三材料层中除预切割层以外的部分的切割和剥离，这样第三材料层313中一部分(即预切割层314或者第二材料层312)留在第一材料层311上，厚度为1-100um，另外一部分可以再重复利用。得到的如图11所示的复合衬底。
204、继续在衬底上制作晶体管(如图4所示)。
其中具体是，通过MOCVD工艺外延成核层321、缓冲层322、插入层323、势垒层324。再经过器件加工工艺得到形成晶体管的电极以形成晶体管。在一种示例中，还包括对第一材料层311进行背面减薄，例如对第一材料层311远离第二材料层312的表面进行研磨加工以及抛光加工等加工工艺中的一种或多种，以对第一材料层311进行减薄或去除，例如将第一材料层311从500um减薄至100um，以到达对器件整体厚度或散热的要求。此外，还可以继续在第一材料层311进行背面加工，例如在第一材料层311层的远离第二材料层312的表面进行背面过孔(back via)加工(如图12所示)，例如制作过孔，并在过孔表面沉积绝缘层，并制作与源极326导通的背面电极33，以利于器件的背面安装。
如图13所示，提供了一种功率放大器的具体封装结构，其中集成电路30封装于功率放大器的封装结构中，如图13所示，封装结构具体包括：散热基板41，其中为了提高散热基板41的导电性以及散热性，散热基板41可以采用复合材料，例如Cu/Mo/Cu形成的叠层结构；散热基板41通过烧结银粘接在散热基板41上，其中如图12所示的集成电路，该集成电路的晶体管32的源极326通过背面电极33与散热基板41导通；此外，漏极328和栅极325分别通过金线引线键合连接到管脚，管脚设置在绝缘层(例如可以是绝缘陶瓷)上，绝缘层通过绝缘粘接剂粘接于散热基板41上。此外，封装结构包括封装管壳42，封装管壳42通过绝缘粘接剂与散热基板41粘接，并且管脚的一端从封装结构露出已连接其他电路，其中集成电路30设置于封装管壳42与散热基板41包围的空间中。
具体的，在一种实施方式中，在制作如包含如图5所述的衬底的集成电路时，参照图14、图15所示，具体包括如下步骤：
301、在第一材料层311上键合第三材料层313。
其中，步骤301具体可以参照步骤201的制作过程，不在具体赘述。
302、对第三材料层313远离第一材料层311的表面进行减薄加工，形成第二材料层312。
减薄加工包括：研磨加工以及抛光加工等加工工艺中的一种或多种。和步骤201-203的区别是步骤301-302不采用切割、剥离的工艺，而是在键合的第三材料层313上直接做正面衬底减薄，这样可以直接得到比较平整的第二材料层312，比切割剥 离工艺少一个工艺。此外，通过正面衬底减薄工艺，可以任意控制第二材料层的厚度，可以实现从5-350um的任意厚度，而不受离子切割和激光切割工艺的限制(通常离子切割一般能得到厚度1-5um的材料层，激光切割可以实现10-100um厚度的切割)。正面衬底减薄具体可以是采用研磨工艺对第三材料层313去掉10-50um的厚度，然后第三材料层313远离第一材料层311的表面进行化学机械抛光(chemical mechanical polishingCMP),CMP主要的目的是得到粗糙度比较低的表面，例如粗糙度<0.5nm。
303、继续在衬底上，制作晶体管(如图4所示)。
其中具体是，通过MOCVD工艺外延成核层321、缓冲层322、插入层323、势垒层324。再经过器件加工工艺得到形成晶体管的电极以形成晶体管。在一种示例中，还包括对第一材料层311进行背面减薄及背面加工。
此外，本申请的实施例中以100μm厚度衬底的HEMT器件为例，在方案一中对100μm厚度的导电型的第一材料层作为衬底形成的HEMT器件的电学及热学性能进行了仿真；在方案二中对5μm厚度的第二材料层以及95μm厚度的第一材料层键合的复合衬底形成的HEMT器件的电学及热学性能进行了仿真；在方案三中对20μm厚度的第二材料层以及80μm厚度的第一材料层键合的复合衬底形成的HEMT器件的电学及热学性能进行了仿真；在方案四中对100μm厚度的第二材料层作为衬底形成的HEMT器件的电学及热学性能进行了仿真。
其中，图16示出了四种方案的HEMT在栅电压Vg(gate voltage)分别为0V、-1V、-2V或-3V时，漏电流(drain current，Id(安培A))-漏电压(drain voltage，Vd(伏特V))的曲线，其中，方案二、方案三以及方案四在固定的栅电压下曲线比较接近，在固定的栅电压方案一的曲线与其他方案的曲线区别较大，这说明衬底的材料对HEMT的电学性能Id-Vd影响较大，而第二材料层的厚度对HEMT的电学性能Id-Vd影响不大。
图17示出了四种方案的HEMT的漏电流(drain current，Id(安培A))-栅电压Vg(gate voltage)的曲线。其中，方案二、方案三以及方案四的曲线比较接近，方案一的曲线与其他方案的曲线区别较大，这说明衬底的材料对HEMT的电学性能Vg-Id曲线影响较大，而第二材料层的厚度对HEMT的电学性能Id-Vg曲线影响不大。
综合图16和图17，键合的第二材料层的厚度对HEMT的电学性能影响不大。
图18提供了方案一、方案四以及复合衬底(第二材料层不同厚度情况下)对于HEMT器件峰值结(PN junction)温的影响(单个HEMT的功率为5W)，黑色圆点显示随着第二材料层的厚度的增加，HEMT的峰值结温逐渐降低，当衬底全部采用第二材料层(即方案四)时，HEMT的峰值结温是231.25度(虚线)，而衬底全部采用第一材料层(即方案一)时，HEMT的峰值结温是249.45度(实线)，主要原因是由于第一材料层的导热率低于第二材料层的导热率。从黑色圆点的趋势来看，随着第二材料层厚度增加，峰值结温先下降的比较快，后下降的比较慢，转折点在3-5um厚度处。键合的第二材料层的厚度超过3-5um厚，其峰值结温就会低于方案一。仿真结果进一步说明第二材料层厚度超过3-5um，复合衬底的导热效果就会由于方案一，散热效果取决于第二材料层的厚度。如采用10um厚的第二材料层时，HEMT的峰值结温升高10.74度。另一个示例中，如图19所示，当单个HEMT的晶体管单元功率为1W时候，键合 10um厚度的第二材料层，HEMT的峰值结温仅升高2.15度。
在本申请的另一方面，还提供一种与计算机一起使用的非瞬时性计算机可读存储介质，该计算机具有用于设计集成电路的软件，该计算机可读存储介质上存储有一个或多个计算机可读数据结构，工艺设备使用上述一个或多个计算机可读数据结构制造上文所提供的集成电路。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种集成电路，其特征在于，包括衬底，其中所述衬底上覆盖有晶体管，所述衬底包括：第一材料层以及覆盖于所述第一材料层上的第二材料层，其中，所述晶体管覆盖在所述第二材料层上；
    所述第二材料层包含碳化硅SiC，所述第二材料层与第一材料层的材料的电阻率不同。
  2. 根据权利要求1所述的集成电路，其特征在于，所述第二材料层的碳化硅包括第一晶型的碳化硅，所述第一晶型为4H，或6H。
  3. 根据权利要求1或2所述的集成电路，其特征在于，所述第二材料层键合于所述第一材料层上。
  4. 根据权利要求1-3任一项所述的集成电路，其特征在于，所述第一材料层为绝缘材料；
    或者，所述第一材料层为导电材料，所述第一材料层的电阻率小于所述第二材料层的电阻率。
  5. 根据权利要求1-4任一所述的集成电路，其特征在于，所述第一材料层的材料至少可以采用以下任一碳化硅SiC、氮化铝AlN、氧化铝Al 2O 3及硅Si。
  6. 根据权利要求1-5任一项所述的集成电路，其特征在于，所述第二材料层的SiC的晶胞的轴向[0001]与垂直于所述第二材料层的方向的偏角小于4°。
  7. 根据权利要求1-5任一项所述的集成电路，其特征在于，所述第一材料层包含至少一种晶型。
  8. 根据权利要求7所述的集成电路，其特征在于，所述第一材料层包含以下至少一种晶型的碳化硅：4H-SiC，6H-SiC，3C-SiC以及15R-SiC。
  9. 根据权利要求1-8任一项所述的集成电路，其特征在于，所述第一材料层掺杂有提供载流子的杂质，用于降低所述第一材料层的电阻率。
  10. 根据权利要求1-8任一项所述的集成电路，其特征在于，所述第二材料层采用过渡金属掺杂，用于提升所述第二材料层的电阻率。
  11. 根据权利要求10所述的集成电路，其特征在于，所述过渡金属包括钒V或铁Fe。
  12. 根据权利要求10或11所述的集成电路，其特征在于，所述第二材料层中过渡金属的掺杂浓度为1e14cm^-3至1e17cm^-3。
  13. 根据权利要求1-12任一项所述的集成电路，其特征在于，所述第一材料层的电阻率小于0.03Ω·cm。
  14. 根据权利要求1-13任一项所述的集成电路，其特征在于，所述第二材料层的电阻率大于1e5Ω·cm。
  15. 根据权利要求1-14任一项所述的集成电路，其特征在于，所述第二材料层掺杂的提供载流子的杂质的浓度小于1e17cm^-3，所述提供载流子的杂质至少包括以下一项或多项氮N、硼B、铝AL。
  16. 根据权利要求1-15任一项所述的集成电路，其特征在于，所述第二材料层的厚度包括1μm到100um的范围。
  17. 一种集成电路的制作方法，其特征在于，该制作方法包括：
    在第一材料层上制作第二材料层，所述第二材料层包含碳化硅SiC，所述第二材料层与第一材料层的材料的电阻率不同；
    在所述第二材料层上制作晶体管。
  18. 根据权利要求17所述的制作方法，其特征在于，在第一材料层上制作第二材料层包括：
    在第一材料层上键合第三材料层，所述第三材料层包含碳化硅SiC，所述第三材料层与第一材料层的材料的电阻率不同；
    对所述第三材料层进行减薄处理形成第二材料层。
  19. 根据权利要求18所述的制作方法，其特征在于，所述在第一材料层上键合第三材料层之前，包括：对所述第三材料层进行切割处理，形成与所述第一材料层接触的预切割层；
    在第一材料层上键合第三材料层；包括：在第一材料层上键合第三材料层，其中所述预切割层与所述第一材料层接触；
    所述对所述第三材料层进行减薄处理形成第二材料层，包括：将所述第三材料层中除所述预切割层以外的部分剥离。
  20. 根据权利要求19所述的制作方法，其特征在于，对所述第三材料层进行减薄处理形成第二材料层，包括：对所述第三材料层远离所述第一材料层的表面进行减薄加工，形成第二材料层。
  21. 根据权利要求20所述的制作方法，其特征在于，所述减薄加工至少包括以下一种或多种：研磨加工以及抛光加工。
  22. 一种功率放大器，其特征在于，包括如权利要求1-16任一项所述的集成电路以及封装结构，其中所述集成电路封装于所述封装结构内部。
  23. 一种电子设备，包括功率放大器及天线，所述功率放大器用于将射频信号放大后输出至所述天线向外辐射，所述功率放大器包括如权利要求22所述的功率放大器。
  24. 根据权利要求23所述的电子设备，其特征在于，所述电子设备包括基站或终端。
PCT/CN2020/142258 2020-12-31 2020-12-31 一种集成电路、功率放大器及电子设备 WO2022141442A1 (zh)

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