WO2022041157A1 - 一种衬底及功率放大器件 - Google Patents

一种衬底及功率放大器件 Download PDF

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WO2022041157A1
WO2022041157A1 PCT/CN2020/112292 CN2020112292W WO2022041157A1 WO 2022041157 A1 WO2022041157 A1 WO 2022041157A1 CN 2020112292 W CN2020112292 W CN 2020112292W WO 2022041157 A1 WO2022041157 A1 WO 2022041157A1
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substrate
epitaxial layer
epitaxial
layer
resistivity
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PCT/CN2020/112292
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English (en)
French (fr)
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胡彬
段焕涛
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华为技术有限公司
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Priority to JP2023513837A priority Critical patent/JP2023539318A/ja
Priority to EP20950827.4A priority patent/EP4195239A4/en
Priority to CN202080103586.8A priority patent/CN116034485A/zh
Priority to PCT/CN2020/112292 priority patent/WO2022041157A1/zh
Publication of WO2022041157A1 publication Critical patent/WO2022041157A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02447—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02581—Transition metal or rare earth elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a substrate and a power amplifier device.
  • High-electron-mobility transistors are mainly used in power amplifier devices in electronic equipment.
  • the power of the radio frequency signal generated in the radio frequency modulation circuit of electronic equipment is very small, and it needs to go through a series of amplification to obtain enough radio frequency power before it can be fed to the antenna for radiation.
  • the radio frequency power amplifier In order to obtain enough radio frequency power, the radio frequency power amplifier must be used to amplify the power of the radio frequency signal.
  • RF power amplifiers are widely used in radar, wireless communication, navigation, satellite communication, electronic countermeasures and other systems equipment, and are the key components of modern wireless communication.
  • RF power amplifiers are devices based on silicon (Si) or gallium arsenide (GaAs) materials.
  • Si silicon
  • GaAs gallium arsenide
  • 5G era High electron mobility transistors based on gallium nitride (GaN) are widely used in base station and other equipment with high performance characteristics.
  • GaN-based HEMTs are usually fabricated on high-purity silicon carbide substrates by epitaxial growth.
  • the substrate is usually formed of silicon carbide SiC material, and the formation process of the substrate is mainly made of high-purity silicon carbide powder. Under the conditions of high temperature sublimation to obtain SiC crystal, a high-purity growth environment should be maintained during the growth of SiC crystal (need to isolate nitrogen in the air). The SiC crystal is then processed by wire cutting, grinding and polishing to obtain a silicon carbide substrate. High-purity silicon carbide powder is mainly obtained by the reaction of high-purity carbon powder and high-purity silicon powder after purification.
  • the substrate thus produced is an intrinsic semiconductor (or an intrinsic state semiconductor), the resistivity of the substrate is greater than 1e5 ⁇ cm (ohm ⁇ cm), and the thickness is 500um ⁇ 25 ⁇ m.
  • the SiC crystal growth and substrate processing technology are complex and the conditions are harsh, resulting in a very high substrate cost, which in turn leads to a high device cost, which limits the wider application of HEMT devices.
  • the size of the silicon carbide semiconductor substrate is mainly 100mm (4 inches), and further expansion to 150mm (6 inches) and 200mm (8 inches) has technical challenges and higher costs.
  • the present application provides a substrate and a power amplifier device, which realizes a new type of composite substrate, reduces the dependence of transistors on silicon carbide semiconductor substrates, and effectively controls costs.
  • a substrate is provided.
  • the substrate is used for transistors, such as HEMT, wherein the epitaxial structure of the transistor is formed on the substrate, and the substrate includes: a substrate and a first epitaxial layer formed on the substrate, and the first epitaxial layer is a semiconductor; wherein, the substrate and the first epitaxial layer are formed on the substrate.
  • the epitaxial layer includes SiC material; the first epitaxial layer is doped with transition metal, and the substrate is doped with impurities that provide carriers.
  • the substrate can use at least two material layers, namely the base and the first epitaxial layer, wherein the base is mainly made of SiC material and is doped with impurities that provide carriers, and the first epitaxial layer is made of transition metal doped.
  • SiC material in this way, since the first epitaxial layer adopts SiC material doped with transition metal, and the impurity compensation of the SiC material is performed by the transition metal, the resistivity of the first epitaxial layer can be improved, so that the first epitaxial layer has the characteristics of a semi-insulator,
  • the embodiments of the present application reduce the requirement for the substrate.
  • a SiC material is used to form a substrate
  • a transition metal-doped silicon carbide material is used to form a first epitaxial layer with semi-insulator characteristics, and compared with the prior art, all silicon carbide materials are used to form an intrinsic state.
  • Silicon carbide substrate, the substrate of the present application adopts the form of a composite substrate of a base and a first epitaxial layer, which can reduce the usage amount of silicon carbide material in an intrinsic state.
  • the substrate can be a conductive type silicon carbide material doped with impurities that can provide carriers, so that the growth process requirements are much lower than that of the eigenstate silicon carbide material; Impurity doping to provide carriers), so that the resistivity of the first epitaxial layer is greater than the resistivity of the substrate; due to the low requirements for the resistivity of the substrate, the purity of the silicon carbide powder and the doping in the manufacturing process of the substrate are required.
  • the requirements are lower, for example: the base adopts an N-type substrate with relatively low production cost (doping with N-type elements); in this way, when using SiC powder to form SiC crystals, it is not necessary to completely isolate the air, and it is not necessary to completely isolate the air during the production process.
  • Impurities that can provide carriers, such as nitrogen N, aluminum Al, boron B, etc., introduced by doping are also not required.
  • a second epitaxial layer is included between the first epitaxial layer and the substrate, and the second epitaxial layer includes a SiC material, wherein the second epitaxial layer and the substrate are formed by different processing techniques.
  • the second epitaxial layer and the substrate are formed by different processing techniques.
  • the substrate mainly uses silicon carbide powder to grow a SiC crystal by a physical vapor transport process (PVT) method, and then the SiC crystal is processed by wire cutting, grinding and polishing to obtain a substrate.
  • PVT physical vapor transport process
  • the type of substrate so the purity of silicon carbide powder and the process complexity of PVT are lower.
  • a second epitaxial layer is epitaxially grown on the substrate by a high-temperature chemical vapor deposition method (chemical vapor deposition, CVD).
  • CVD chemical vapor deposition
  • the second epitaxial layer may be a conductive type silicon carbide material or a semi-insulator characteristic silicon carbide material.
  • the top epitaxial layer such as the first epitaxial layer
  • the epitaxial layer in the middle adopts the conductive type silicon carbide material, which can reduce the thickness of the first epitaxial layer as much as possible, thereby reducing the amount of transition metal used during doping, and also reducing the occurrence of crystal defects and crystal polytype problems.
  • the second epitaxial layer may be a semi-insulator character silicon carbide material formed by doping a transition metal (eg, vanadium V or iron Fe) with a reactive gas during epitaxial growth.
  • the resistivity of the first epitaxial layer is greater than the resistivity of the substrate.
  • the resistivity of the first epitaxial layer is greater than 1e5 ⁇ cm, and the resistivity of the substrate is less than 0.03 ⁇ cm.
  • the resistivity of the second epitaxial layer is equal to the resistivity of the substrate, for example: the resistivity of the second epitaxial layer is less than 0.03 ⁇ cm; or the resistivity of the second epitaxial layer is greater than that of the substrate and smaller than the resistivity of the first epitaxial layer.
  • the resistivity of the second epitaxial layer may be greater than or equal to 0.03 ⁇ cm and less than 1e5 ⁇ cm. This enables a gradual transition of resistivity from the substrate to the first epitaxial layer.
  • the resistivity can be adjusted by controlling the concentration of the doped transition metal, so that when the doping concentration of the transition metal in the second epitaxial layer is lower than that of the first epitaxial layer, the resistivity of the second epitaxial layer is smaller than that of the first epitaxial layer. In this way, crystal defects and crystal polytype problems caused by excessively large differences in material properties can also be avoided when the first epitaxial layer is directly fabricated on the substrate.
  • the resistivity of the second epitaxial layer can also be adjusted by controlling Si vacancies and/or C vacancies during SiC epitaxy.
  • the transition metal includes vanadium V or iron Fe.
  • the first epitaxial layer is mainly realized by doping transition metals in the process of chemical vapor deposition CVD homoepitaxial growth, and the transition metals include vanadium V or iron Fe.
  • the transition metal vanadium V is used for doping
  • the vanadium doping is realized by introducing an appropriate amount of vanadium compound reaction gas (eg VCl 4 ) during the epitaxial growth process.
  • the vanadium impurity in the SiC crystal can be used as a deep level compensation center.
  • the unintentionally doped nitrogen N and boron B in the SiC crystal can be compensated to realize the semi-insulator characteristics of the first epitaxial layer.
  • the transition metal iron when used for doping, the iron doping is realized by feeding an appropriate amount of reaction gas of iron compound (such as tert-butylferrocene C 14 H 17 Fe) during the epitaxial growth process. miscellaneous.
  • iron compound such as tert-butylferrocene C 14 H 17 Fe
  • the doping concentration of the transition metal in the first epitaxial layer 312 is 1e14 cm ⁇ -3 to 1e17 cm ⁇ -3.
  • the thickness of the first epitaxial layer is 1 to 100 ⁇ m.
  • the thickness of the base is 350 ⁇ m ⁇ 25 ⁇ m, and the thickness of the first epitaxial layer is 1 to 100 ⁇ m, so that the thickness of the substrate can meet the requirements of the epitaxial structure of the epitaxial transistor.
  • the thickness of the first epitaxial layer is 1 to 50 ⁇ m
  • the thickness of the second epitaxial layer is 1 to 50 ⁇ m.
  • the thicknesses of the two epitaxial layers can be reduced to 1 to 50 ⁇ m, so as to minimize the thickness of the first epitaxial layer on the top layer.
  • the unit cell of the SiC material adopts a 4H structure.
  • a method for fabricating a substrate is provided, the substrate is used for a transistor, wherein an epitaxial structure of the transistor is formed on the substrate, and the fabrication method includes: performing surface processing on the surface of the substrate; A first epitaxial layer is fabricated on the substrate, the substrate and the first epitaxial layer include SiC material; the first epitaxial layer is doped with transition metal, and the substrate is doped with impurities that provide carriers.
  • the method before fabricating the first epitaxial layer on the substrate, the method further includes: fabricating a second epitaxial layer on the substrate, and the second epitaxial layer includes a SiC material.
  • the surface processing includes one or more of cutting processing, grinding processing and polishing processing. After the surface of the substrate is surface-processed, the roughness of the surface of the substrate is less than or equal to 0.5 nm.
  • the method further includes: etching the surface of the substrate to form steps of atomic scale.
  • the width of the step is 1nm-3um
  • the height is 0.25nm-2nm.
  • fabricating the first epitaxial layer on the substrate includes: using a chemical vapor deposition process to epitaxially form the first epitaxial layer on the substrate.
  • the gas used in the chemical vapor deposition process includes: silane SiH 4 , propane C 3 H 8 , and transition metal compounds.
  • the transition metal compound comprises vanadium tetrachloride VCL 4 or tert-butylferrocene C 14 H 17 Fe.
  • fabricating the second epitaxial layer on the substrate includes: using a chemical vapor deposition process to epitaxially form the second epitaxial layer on the substrate.
  • the gas used in the chemical vapor deposition process includes: SiH 4 , propane C 3 H 8 .
  • the method further includes: performing a surface processing on the second epitaxial layer, so that the surface roughness of the second epitaxial layer is less than 0.5 nm.
  • the method further includes: performing a surface processing on the first epitaxial layer, so that the surface roughness of the first epitaxial layer is less than 0.5 nm.
  • a power amplifier device including a substrate, and an epitaxial structure of a transistor formed on the substrate, the substrate including the substrate as described above.
  • the epitaxial structure includes: a buffer layer disposed on the first epitaxial layer, a barrier layer disposed on the buffer layer; and electrodes on the barrier layer.
  • the epitaxial structure further includes: a nucleation layer disposed between the first epitaxial layer and the buffer layer.
  • the epitaxial structure further includes: an insertion layer disposed between the buffer layer and the barrier layer.
  • an electronic device including a power amplifier device and an antenna, the power amplifier device is used to amplify a radio frequency signal and then output it to the antenna for outward radiation, and the power amplifier device includes the above-mentioned power amplifier device .
  • a non-transitory computer-readable storage medium for use with a computer having software for designing integrated circuits, the computer-readable storage medium having stored thereon one or more computer-readable data structures , a process apparatus fabricates the substrate provided above using one or more of the computer readable data structures described above.
  • FIG. 1 is a schematic structural diagram of a hexagonal crystal system provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a base station according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a base station according to another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a power amplifier device according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a substrate provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a substrate according to another embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a substrate according to yet another embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a substrate according to another embodiment of the present application.
  • FIG. 9 is a schematic flowchart of a method for fabricating a substrate according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram 1 in a manufacturing process of a substrate according to an embodiment of the present application.
  • FIG. 11 is a second structural schematic diagram in a manufacturing process of a substrate according to an embodiment of the application.
  • FIG. 12 is a schematic structural diagram 3 in a manufacturing process of a substrate according to an embodiment of the present application.
  • FIG. 13 is a schematic flowchart of a method for fabricating a substrate according to another embodiment of the present application.
  • the hexagonal crystal system refers to the ownership of crystals in which there are hexagonal or hexagonal characteristic symmetry elements in the main axis direction of the c-crystal axis with the only high-order axis.
  • the hexagonal crystal system also known as "hexagonal galaxy", belongs to the intermediate crystal family.
  • four crystal axes a1, a2, a3 and c are usually used to calibrate the crystal plane index and crystal orientation index to reflect the crystal orientation and crystal plane of the atoms of the hexagonal crystal system.
  • the crystal orientation refers to the direction of the point array in the spatial lattice (the direction of the straight line connecting any node row in the lattice).
  • the crystal orientation is used to represent certain directions in the crystal, involving the position of atoms in the crystal, the direction of the atomic column, and the orientation of a group of parallel lines with the same direction.
  • a crystal plane refers to a plane passing through any lattice point in the spatial lattice (a plane composed of nodes in the lattice).
  • the crystal plane in the hexagonal system is used to represent the plane of the atoms in the crystal.
  • the crystal orientation of the c-axis is [0001]
  • the crystal orientation of the a1-axis is
  • the crystal orientation of the a2 axis is
  • the crystal orientation of the a3 axis is Also shown in Figure 1 are two crystal planes and
  • the white dots in Figure 1 are Si atoms, and the black dots are C atoms.
  • a semiconductor is a material whose electrical conductivity is between conductors and insulators at room temperature; semiconductors include intrinsic semiconductors and impurity semiconductors.
  • Semiconductors doped with a certain amount of impurities are called impurity semiconductors or extrinsic semiconductors. Among them, the impurities doped in the impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons, and the impurity semiconductors doped with impurities that provide electrons (such as 5-valent phosphorus element) are also called electron-type semiconductors or N-type semiconductors.
  • impurity semiconductors that are doped with impurities that provide holes are also called hole type semiconductors or P (positive, positive) type semiconductors), can improve the intrinsic semiconductor Generally speaking, the higher the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity.
  • this type of impurity semiconductor is also called conductive type semiconductor, for example, conductive type carbide Silicon material, doped impurities are nitrogen N, boron B, aluminum Al, etc.
  • the impurities doped in the impurity semiconductor can compensate the impurity semiconductor, the donor electrons are just enough to fill the acceptor energy level, but cannot provide electrons and holes in the conduction band and valence band, so that the semiconductor material with a wider band gap has Resistivity similar to that of an insulator.
  • the silicon carbide material is doped with a transition metal to achieve impurity compensation for the silicon carbide material, thereby increasing the resistivity of the silicon carbide material.
  • This type of impurity semiconductor is also called semi-insulating semiconductor or semi-insulating semiconductor. Insulator, or has semi-insulator properties.
  • At least one (a) of a, b or c may represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be It can be single or multiple.
  • words such as “first” and “second” do not limit the quantity and order.
  • orientation terms such as “upper” and “lower” are defined relative to the orientation in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, and they are used for relative In the description and clarification of the drawings, it may change correspondingly according to the change of the orientation in which the components are placed in the drawings.
  • the technical solution of the present application can be applied to electronic equipment, and the electronic equipment can be different types of user equipment or terminal equipment such as computers, mobile phones, tablet computers, wearable equipment, and vehicle-mounted equipment; the electronic equipment can also be a network such as a base station. equipment.
  • the electronic equipment may also be a device such as a power amplifier used in the above electronic equipment.
  • the embodiments of the present application do not specifically limit the specific form of the above electronic device.
  • the electronic equipment provided by the embodiments of this application takes a 5G base station as an example.
  • the 5G base station can be divided into a baseband unit (baseband unit, BBU)-active antenna unit (active antenna unit, AAU), a centralized unit-distributed unit (central unit) -distribute unit, CU-DU)-AAU, BBU-remote radio unit (RRU)-antenna, CU-DU-RRU-Antenna, integrated 5G base station (5G node base station, gNB) etc. different architectures. Taking a base station with a BBU-AAU architecture as an example, as shown in FIG.
  • the base station includes a BBU11 and an AAU12; wherein the BBU11 transmits the generated baseband digital signal through the AAU12.
  • the AAU includes a digital-to-analog conversion module 121 (for example, a digital to analog converter (DAC)), a radio frequency unit 122, a power amplifier 123 (power amplifier, PA), and an antenna 124, wherein,
  • the digital-to-analog conversion module 121 is used to convert the baseband digital signal output by the baseband processing unit into an analog signal
  • the radio frequency unit 122 is used to convert the analog signal into a low-power radio frequency signal
  • the power amplifier 123 is used to convert the low-power radio frequency signal into power.
  • the AAU shown in FIG. 3 includes n antennas 124 , and each antenna 124 corresponds to a group of digital-to-analog conversion modules 121 , radio frequency units 122 , and power amplifiers 123 .
  • the embodiments of the present application are not limited to the base stations shown in FIG. 2 and FIG. 3 . It can be understood that any of the above electronic devices that need to use a power amplifier to amplify signals belong to the application scenarios of the embodiments of the present application.
  • an embodiment of the present application provides a power amplifier device 30 (wherein the power amplifier device 30 may be the power amplifier 123 in FIG. 3 ), which mainly includes a substrate 31 and is fabricated on the substrate 31
  • the epitaxial structure 32 of the transistor mainly includes a nucleation layer 321, a buffer layer 322, an insertion layer 323 and a barrier layer 324 disposed on the substrate 31; electrodes are disposed on the epitaxial structure 32, such as: gate 35, source 33 and The drain electrode 34; the electrode is covered with a passivation layer 36.
  • the transistor is a high electron mobility transistor (HEMT) as an example
  • the nucleation layer 321 in the epitaxial structure 32 is usually made of aluminum nitride (AlN) material
  • the buffer layer 322 is usually made of GaN material
  • the insertion layer 323 Aluminum nitride (AlN) material is usually used
  • the barrier layer 324 is usually aluminum gallium nitride (AlGaN) material
  • the electrode is usually metal material.
  • the source electrode 33 and the drain electrode 34 respectively form conductive ohmic contact with the barrier layer 324
  • the gate electrode 35 and the barrier layer 324 form Schottky contact.
  • the dotted line in the buffer layer 322 represents the two-dimensional electron gas (2DEG) generated in the heterostructure formed by the buffer layer 322 and the barrier layer 324 in the HEMT, and the two-dimensional electron gas is along the plane direction (as shown in FIG. 3 ).
  • the mobility is very high and is the basis of HEMT operation.
  • the function of the insertion layer 323 is to improve the density, localization degree and mobility of the two-dimensional electron gas, thereby improving the performance of the device, such as excellent switching performance, etc.; therefore, the insertion layer 323 is an optional structure, in HEMT When the insertion layer 323 is not provided in the device, the performance of the device will be degraded.
  • the nucleation layer 321 is also an optional structure, and its main function is to serve as a transition when the crystal structures of the materials of the buffer layer 322 and the substrate 31 are quite different.
  • a nucleation layer 321 with a smaller crystal structure difference from the substrate 31 may be epitaxially grown on the substrate first, and then a nucleation layer 321 may be epitaxially formed on the substrate.
  • the buffer layer 322 is epitaxially formed.
  • the substrate 31 is a composite substrate. As shown in FIG. 5 , the substrate 31 includes a base 311 and a first epitaxial layer 312 formed on the base 311 , and the first epitaxial layer 312 is a semiconductor.
  • the substrate 311 and the first epitaxial layer 312 include SiC material; the first epitaxial layer 312 is doped with transition metal, and the substrate 311 is doped with impurities that provide carriers.
  • the first epitaxial layer 312 and the unit cell of the SiC crystal formed of the SiC material in the substrate 311 mainly adopt a 4H (4-hexagonal, 4-layer carbon-silicon atom hexagonal) structure.
  • the resistivity of the first epitaxial layer 312 is greater than that of the substrate.
  • the substrate may be a conductive type SiC material.
  • the resistivity of the substrate 311 is less than 0.03 ⁇ cm
  • the thickness of the substrate 311 is 350 ⁇ m ⁇ 25 ⁇ m
  • the diameter is 100 mm, 150 mm or 200 mm.
  • the first epitaxial layer 312 is mainly realized by doping transition metals in the process of chemical vapor deposition (CVD) homoepitaxial growth, and the transition metals include vanadium V or iron Fe.
  • the transition metal vanadium V is used for doping
  • the vanadium doping is realized by introducing an appropriate amount of vanadium compound reaction gas (eg VCl 4 ) during the epitaxial growth process.
  • the vanadium impurity in the SiC crystal can be used as a deep level compensation center.
  • the unintentionally doped nitrogen N and boron B in the SiC crystal can be compensated to realize the semi-insulator characteristics of the first epitaxial layer 312 .
  • the doping concentration of the transition metal in the first epitaxial layer 312 is 1e14 cm ⁇ -3 to 1e17 cm ⁇ -3, the resistivity of the first epitaxial layer 312 is greater than 1e5 ⁇ cm, and the thickness of the first epitaxial layer 312 is 1 to 100 ⁇ m.
  • the iron doping is realized by feeding an appropriate amount of reaction gas of iron compound (such as tert-butylferrocene C 14 H 17 Fe) during the epitaxial growth process. miscellaneous.
  • the formation process of the substrate is mainly to use silicon carbide powder, obtain SiC crystal by high temperature sublimation by PVT method, and then obtain the SiC crystal by wire cutting.
  • the resistivity of the substrate is required to be low, the purity and doping requirements of the silicon carbide powder in the fabrication process of the substrate are low.
  • the substrate adopts an N-type substrate with relatively low fabrication cost (doping with N-type elements) In this way, when using SiC powder to form SiC crystal, it is not necessary to completely isolate the air, and there is no requirement for nitrogen N, aluminum Al, boron B, etc., which are introduced by unintentional doping in the production process.
  • the vertical surface of the substrate 31 adopts the [0001] crystal axis of the SiC crystal, or is close to the [0001] crystal axis, such as the axial declination angle ⁇ (0 to 4 degrees) (refer to FIG. 7 ).
  • the primary orientation flat of the horizontal surface of the substrate 31 is orientation (also known as the large cut edge), the second orientation flat is Orientation (also called small cutting edge).
  • the ratio of the length of the large cutting edge to the length of the small cutting edge is typically less than 2. For example, the length of the large cutting edge is 32.5 mm, and the length of the small cutting edge is 18 mm.
  • the substrate can use at least two material layers, namely the base and the first epitaxial layer, wherein the base is mainly made of SiC material and is doped with impurities that provide carriers, and the first epitaxial layer is made of transition metal doped.
  • SiC material in this way, since the first epitaxial layer adopts SiC material doped with transition metal, and the impurity compensation of the SiC material is performed by the transition metal, the resistivity of the first epitaxial layer can be improved, so that the first epitaxial layer has the characteristics of a semi-insulator,
  • the embodiments of the present application reduce the requirement for the substrate.
  • a SiC material is used to form a substrate
  • a transition metal-doped silicon carbide material is used to form a first epitaxial layer with semi-insulator characteristics, and compared with the prior art, all silicon carbide materials are used to form an intrinsic state.
  • Silicon carbide substrate, the substrate of the present application uses the form of a composite substrate of a base and a first epitaxial layer, which can reduce the amount of silicon carbide material used in the intrinsic state.
  • the substrate can be a conductive type silicon carbide material doped with impurities that can provide carriers, so that the growth process requirements are much lower than that of the intrinsic state silicon carbide material; for example: the substrate can be a conductive type SiC material (that is, using Impurity doping that can provide carriers), so that the resistivity of the first epitaxial layer is greater than that of the substrate; due to the low requirements for the resistivity of the substrate, the purity of the silicon carbide powder and the doping of the silicon carbide powder are required in the substrate fabrication process.
  • the impurity requirements are low, for example: the base adopts an N-type substrate with relatively low production cost (doping with N-type elements); in this way, when using SiC powder to form SiC crystals, it is not necessary to completely isolate the air, and it is not necessary to completely isolate the air in the production process. Impurities that can provide carriers, such as nitrogen N, aluminum Al, boron B, etc., introduced by intentional doping are also not required.
  • the substrate 31 may be in the form of multiple epitaxial layers on the substrate 311. As shown in FIG. 8, a second epitaxial layer 313 is included between the first epitaxial layer 312 and the substrate 311.
  • the second epitaxial layer 313 includes SiC material, wherein the second epitaxial layer and the substrate are formed using different processing techniques.
  • the thickness of the first epitaxial layer can be reduced as much as possible, wherein the requirements for the second epitaxial layer are similar to those of the substrate, which can further reduce the use of intrinsic state silicon carbide materials quantity.
  • the second epitaxial layer may be a conductive silicon carbide material or a semi-insulator characteristic silicon carbide material.
  • the resistivity of the second epitaxial layer may be equal to the resistivity of the substrate, for example, the resistivity of the second epitaxial layer is less than 0.03 ⁇ cm.
  • the top epitaxial layer eg, the first epitaxial layer 313
  • the middle epitaxial layer eg, the second epitaxial layer
  • a conductive type epitaxial layer is used to minimize the thickness of the first epitaxial layer.
  • the thickness of the first epitaxial layer is 1 to 50 ⁇ m
  • the thickness of the second epitaxial layer is 1 to 50 ⁇ m.
  • the sum of the thicknesses of the second epitaxial layer is basically the same as that of the substrate shown in FIG. 3 , but since only the first epitaxial layer needs to be doped, the amount of transition metal used during doping is reduced, and crystal defects and crystallites are also reduced. Occurrence of polymorphic problems.
  • the resistivity of the second epitaxial layer is greater than the resistivity of the substrate and less than the resistivity of the first epitaxial layer.
  • the resistivity of the second epitaxial layer can also be greater than or equal to 0.03 ⁇ cm and less than 1e5 ⁇ cm. This enables a gradual transition of resistivity from the substrate to the first epitaxial layer.
  • the second epitaxial layer may be a semi-insulator silicon carbide material formed by doping a transition metal (eg, vanadium V or iron Fe) with a reactive gas during the epitaxial growth process.
  • a transition metal eg, vanadium V or iron Fe
  • the resistivity can be adjusted by controlling the concentration of the doped transition metal, so that when the doping concentration of the transition metal in the second epitaxial layer is lower than that of the first epitaxial layer, the resistivity of the second epitaxial layer is smaller than the resistance of the first epitaxial layer. This can also avoid the occurrence of crystal defects and crystal polytype problems caused by too large difference in material properties when the first epitaxial layer is directly fabricated on the substrate.
  • the resistivity of the second epitaxial layer can also be adjusted by controlling the Si vacancies and/or C vacancies in the SiC epitaxy process, which can be achieved by controlling the ratio of C atoms and Si atoms in the gas used for the epitaxy of the second epitaxial layer. Adjustment of Si vacancies and/or C vacancies.
  • the unit cell of the SiC crystal formed by the SiC material of the second epitaxial layer 313 mainly adopts a 4H structure.
  • more epitaxial layers may also be included between the first epitaxial layer and the substrate.
  • the structures of these epitaxial layers are the same as those of the second epitaxial layer.
  • the second epitaxial layer and the substrate are formed by different processing techniques.
  • the substrate mainly uses silicon carbide powder to grow SiC crystal by physical vapor transport method PVT method, and then the SiC crystal is processed by wire cutting, grinding and polishing to obtain the substrate. The purity of the powder and the process complexity of PVT are less demanding. Then, a second epitaxial layer is epitaxially grown on the substrate by high temperature chemical vapor deposition (CVD).
  • CVD high temperature chemical vapor deposition
  • an embodiment of the present application provides a method for fabricating a substrate, comprising the following steps:
  • the surface roughness of the substrate after surface processing is less than or equal to 0.5 nm, wherein the surface processing includes one or more of cutting processing, grinding processing and planing and milling processing.
  • the substrate is mainly made of silicon carbide powder by the physical vapor transport method PVT method to obtain SiC crystal, and then the SiC crystal is processed by wire cutting, grinding and polishing to obtain the substrate. Impurities of carriers), so the purity of silicon carbide powder and the process complexity of PVT are lower.
  • a first epitaxial layer on a substrate, where the substrate and the first epitaxial layer include SiC material; the first epitaxial layer is doped with a transition metal, and the first epitaxial layer is a semiconductor.
  • the substrate 311 adopts a conductive material
  • the substrate 311 includes a SiC material.
  • the SiC material in the substrate may be SiC whose unit cell mainly adopts a 4H (4-hexagonal, 4-layer carbon-silicon atom hexagonal crystal system) structure. crystal.
  • the resistivity of the substrate 311 is less than 0.03 ⁇ cm
  • the thickness of the substrate 311 is 350 ⁇ m ⁇ 25 ⁇ m
  • the diameter is 100 mm, 150 mm or 200 mm. As shown in FIG.
  • the vertical surface of the substrate 311 adopts the [0001] crystal axis of the SiC crystal, or is close to the [0001] crystal axis, such as the axial declination ⁇ (0- 4 degrees).
  • the surface of the substrate 311 is further etched through an etching process to obtain a step 3110 with an atomic size.
  • the width of the step 3110 is generally 1nm to 3um.
  • the height of the steps 3110 is typically 0.25 nm to 2 nm.
  • the etching process adopts hydrogen H2 etching, the etching temperature is 1500 to 1700 degrees, and the etching time is from 10 minutes to 200 minutes.
  • the function of making the steps of atomic scale in step 202 is to adjust the influence of the axial off-angle ⁇ on the fabrication of the first epitaxial layer. For example, as shown in FIG.
  • step 202 when the vertical surface of the substrate 311 has a leftward axial direction
  • the steps extend from left to right as shown in FIG. 11; when there is a rightward axial deflection angle ⁇ on the vertical surface of the substrate 311, the steps extend from right to left; in addition, the steps can be distributed continuously On the surface of the substrate 311 , or periodically distributed on the surface of the substrate 311 . Therefore, when the vertical surface of the substrate 311 adopts the [0001] crystal axis of the SiC crystal, step 202 can be omitted.
  • the first epitaxial layer 312 includes SiC material; the first epitaxial layer 312 is doped with transition metal.
  • a chemical vapor deposition process is specifically used to epitaxially form a first epitaxial layer 312 on the substrate, as shown in FIG. 12 .
  • the homoepitaxy of the conductive type SiC substrate is performed (that is, the first epitaxial layer and the substrate are made of the same SiC material).
  • Epitaxy is completed in high temperature chemical vapor deposition (CVD) equipment.
  • the temperature of epitaxial growth is 1400-1700 degrees.
  • the gases used for epitaxy are mainly silane SiH 4 , propane C 3 H 8 , HCl, H 2 and VCl 4 and other gases.
  • silane SiH 4 and propane C 3 H 8 are mainly used to react to obtain SiC
  • vanadium tetrachloride VCl 4 gas is mainly used to provide transition metal V element for doping
  • H 2 is a carrier gas
  • HCl is used as a growth additive. is to promote the growth rate of the silicon carbide epitaxial layer.
  • V element By doping V element, a first epitaxial layer is obtained, and the resistivity of the first epitaxial layer is greater than 1e5 ⁇ cm.
  • the V doping concentration is between 1e14 and 1e17cm ⁇ -3.
  • the thickness of the first epitaxial layer is generally 10 to 100 um.
  • an epitaxial crystal structure dominated by 4H-SiC SiC crystal of 4H structure
  • the etching process of step 202 and the epitaxy process of step 203 are completed in the same CVD equipment, so as to ensure that the etched substrate will not be secondary polluted.
  • step 203 if the first epitaxial layer is doped with a transition metal iron element, in this process, a certain proportion of tert-butylferrocene (C 14 H 17 Fe) is introduced in the CVD process.
  • the gas replaces the vanadium tetrachloride VCl 4 gas to realize the doping of silicon carbide.
  • the compound of vanadium reacts with the gas used for epitaxy of silicon carbide to form intermediate products or precipitates or generate other crystal forms (such as 3C-SiC crystal type, 3-cubic, 3-layer carbon-silicon atomic cubic crystal system) causes impurities or microscopic defects, and requires one-step surface processing (such as grinding, polishing, cutting) to remove the first epitaxial layer.
  • Some impurities 3121 and microscopic defects 3122 on the surface make the surface roughness of the first epitaxial layer less than 0.5 nm.
  • the epitaxial structure 32 of the transistor (as shown in FIG. 4 ) can be epitaxially grown on the substrate by a CVD process. Then, through a device processing process, electrodes for forming transistors are obtained to form transistors.
  • step 301 reference may be made to the production process of step 201, and details are not repeated here.
  • step 302 reference may be made to the production process of step 202, and details are not repeated here.
  • the second epitaxial layer includes a SiC material; in step 303, a chemical vapor deposition process is specifically used to epitaxially form the second epitaxial layer on the substrate. After the surface etching of the substrate is completed, the homoepitaxy of the conductive type SiC substrate is performed (that is, the second epitaxial layer and the substrate are made of the same SiC material). Epitaxy is completed in high temperature chemical vapor deposition (CVD) equipment. The temperature of epitaxial growth is 1400-1700 degrees.
  • the gases used for epitaxy are mainly silane SiH 4 , propane C 3 H 8 , HCl, H 2 and other gases, among which silane SiH 4. Propane C 3 H 8 is mainly used for reaction to obtain SiC.
  • the resistivity of the second epitaxial layer is less than 0.03 ⁇ cm.
  • a transition metal such as vanadium V or iron Fe
  • the resistivity can be adjusted by controlling the concentration of the doped transition metal; or by controlling The adjustment of the resistivity of the second epitaxial layer is realized by the Si vacancies in the SiC epitaxy process.
  • the etching process of step 302 and the epitaxy process of step 303 are completed in the same CVD equipment, so as to ensure that the etched substrate will not be secondary polluted.
  • step 303 the roughness of the surface of the second epitaxial layer can meet the requirements of fabricating the first epitaxial layer in the next step, then step 304 can be omitted.
  • the process of fabricating the first epitaxial layer on the second epitaxial layer is also homoepitaxial. Therefore, the process is the same as that of fabricating the first epitaxial layer on the substrate, and the details can be referred to step 204, which will not be repeated.
  • step 306 reference may be made to the production process of step 204, and details are not repeated here.
  • the epitaxial structure 32 (as shown in FIG. 4 ) of the epitaxial transistor can be continued on the substrate by CVD. Then, through a device processing process, electrodes for forming transistors are obtained to form transistors.
  • a non-transitory computer-readable storage medium for use with a computer having software for designing integrated circuits, the computer-readable storage medium having stored thereon one or more Computer-readable data structures, processing equipment using one or more of the computer-readable data structures described above to manufacture the substrates provided above.

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Abstract

本申请的实施例提供一种衬底及功率放大器件，涉及半导体技术领域，实现了一种新型的复合衬底，降低了晶体管对碳化硅半导体衬底的依赖，有效控制了成本。该衬底用于晶体管，其中晶体管的外延结构生成于衬底上，衬底包括：基底以及形成于基底上的第一外延层，第一外延层为半导体；其中，基底以及第一外延层包括SiC材料；第一外延层采用过渡金属掺杂。

Description

一种衬底及功率放大器件 技术领域
本申请涉及半导体技术领域，尤其涉及一种衬底及功率放大器件。
背景技术
高电子迁移率晶体管(high-electron-mobility transistor，HEMT)主要用于电子设备中的功率放大器件。例如，在电子设备的射频调制电路中所产生的射频信号功率很小，需要经过一系列的放大，获得足够的射频功率以后，才能馈送到天线上辐射出去。为了获得足够大的射频功率，必须采用射频功率放大器对射频信号进行功率放大。射频功率放大器在雷达、无线通信、导航、卫星通讯、电子对抗等系统的设备中有着广泛的应用，是现代无线通信的关键器件。
传统的第三代/第四代移动通信技术(3rd-generation of wireless communications technologies，3G)/4G时代，射频功率放大器是基于硅(Si)或者砷化镓(GaAs)材料的器件，在5G时代，基于氮化镓(GaN)的高电子迁移率晶体管以高性能特点广泛应用于基站等设备。其中，基于氮化镓的HEMT通常是通过外延生长制作于高纯度的碳化硅衬底上的。
目前，衬底通常是采用碳化硅SiC材料形成，衬底的形成过程主要是采用高纯的碳化硅粉末，通过物理气相传输法(physical vapor transport process，PVT)的方法，在超过2000度的温度条件下，高温升华得到SiC晶体，在SiC晶体生长过程中也要保持较高的纯度生长环境(需要隔绝空气中氮气)。再将SiC晶体再通过线切割，研磨和抛光等工艺加工得到碳化硅衬底。高纯的碳化硅粉末主要是通过高纯碳粉和高纯硅粉提纯后反应得到，对材料纯度要求高，一般纯度要大于99.999％。这样制作的衬底为本征半导体(或本征态的半导体)，衬底的电阻率大于1e5Ω·cm(欧姆·厘米)，厚度为500um±25μm。上述过程中，SiC晶体生长和衬底加工工艺复杂，条件要求苛刻，导致衬底成本非常高，进而导致器件成本也高，限制了HEMT器件在更大范围的应用。此外，碳化硅半导体衬底尺寸主要是100mm(4英寸)，尺寸进一步扩大到150mm(6英寸)、200mm(8英寸)有技术挑战，成本更高。
发明内容
本申请提供一种衬底及功率放大器件,实现了一种新型的复合衬底，降低了晶体管对碳化硅半导体衬底的依赖，有效控制了成本。
第一方面，提供一种衬底。该衬底用于晶体管，例如HEMT，其中晶体管的外延结构生成于衬底上，衬底包括：基底以及形成于基底上的第一外延层，第一外延层为半导体；其中，基底以及第一外延层包括SiC材料；第一外延层采用过渡金属掺杂，基底掺杂提供载流子的杂质。上述方案中，衬底可以采用至少两层材料层，即基底和第一外延层，其中基底主要采用SiC材料，并掺杂有提供载流子的杂质，第一外延层采用掺杂过渡金属的SiC材料，这样由于第一外延层采用掺杂过渡金属的SiC材料，通过过渡金属对SiC材料进行杂质补偿，因此能够提高第一外延层的电阻率，使得第一外延层具有半绝缘体的特性，满足外延结构的制作要求，由于外延结构不直接制作于 基底上，因此，本申请的实施例降低了对基底的要求。从而降低了晶体管对本征态的碳化硅衬底的依赖，有效控制了成本。例如：在本申请的实施例中采用SiC材料形成基底，采用掺杂过渡金属的碳化硅材料形成具有半绝缘体特性的第一外延层，相对于现有技术全部使用碳化硅材料形成本征态的碳化硅衬底，本申请的衬底使用了基底和第一外延层的复合衬底形式，可以降低对本征态的碳化硅材料的使用量。基底可以采用能够提供载流子的杂质掺杂的导电型的碳化硅材料，这样生长工艺要求相对本征态的碳化硅材料会降低很多；如：基底可以为导电型的SiC材料(即采用能够提供载流子的杂质掺杂)，这样第一外延层的电阻率大于基底的电阻率；由于对基底的电阻率要求较低，因此在基底的制作工艺中对碳化硅粉末的纯度以及掺杂要求较低，例如：基底采用制作成本相对较低的N型衬底(采用N型元素掺杂)；这样，在使用SiC粉末形成SiC晶体时，无需完全隔离空气，对生产工艺中由非故意掺杂引入的氮N、铝Al、硼B等能够提供载流子的杂质也不做要求。
在一种可能的实施方式中，第一外延层和基底之间包括第二外延层，第二外延层包括SiC材料，其中第二外延层和基底采用不同的加工工艺形成。其中采用两个或两个以上的外延层时，第一外延层和基底之间至少包含第二外延层，则只需要对顶层的外延层(例如第一外延层)进行过渡金属掺杂，可以尽量降低第一外延层的厚度，其中对第二外延层的要求类似于基底，可以进一步降低对本征态的碳化硅材料的使用量。此外，第二外延层与基底采用不同的加工工艺形成。例如：基底主要采用碳化硅粉末通过物理气相传输法(physical vapor transport process，PVT)的方法生长得到SiC晶体，再将SiC晶体通过线切割，研磨和抛光等工艺加工得到基底，由于基底可以采用导电型的基底，因此对碳化硅粉末的纯度，以及PVT的工艺复杂度要求较低。然后，通过高温化学气相沉积法(chemical vapor deposition，CVD)在基底上外延出第二外延层。
在一种可能的实施方式中，第二外延层可以采用导电型的碳化硅材料或半绝缘体特性的碳化硅材料。例如，采用两个或两个以上的外延层时，只需要对顶层的外延层(例如第一外延层)进行过渡金属掺杂，形成半绝缘体特性的碳化硅材料；而位于中间的外延层(如第二外延层)采用导电型的碳化硅材料，这样可以尽量降低第一外延层的厚度，从而减少掺杂时过渡金属的使用量，也减少了晶体缺陷和晶体多型问题的发生。或者，第二外延层可以是在外延生长过程中通过反应气体掺杂过渡金属(如钒V或铁Fe)掺杂形成的半绝缘体特性的碳化硅材料。
在一种可能的实施方式中，第一外延层的电阻率大于基底的电阻率。例如：第一外延层的电阻率大于1e5Ω·cm，基底的电阻率小于0.03Ω·cm。
在一种可能的实施方式中，第二外延层的电阻率等于基底的电阻率，例如：第二外延层的电阻率小于0.03Ω·cm；或者第二外延层的电阻率大于基底的电阻率并小于第一外延层的电阻率。例如：第二外延层的电阻率可以大于或等于0.03Ω·cm并小于1e5Ω·cm。这样可以实现从基底到第一外延层的电阻率的逐渐过渡。具体的，可以通过控制掺杂过渡金属的浓度实现电阻率的调整，这样在第二外延层的过渡金属的掺杂浓度小于第一外延层时，第二外延层的电阻率小于第一外延层的电阻率，这样也可以避免直接在基底上制作第一外延层时，材料性质差异过大导致的晶体缺陷和晶体 多型问题的发生。此外，第二外延层的电阻率也可以通过控制SiC外延过程中的Si空位和/或C空位来实现调整。
在一种可能的实施方式中，过渡金属包括钒V或铁Fe。第一外延层主要通过在化学气相沉积法CVD同质外延生长的过程中掺杂过渡金属来实现，过渡金属包括钒V或铁Fe。采用过渡金属钒V掺杂时，具体是通过在外延生长过程中通入适量的钒化合物的反应气体(如:VCl 4)实现钒掺杂，SiC晶体中钒杂质能作为深能级补偿中心,可以把SiC晶体中非故意掺杂的氮N、硼B补偿掉，实现第一外延层的半绝缘体特性。此外，需要说明的是，采用过渡金属铁掺杂时，具体是通过在外延生长过程中通入适量的铁化合物的反应气体(如:叔丁基二茂铁C 14H 17Fe)实现铁掺杂。
在一种可能的实施方式中，第一外延层312中过渡金属的掺杂浓度为1e14cm^-3至1e17cm^-3。
在一种可能的实施方式中，第一外延层的厚度为1到100μm。其中衬底仅包括基底和外延层时，基底的厚度为350μm±25μm，第一外延层的厚度为1到100μm，使得衬底厚度能够满足外延晶体管的外延结构的要求。
在一种可能的实施方式中，第一外延层的厚度为1到50μm，第二外延层的厚度为1到50μm。其中衬底仅包括基底以及至少两层外延层时，可以分别将两层外延层的厚度减薄至1到50μm，从而尽量减小顶层的第一外延层的厚度。
在一种可能的实施方式中，SiC材料的晶胞采用4H结构。
第二方面，提供一种衬底的制作方法，所述衬底用于晶体管，其中所述晶体管的外延结构生成于所述衬底上，该制作方法包括：对基底的表面进行表面加工；在基底上制作第一外延层，基底以及第一外延层包括SiC材料；第一外延层采用过渡金属掺杂，所述基底掺杂有提供载流子的杂质。
在一种可能的实施方式中，在基底上制作第一外延层之前，还包括：在所述基底上制作第二外延层，第二外延层包括SiC材料。
在一种可能的实施方式中，表面加工包括切削加工、研磨加工以及抛光加工中的一种或多种。对基底的表面进行表面加工后，基底的表面的粗糙度小于或等于0.5nm。
在一种可能的实施方式中，对基底的表面进行表面加工后，还包括：对基底的表面进行刻蚀形成原子级尺寸的台阶。其中，台阶的宽度为1nm-3um、高度为0.25nm-2nm。
在一种可能的实施方式中，在基底上制作第一外延层包括：采用化学气相沉积工艺在基底上外延出第一外延层。
在一种可能的实施方式中，所述化学气相沉积工艺使用的气体包括：硅烷SiH 4、丙烷C 3H 8、以及过渡金属化合物。
在一种可能的实施方式中，过渡金属化合物包括四氯化钒VCL 4或叔丁基二茂铁C 14H 17Fe。
在一种可能的实施方式中，在所述基底上制作第二外延层包括：采用化学气相沉积工艺在基底上外延出第二外延层。
在一种可能的实施方式中，化学气相沉积工艺使用的气体包括：SiH 4、丙烷C 3H 8。
在一种可能的实施方式中，在基底上制作第二外延层后还包括：对所述第二外延层进行一次表面加工，使得所述第二外延层的表面的粗糙度小于0.5nm。
在一种可能的实施方式中，在基底上制作第一外延层后还包括：对所述第一外延层进行一次表面加工，使得所述第一外延层的表面的粗糙度小于0.5nm。
第三方面，提供一种功率放大器件，包括衬底，以及形成于所述衬底上的晶体管的外延结构，衬底包括如上述的衬底。
在一种可能的实施方式中，所述外延结构包括：设置于所述第一外延层上的缓冲层、设置于所述缓冲层上的势垒层；所述势垒层上有电极。
在一种可能的实施方式中，所述外延结构还包括：设置于所述第一外延层与所述缓冲层之间的成核层。
在一种可能的实施方式中，所述外延结构还包括：设置于所述缓冲层与所述势垒层之间的插入层。
第四方面，提供一种电子设备，包括功率放大器件及天线，所述功率放大器件用于将射频信号放大后输出至所述天线向外辐射，所述功率放大器件包括如上述的功率放大器件。
第五方面，提供一种与计算机一起使用的非瞬时性计算机可读存储介质，该计算机具有用于设计集成电路的软件，该计算机可读存储介质上存储有一个或多个计算机可读数据结构，工艺设备使用上述一个或多个计算机可读数据结构制造上文所提供的衬底。
其中，第二方面至第五方面中任一种可能的实现方式所带来的技术效果可参见上述第一方面中不同实现方式所带来的技术效果，此处不再赘述。
附图说明
图1为本申请的实施例提供的一种六方晶系的结构示意图；
图2为本申请的实施例提供的一种基站的结构示意图；
图3为本申请的另一实施例提供的一种基站的结构示意图；
图4为本申请的实施例提供的一种功率放大器件的结构示意图；
图5为本申请的实施例提供的一种衬底的结构示意图；
图6为本申请的另一实施例提供的一种衬底的结构示意图；
图7为本申请的再一实施例提供的一种衬底的结构示意图；
图8为本申请的又一实施例提供的一种衬底的结构示意图；
图9为本申请的实施例提供的一种衬底的制作方法的流程示意图；
图10为本申请的实施例提供的一种衬底的制作过程中的结构示意图一；
图11为本申请的实施例提供的一种衬底的制作过程中的结构示意图二；
图12为本申请的实施例提供的一种衬底的制作过程中的结构示意图三；
图13为本申请的另一实施例提供的一种衬底的制作方法的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下对本申请的实施例中的技术术语说明如下：
六方(hexagonal)晶系，是指在唯一具有高次轴的c晶轴主轴方向存在六重轴或六重反轴特征对称元素的晶体归属。六方晶系也称作“六角星系”，属于中级晶族。 如图1所示，在六方晶系中通常采用a1、a2、a3以及c四个晶轴标定晶面指数和晶向指数，以反映六方晶系原子的晶向和晶面。其中，晶向指空间点阵中个点阵列的方向(连接点阵中任意节点列的直线方向)。在六方晶系中晶向用于表示晶体中的某些方向，涉及晶体中原子的位置、原子列方向，标识一组相互平行、方向一致的直线的指向。晶面指通过空间点阵中任意阵点的平面(在点阵中由节点构成的平面)。六方晶系中晶面用于表示晶体中原子构成的平面。例如在图1中以SiC的六方晶系结构为例，c轴的晶向为[0001]，a1轴的晶向为
Figure PCTCN2020112292-appb-000001
a2轴的晶向为
Figure PCTCN2020112292-appb-000002
a3轴的晶向为
Figure PCTCN2020112292-appb-000003
图1中还示出了两个晶面
Figure PCTCN2020112292-appb-000004
及
Figure PCTCN2020112292-appb-000005
其中图1中白点为Si原子，黑点为C原子。
半导体：半导体是一种常温下导电性能介于导体与绝缘体之间的材料；其中半导体包括本征半导体和杂质半导体。不含杂质和缺陷的纯净半导体，其内部电子和空穴浓度相等，称为本征半导体。掺入一定量杂质的半导体称为杂质半导体或非本征半导体。其中，杂质半导体中掺入的杂质能够提供一定浓度的载流子(如空穴或电子，其中掺杂提供电子的杂质(如5价的磷元素)的杂质半导体也称作电子型半导体或N(negative，负)型半导体，掺杂提供空穴的杂质(如3价的硼元素)的杂质半导体也称作空穴型半导体或P(positive，正)型半导体)时，能够改善本征半导体的导电性，通常载流子浓度越大，半导体的电阻率越低，导电性也越好，在本申请的实施例中，这一类杂质半导体也称为导电型半导体，例如，导电型碳化硅材料，掺杂的杂质为氮N、硼B、铝Al等。此外，杂质半导体中掺入的杂质能够对杂质半导体进行杂质补偿时，施主电子刚好够填充受主能级，但是不能向导带和价带提供电子和空穴，使禁带较宽的半导体材料具有与绝缘体相近的电阻率。例如，在本申请的实施例中，对碳化硅材料掺杂过渡金属实现对碳化硅材料的杂质补偿，从而提高碳化硅材料的电阻率，这一类杂质半导体也称为半绝缘型半导体或半绝缘体，或者具有半绝缘体特性。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
此外，本申请中，“上”、“下”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请的技术方案可以应用于电子设备，该电子设备该电子设备为计算机、手机、 平板电脑、可穿戴设备和车载设备等不同类型的用户设备或者终端设备；该电子设备还可以为基站等网络设备。电子设备也可以是用于上述电子设备中的功率放大器等装置。本申请实施例对上述电子设备的具体形式不做特殊限制。
本申请的实施例提供的电子设备以5G基站为例，5G基站可分为基带处理单元(baseband unit，BBU)-有源天线单元(active antenna unit，AAU)、集中单元-分布单元(central unit-distribute unit，CU-DU)-AAU、BBU-射频拉远单元(remote radio unit，RRU)-天线(antenna)、CU-DU-RRU-Antenna、一体化5G基站(5G node base station，gNB)等不同的架构。以BBU-AAU架构的基站为例，参照图2所示，基站：包括BBU11和AAU12；其中，BBU11将生成的基带数字信号通过AAU12发射。如图3所示，AAU包括数模转换模块121(例如可以是DAC(digital to analog converter，数字模拟转换器))、射频单元122、功率放大器123(power amplifier，PA)以及天线124，其中，数模转换模块121用于将基带处理单元输出的基带数字信号转换为模拟信号，射频单元122用于将模拟信号转化为小功率的射频信号，功率放大器123用于将小功率的射频信号进行功率放大后输出至天线124进行向外辐射。其中图3示出的AAU包括n个天线124，每个天线124对应一组数模转换模块121、射频单元122、功率放大器123。当然本申请的实施例不限于上述图2、图3示出的基站，可以理解的是，任意需要使用功率放大器对信号进行放大的上述电子设备均属于本申请的实施例的应用场景。
其中，如图4所示，本申请的实施例提供一种功率放大器件30(其中该功率放大器件30可以是图3中的功率放大器123)，主要包括衬底31以及制作于衬底31上的晶体管的外延结构32。其中，外延结构32主要包括设置于衬底31上的成核层321、缓冲层322、插入层323以及势垒层324；外延结构32上设置有电极，如：栅极35、源极33和漏极34；电极上覆盖有钝化层36。其中，晶体管以高电子迁移率晶体管(high electron mobility transistor，HEMT)为例，外延结构32中的成核层321通常采用氮化铝(AlN)材料，缓冲层322通常采用GaN材料，插入层323通常采用氮化铝(AlN)材料，势垒层324通常采用铝镓氮(AlGaN)材料，电极通常采用金属材料。其中，源极33和漏极34分别与势垒层324形成导电欧姆接触，栅极35与势垒层324形成肖特基接触。缓冲层322中虚线代表HEMT中缓冲层322与势垒层324形成的异质结构中产生的二维电子气(two-dimensional electron gas，2DEG)，二维电子气沿着平面方向(如图3中，在缓冲层322中的虚线)的迁移率非常高，是HEMT工作的基础。插入层323的作用是可以提高二维电子气的密度、局域化程度及其迁移率，从而提高器件的性能，比如可以获得优异的开关性能等；所以插入层323是可选结构，在HEMT中不设插入层323时，器件性能会降低。另外，成核层321也是可选的结构，其主要作用是在缓冲层322与衬底31的材料的晶体结构差异比较大时用作过渡作用。例如：在缓冲层322与衬底31的材料的晶体结构差异比较大时，可以先在衬底上外延生成与衬底31的晶体结构差异较小的成核层321，然后在成核层32上外延形成缓冲层322。
在本申请的实施例中，衬底31采用复合衬底，如图5所示，衬底31包括基底311和形成于基底311上的第一外延层312，第一外延层312为半导体。其中，基底311以及第一外延层312包括SiC材料；第一外延层312采用过渡金属掺杂，基底311掺 杂有提供载流子的杂质。
在一种实施方式中，第一外延层312以及基底311中由SiC材料形成的SiC晶体的晶胞主要采用4H(4-hexagonal，4层碳硅原子六方晶系)结构。第一外延层312的电阻率大于基底的电阻率。具体的，基底可以采用导电型的SiC材料。例如，基底311的电阻率小于0.03Ω·cm，基底311的厚度为350μm±25μm，直径为100mm，150mm或者200mm。第一外延层312主要通过在化学气相沉积法(chemical vapor deposition，CVD)同质外延生长的过程中掺杂过渡金属来实现，过渡金属包括钒V或铁Fe。采用过渡金属钒V掺杂时，具体是通过在外延生长过程中通入适量的钒化合物的反应气体(如:VCl 4)实现钒掺杂，SiC晶体中钒杂质能作为深能级补偿中心,可以把SiC晶体中非故意掺杂的氮N、硼B补偿掉，实现第一外延层312的半绝缘体特性。第一外延层312中过渡金属的掺杂浓度为1e14cm^-3至1e17cm^-3，第一外延层312的电阻率大于1e5Ω·cm，第一外延层312的厚度为1到100μm。此外，需要说明的是，采用过渡金属铁掺杂时，具体是通过在外延生长过程中通入适量的铁化合物的反应气体(如:叔丁基二茂铁C 14H 17Fe)实现铁掺杂。
基底的形成过程主要是采用碳化硅粉末，通过PVT的方法高温升华得到SiC晶体，再将SiC晶体再通过线切割得到。对于基底的电阻率要求较低时，基底的制作工艺中对碳化硅粉末的纯度以及掺杂要求较低，例如：基底采用制作成本相对较低的N型衬底(采用N型元素掺杂)；这样，在使用SiC粉末形成SiC晶体时，无需完全隔离空气，对生产工艺中由非故意掺杂引入的氮N、铝Al、硼B等也不做要求。
此外，结合图5、图6所示，由于第一外延层312是通过直接在基底上外延生长形成，因此第一外延层312与基底311中的SiC晶体的方向保持同向。如图5所示，衬底31垂直表面采用SiC晶体的[0001]晶体轴向，或者是接近于[0001]晶体轴向，如轴向偏角α(0到4度)(参照图7所示)。如图5、图6所示，衬底31的水平表面主晶向方向(primary orientation flat)是
Figure PCTCN2020112292-appb-000006
方向(也称作大切割边)，次晶向方向(second orientation flat)是
Figure PCTCN2020112292-appb-000007
方向(也称作小切割边)。此外，大切割边的长度与小切割边的长度的比值通常小于2。例如，大切割边的长度32.5mm，小切割边的长度18mm。
上述方案中，衬底可以采用至少两层材料层，即基底和第一外延层，其中基底主要采用SiC材料，并掺杂有提供载流子的杂质，第一外延层采用掺杂过渡金属的SiC材料，这样由于第一外延层采用掺杂过渡金属的SiC材料，通过过渡金属对SiC材料进行杂质补偿，因此能够提高第一外延层的电阻率，使得第一外延层具有半绝缘体的特性，满足外延结构的制作要求，由于外延结构不直接制作于基底上，因此，本申请的实施例降低了对基底的要求。从而降低了晶体管对本征态的碳化硅衬底的依赖，有效控制了成本。例如：在本申请的实施例中采用SiC材料形成基底，采用掺杂过渡金属的碳化硅材料形成具有半绝缘体特性的第一外延层，相对于现有技术全部使用碳化硅材料形成本征态的碳化硅衬底，本申请的衬底使用了基底和第一外延层的复合衬底形式，可以降低对对本征态的碳化硅材料的使用量。基底可以采用能够提供载流子的杂质掺杂的导电型的碳化硅材料，这样生长工艺要求相对本征态的的碳化硅材料会降低很多；如：基底可以为导电型的SiC材料(即采用能够提供载流子的杂质掺杂)，这样第一 外延层的电阻率大于基底的电阻率；由于对基底的电阻率要求较低，因此在基底的制作工艺中对碳化硅粉末的纯度以及掺杂要求较低，例如：基底采用制作成本相对较低的N型衬底(采用N型元素掺杂)；这样，在使用SiC粉末形成SiC晶体时，无需完全隔离空气，对生产工艺中由非故意掺杂引入的氮N、铝Al、硼B等能够提供载流子的杂质也不做要求。
在一种实施方式中，衬底31可以采用基底311上的多个外延层的方式，如图8所示，第一外延层312和基底311之间包括第二外延层313，第二外延层313包括SiC材料，其中第二外延层和基底采用不同的加工工艺形成。其中第一外延层和基底之间包含第二外延层时，可以尽量降低第一外延层的厚度，其中对第二外延层的要求类似于基底，可以进一步降低对本征态的碳化硅材料的使用量。第二外延层可以采用导电型的碳化硅材料或半绝缘体特性的碳化硅材料。第二外延层的电阻率可以等于基底的电阻率，例如：第二外延层的电阻率小于0.03Ω·cm。其中采用两个或两个以上的外延层时，只需要对顶层的外延层(例如第一外延层313)进行过渡金属掺杂，形成半导体；而位于中间的外延层(如第二外延层)采用导电型的外延层，这样可以尽量降低第一外延层的厚度，例如，第一外延层的厚度为1到50μm，第二外延层的厚度为1到50μm，则基底与第一外延层以及第二外延层的厚度之和基本上与图3示出的衬底相当，但是由于只需要对第一外延层掺杂，从而减少掺杂时过渡金属的使用量，也减少了晶体缺陷和晶体多型问题的发生。此外，第二外延层的电阻率大于基底的电阻率并小于第一外延层的电阻率。例如：第二外延层的电阻率也可以大于或等于0.03Ω·cm并小于1e5Ω·cm。这样可以实现从基底到第一外延层的电阻率的逐渐过渡。其中，第二外延层可以是在外延生长过程中通过反应气体掺杂过渡金属(如钒V或铁Fe)形成的半绝缘体特性的碳化硅材料。并且可以通过控制掺杂过渡金属的浓度实现电阻率的调整，这样在第二外延层的过渡金属的掺杂浓度小于第一外延层时，第二外延层的电阻率小于第一外延层的电阻率，这样也可以避免直接在基底上制作第一外延层时，材料性质差异过大导致的晶体缺陷和晶体多型问题的发生。此外，第二外延层的电阻率也可以通过控制SiC外延过程中的Si空位和/或C空位来实现调整，其中可以通过控制第二外延层外延使用的气体中C原子和Si原子的比例实现对Si空位和/或C空位的调整。本实施例中，第二外延层313的SiC材料形成的SiC晶体的晶胞主要采用4H结构。当然，第一外延层与基底之间还可以包括更多的外延层，当然在采用更多的外延层时，这些外延层的结构与第二外延层相同。此外，第二外延层与基底采用不同的加工工艺形成。例如：基底主要采用碳化硅粉末通过物理气相传输法PVT方法生长得到SiC晶体，将SiC晶体再通过线切割，研磨和抛光等工艺加工得到基底，由于基底可以采用导电型的基底，因此对碳化硅粉末的纯度，以及PVT的工艺复杂度要求较低。然后，通过高温化学气相沉积法(CVD)在基底上外延出第二外延层。
在一种实施方式中，本申请的实施例提供一种衬底的制作方法，包括如下步骤：
101、对基底的表面进行表面加工。
基底在表面加工后表面粗糙度≤0.5nm，其中表面加工包括切削加工、研磨加工以及刨铣加工中的一种或多种。基底主要采用碳化硅粉末通过物理气相传输法PVT方法生长得到SiC晶体，将SiC晶体再通过线切割，研磨和抛光等工艺加工得到基底，由 于基底可以采用导电型的基底(例如基底掺杂有提供载流子的杂质)，因此对碳化硅粉末的纯度，以及PVT的工艺复杂度要求较低。
102、在基底上制作第一外延层，基底以及第一外延层包括SiC材料；第一外延层采用过渡金属掺杂，第一外延层为半导体。
具体的，在一种实施方式中，在制作如图5所示的衬底时，参照图9所示，具体包括如下步骤：
201、对基底311的表面进行表面加工。
本申请的实施例中基底311采用导电型的材料，基底311包括SiC材料，例如基底中的SiC材料可以是晶胞主要采用4H(4-hexagonal，4层碳硅原子六方晶系)结构的SiC晶体。基底311的电阻率小于0.03Ω·cm，基底311的厚度为350μm±25μm，直径为100mm，150mm或者200mm。如图10所示，参考基底311表面的局部放大图，基底311垂直表面采用SiC晶体的[0001]晶体轴向，或者是接近于[0001]晶体轴向，如轴向偏角α(0-4度)。
202、对基底311的表面进行刻蚀形成原子级尺寸的台阶。
在该步骤202中进一步通过刻蚀工艺实现对基底311表面的刻蚀，得到原子级尺寸的台阶3110，如图11所示，台阶3110局部放大示意图中，台阶3110的宽度一般是1nm到3um,台阶3110的高度一般是0.25nm到2nm。该步骤中，刻蚀工艺采用氢气H 2刻蚀，刻蚀温度为1500到1700度，刻蚀时间为从10分钟到200分钟。其中，步骤202中制作原子级尺寸的台阶的作用是用于调整轴向偏角α对第一外延层制作的影响，例如，如图10所示，当基底311垂直表面存在向左的轴向偏角α时，如图11所示台阶为从左向右延伸；当基底311垂直表面存在向右的轴向偏角α时，台阶为从右向左延伸；另外，台阶可以是连续的分布在基底311的表面，或者周期性的分布在基底311的表面。因此当基底311垂直表面采用SiC晶体的[0001]晶体轴向时，可以省略步骤202。
203、在基底311上制作第一外延层312。
第一外延层312包括SiC材料；第一外延层312采用过渡金属掺杂。其中步骤203中具体采用化学气相沉积工艺在基底上外延出第一外延层312，如图12所示。完成基底的表面刻蚀后，再进行导电型的SiC基底的同质外延(即第一外延层与基底采用相同的SiC材料)。外延在高温化学气相沉积法(CVD)设备中完成，外延生长的温度在1400-1700度，外延使用的气体主要有硅烷SiH 4、丙烷C 3H 8、HCl、H 2和VCl 4等气体，其中硅烷SiH 4、丙烷C 3H 8主要是用来反应得到SiC，四氯化钒VCl 4气体主要是提供掺杂用的过渡金属V元素，H 2为载气，HCl作为生长添加剂，主要作用是促进碳化硅外延层的生长速度。通过掺杂V元素，获得第一外延层，第一外延层电阻率大于1e5Ω·cm。通常V掺杂浓度在1e14到1e17cm^-3之间。第一外延层的厚度一般是10到100um。通过调节不同气体的配比，流速和生长工艺条件，可以获得以4H-SiC(4H结构的SiC晶体)为主的外延晶体结构。通常，步骤202的刻蚀工艺和步骤203的外延工艺在同一个CVD设备内完成，保障刻蚀后的基底不被二次污染。此外，在步骤203中，如果通过过渡金属铁元素对第一外延层掺杂，则该过程中通过在CVD的过程中，通入一定比例的叔丁基二茂铁(C 14H 17Fe)的气体替代四氯化钒VCl 4气体，实现碳化硅的掺杂。
204、对第一外延层312进行一次表面加工。
在对基底外延第一外延层的过程中，由于工艺的不稳定性，容易出现杂质和缺陷，例如，钒的化合物与碳化硅外延使用的气体发生反应形成中间产物或者沉淀物或者生成其它晶型(如3C-SiC晶型，3-cubic，3层碳硅原子立方晶系)造成杂质或微观缺陷，需要进行一步表面加工(如研磨加工、抛光加工、切削加工)，来去除第一外延层表面的一些杂质3121和微观缺陷3122，使得第一外延层的表面的粗糙度小于0.5nm。最终得到如图5所示的衬底。
至此，可以继续在衬底上，通过CVD工艺外延晶体管的外延结构32(如图4所示)。再经过器件加工工艺得到形成晶体管的电极形成晶体管。
具体的，在一种实施方式中，在制作如图8所述的衬底时，参照图13所示，具体包括如下步骤：
301、对基底的表面进行表面加工。
其中，步骤301具体可以参照步骤201的制作过程，不在具体赘述。
302、对基底的表面进行刻蚀形成原子级尺寸的台阶。
其中，步骤302具体可以参照步骤202的制作过程，不在具体赘述。
303、在基底上制作第二外延层。
第二外延层包括SiC材料；其中步骤303中具体采用化学气相沉积工艺在基底上外延出第二外延层。完成基底的表面刻蚀后，再进行导电型的SiC基底的同质外延(即第二外延层与基底采用相同的SiC材料)。外延在高温化学气相沉积法(CVD)设备中完成，外延生长的温度在1400-1700度，外延使用的气体主要有硅烷SiH 4、丙烷C 3H 8、HCl、H 2等气体，其中硅烷SiH 4、丙烷C 3H 8主要是用来反应得到SiC。第二外延层的电阻率小于0.03Ω·cm。通过调节不同气体的配比，流速和生长工艺条件，可以获得以4H-SiC(4H结构的SiC晶体)为主的外延晶体结构。在步骤303中，可以在第二外延层外延生长过程中通过反应气体掺杂过渡金属(如钒V或铁Fe)，并且可以通过控制掺杂过渡金属的浓度实现电阻率的调整；或者通过控制SiC外延过程中的Si空位来实现第二外延层的电阻率的调整。通常，步骤302的刻蚀工艺和步骤303的外延工艺在同一个CVD设备内完成，保障刻蚀后的基底不被二次污染。
304、对第二外延层进行一次表面加工。
在对基底外延第二外延层的过程中，由于工艺的不稳定性，容易出现杂质和缺陷，例如，生成其它晶型(如3C-SiC晶型)造成杂质或微观缺陷，需要进行一步表面加工(如切削加工、研磨加工以及抛光加工)，来去除第二外延层表面的一些杂质和微观缺陷，使得第二外延层的表面的粗糙度小于0.5nm。当然，如果在步骤303之后，第二外延层表面的粗糙度可以达到下一步制作第一外延层的要求，则可以省略该步骤304。
305、在第二外延层上制作第一外延层。
其中在第二外延层上制作第一外延层的过程也是采用同质外延。因此该过程与在基底上制作第一外延层的方式相同，具体可以参照步骤204，不在赘述。
306、对第一外延层进行一次表面加工。
其中，步骤306具体可以参照步骤204的制作过程，不在具体赘述。
至此，可以继续在衬底上，通过CVD外延晶体管的外延结构32(如图4所示)。再经过器件加工工艺得到形成晶体管的电极形成晶体管。
在本申请的另一方面，还提供一种与计算机一起使用的非瞬时性计算机可读存储介质，该计算机具有用于设计集成电路的软件，该计算机可读存储介质上存储有一个或多个计算机可读数据结构，工艺设备使用上述一个或多个计算机可读数据结构制造上文所提供的衬底。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种衬底，其特征在于，用于晶体管，其中所述晶体管的外延结构生成于所述衬底上，所述衬底包括：基底以及形成于所述基底上的第一外延层，所述第一外延层为半导体；
    其中，所述基底以及所述第一外延层包括SiC材料；
    所述第一外延层采用过渡金属掺杂，所述基底掺杂有提供载流子的杂质。
  2. 根据权利要求1所述的衬底，其特征在于，所述第一外延层和所述基底之间包括第二外延层，所述第二外延层包括SiC材料，其中第二外延层和所述基底采用不同的加工工艺形成。
  3. 根据权利要求1或2所述的衬底，其特征在于，所述第一外延层的电阻率大于所述基底的电阻率。
  4. 根据权利要求2所述的衬底，其特征在于，所述第二外延层的电阻率大于所述基底的电阻率，并且所述第二外延层的电阻率小于所述第一外延层的电阻率。
  5. 根据权利要求1-4任一项所述的衬底，其特征在于，所述过渡金属包括钒V或铁Fe。
  6. 根据权利要求1-5任一项所述的衬底，其特征在于，所述第一外延层中过渡金属的掺杂浓度为1e14cm^-3至1e17cm^-3。
  7. 根据权利要求1-6任一项所述的衬底，其特征在于，所述基底的电阻率小于0.03Ω·cm。
  8. 根据权利要求1-7任一项所述的衬底，其特征在于，所述第一外延层的电阻率大于1e5Ω·cm。
  9. 根据权利要求2所述的衬底，其特征在于，所述第二外延层的电阻率小于0.03Ω·cm。
  10. 根据权利要求1-9任一项所述的衬底，其特征在于，所述SiC材料的晶胞采用4H结构。
  11. 一种衬底的制作方法，其特征在于，所述衬底用于晶体管，其中所述晶体管的外延结构生成于所述衬底上，该制作方法包括：
    对基底的表面进行表面加工；
    在所述基底上制作第一外延层，所述基底以及所述第一外延层包括SiC材料；所述第一外延层采用过渡金属掺杂，所述第一外延层为半导体，所述基底掺杂有提供载流子的杂质。
  12. 根据权利要求11所述的衬底的制作方法，其特征在于，在基底上制作第一外延层之前，还包括：在所述基底上制作第二外延层，所述第二外延层包括SiC材料。
  13. 根据权利要求11或12所述的衬底的制作方法，其特征在于，所述表面加工包括切削加工、研磨加工以及抛光加工中的一种或多种。
  14. 根据权利要求11-13任一项所述的衬底的制作方法，其特征在于，对所述基底的表面进行表面加工后，还包括：
    对所述基底的表面进行刻蚀形成原子级尺寸的台阶。
  15. 根据权利要求11-14任一项所述的衬底的制作方法，其特征在于，在所述基 底上制作第一外延层包括：
    采用化学气相沉积工艺在所述基底上外延出第一外延层。
  16. 根据权利要求15所述的衬底的制作方法，其特征在于，所述化学气相沉积工艺使用的气体包括：硅烷SiH 4、丙烷C 3H 8、以及过渡金属化合物。
  17. 根据权利要求16所述的衬底的制作方法，其特征在于，所述过渡金属化合物包括四氯化钒VCL 4或叔丁基二茂铁C 14H 17Fe。
  18. 一种功率放大器件，其特征在于，包括衬底，以及形成于所述衬底上的晶体管的外延结构，所述衬底包括如权利要求1-10任一项所述的衬底。
  19. 根据权利要求18所述的功率放大器件，其特征在于，所述外延结构包括：设置于所述第一外延层上的缓冲层、设置于所述缓冲层上的势垒层；所述势垒层上有电极。
  20. 根据权利要求19所述的功率放大器件，其特征在于，所述外延结构还包括：设置于所述第一外延层与所述缓冲层之间的成核层。
  21. 根据权利要求19所述的功率放大器件，其特征在于，所述外延结构还包括：设置于所述缓冲层与所述势垒层之间的插入层。
  22. 一种电子设备，包括功率放大器件及天线，所述功率放大器件用于将射频信号放大后输出至所述天线向外辐射，所述功率放大器件包括如权利要求18-21任一项所述的功率放大器件。
PCT/CN2020/112292 2020-08-28 2020-08-28 一种衬底及功率放大器件 WO2022041157A1 (zh)

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