WO2023039768A1 - 半导体器件及其制备方法、功率放大电路、电子设备 - Google Patents

半导体器件及其制备方法、功率放大电路、电子设备 Download PDF

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Publication number
WO2023039768A1
WO2023039768A1 PCT/CN2021/118619 CN2021118619W WO2023039768A1 WO 2023039768 A1 WO2023039768 A1 WO 2023039768A1 CN 2021118619 W CN2021118619 W CN 2021118619W WO 2023039768 A1 WO2023039768 A1 WO 2023039768A1
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source
semiconductor device
layer
substrate
conductive layer
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PCT/CN2021/118619
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English (en)
French (fr)
Inventor
张志利
饶进
刘涛
李海军
李水明
鲁明
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华为技术有限公司
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Priority to JP2024516635A priority Critical patent/JP2024537665A/ja
Priority to CN202180102317.4A priority patent/CN117941074A/zh
Priority to EP21957058.7A priority patent/EP4394890A4/en
Priority to PCT/CN2021/118619 priority patent/WO2023039768A1/zh
Publication of WO2023039768A1 publication Critical patent/WO2023039768A1/zh
Priority to US18/603,994 priority patent/US20240274688A1/en

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Definitions

  • the present application relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof, a power amplifier circuit, and electronic equipment.
  • semiconductor devices with high thermal conductivity, high electron drift rate, high temperature resistance, and stable chemical properties are widely used in high frequency, high temperature, and microwave fields.
  • the source of the semiconductor device when applied to an integrated circuit such as a power amplifier circuit, the source of the semiconductor device needs to be grounded.
  • a backhole structure is usually used, through which the source of the semiconductor device is connected to the back of the semiconductor, so that the source of the semiconductor device is directly grounded.
  • Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, a power amplifier circuit, and an electronic device, which are used to reduce the impact of setting a back hole on the semiconductor device.
  • a semiconductor device including: a substrate; a channel layer and a barrier layer, which are sequentially stacked on the substrate; a source, a gate, and a drain, which are arranged on the barrier layer
  • the back hole runs through the barrier layer region from the substrate to the source electrode; the back conductive layer covers the back hole and the back of the substrate, and the source electrode is connected to the back conductive layer.
  • the source is directly in ohmic contact with the barrier layer, and the back hole is located under the source.
  • the back hole is arranged under the source electrode, and the conductive layer on the back is directly connected to the source electrode through the back hole.
  • the signal directly contacts the conductive layer on the back from the source, so that the path for transmission to the source is shorter, which can reduce the inductance of the semiconductor device and increase the frequency of the semiconductor device.
  • the width of the back hole can be reasonably set according to the needs without additional reduction of the width of the back hole, so as to reduce the difficulty and yield of the preparation process of the back hole, improve the yield and reliability of the conductive layer on the back, and thereby improve the yield of semiconductor devices and reliability. Therefore, the size of the device source is reduced, so that a small-sized, low-cost semiconductor device can be produced.
  • the work function of the material of the source is in the range of 4.3-6eV.
  • the material of the source electrode as a metal with high work function and stable chemical properties (for example, including titanium, gold, platinum) or an alloy containing elements, active metals such as aluminum are no longer included.
  • the source electrode can block the etching of the back hole, and can also avoid corrosion in the wet process of the back hole process. Therefore, even if the source electrode is touched in the back hole process, the source electrode will not be damaged. Therefore, the source does not need to avoid the back hole, so as to prepare the above-mentioned semiconductor device.
  • the preparation process is simple, without increasing the difficulty of the process, and is easy to realize.
  • the material of the source electrode includes at least one of titanium, gold, and platinum. Commonly used several metal elements.
  • the source includes at least one conductive layer.
  • the structure is simple and the manufacturing process is simple.
  • the source electrode includes multiple conductive layers, the properties of different materials can be fused together, so that the stress and resistivity of the source electrode can be adjusted.
  • the source electrode can also include a conductive layer acting as a barrier to block the diffusion between the multi-layer metals, so as to prevent the volume expansion of the source electrode from causing damage to the semiconductor device.
  • the source level includes sequentially stacking a first conductive layer and a second conductive layer, the first conductive layer includes titanium elements, the second conductive layer includes gold elements, and the first conductive layer is in contact with the barrier layer.
  • the titanium element is arranged on the surface of the stacked semiconductor layer (such as a barrier layer), which not only plays a conductive role, but also plays an adhesive role, and improves the connection effect between the source electrode and the drain electrode and the stacked semiconductor layer.
  • the thickness of each conductive layer is in the range of 1 nm ⁇ 10000 nm.
  • the source is a planar structure.
  • the source electrode has a planar structure, simple structure and simple preparation process. Moreover, there is no need to consider the issue of how to interconnect multiple strip structures after the source is divided into structures including multiple strip patterns by providing openings on the source.
  • the source has an opening; the opening is above the back hole.
  • the source electrode will not be corroded due to etching during the fabrication of the back hole, that is, even if the source electrode is touched during the back hole process, the source electrode will not be damaged. Therefore, there is no need to set the opening on the source electrode larger than the size of the back hole in order to avoid corrosion caused by the back hole process, thereby reducing the size of the source electrode and reducing the size of the overall semiconductor device.
  • the semiconductor device further includes a thickened source; the thickened source is disposed on a surface of the source.
  • a thickened source electrode By setting a thickened source electrode, it is equivalent to increasing the thickness of the source electrode and reducing the resistance of the source electrode, thereby improving the current conduction capability of the semiconductor device.
  • the semiconductor device further includes a thickened source electrode, the thickened source electrode is disposed on the surface of the source electrode, and the thickened source electrode contacts the back conductive layer through the opening.
  • the semiconductor device further includes a thickened drain; the thickened drain is disposed on a surface of the drain.
  • the thickened drain By setting the thickened drain, it is equivalent to increasing the thickness of the drain and reducing the resistance of the drain, thereby improving the current conduction capability of the semiconductor device.
  • the semiconductor device further includes a field plate; the field plate is disposed on a side of the gate away from the substrate, between the gate and the drain, and overlaps with a projection of the gate. Since electric field peaks are prone to appear at the gate position, by setting a field plate above the gate, the electric field distribution in the semiconductor device can be modulated to make the electric field distribution uniform and avoid electric field peaks.
  • a power amplifier circuit including a package structure and the semiconductor device according to any one of the first aspect, and the semiconductor device is packaged inside the package structure.
  • the power amplifying circuit provided by the embodiment of the present application includes the semiconductor device of the first aspect, and its beneficial effect is the same as that of the semiconductor device, so it will not be repeated here.
  • an electronic device including a power amplifier and an antenna.
  • the power amplifier is used to amplify a radio frequency signal and output it to the antenna for external radiation.
  • the power amplifier includes the power amplifying circuit as in the second aspect.
  • the electronic device provided by the embodiment of the present application includes the semiconductor device according to the first aspect, and its beneficial effect is the same as that of the semiconductor device, which will not be repeated here.
  • a method for manufacturing a semiconductor device comprising: sequentially forming a stacked channel layer and a barrier layer on a substrate; forming a source, a gate, and a drain on the barrier layer; A back hole is formed below; the back hole runs through the barrier layer region from the substrate to the source; a back conductive layer is formed on the back of the substrate, and the back conductive layer covers the back hole and the back of the substrate; the source and the back conductive layer contact connection.
  • the material of the source is selected as a metal with a high work function and chemical stability (for example, including titanium, gold, platinum), and no active metal is included.
  • the source By adjusting the preparation process or the material of the source, the source directly forms an ohmic contact with the barrier layer.
  • the source electrode can block the etching of the back hole, and can also avoid corrosion in the wet process of the back hole process. In this way, the finally formed back hole is arranged under the source electrode, and the conductive layer on the back is directly connected to the source electrode through the back hole.
  • the signal directly contacts the conductive layer on the back from the source, so that the path for transmission to the source is shorter, which can reduce the inductance of the semiconductor device and increase the frequency of the semiconductor device.
  • the width of the back hole can be reasonably set according to the needs without additional reduction of the width of the back hole, so as to reduce the difficulty and yield of the preparation process of the back hole, improve the yield and reliability of the conductive layer on the back, and thereby improve the yield of semiconductor devices and reliability. Therefore, the size of the device source is reduced, so that a small-sized, low-cost semiconductor device can be produced.
  • forming the back hole under the source electrode includes: using a dry etching process to open holes in the film layer under the source electrode from the back of the substrate to form a back hole; using dry etching or wet etching Etching by-products remaining in the holes is removed by etching.
  • FIG. 1A is a schematic framework diagram of a terminal provided in an embodiment of the present application.
  • FIG. 1B is a schematic framework diagram of a base station provided in an embodiment of the present application.
  • FIG. 1C is a schematic framework diagram of a power amplifier circuit provided by an embodiment of the present application.
  • FIG. 2A is a schematic top view of an integrated circuit provided by an embodiment of the present application.
  • FIG. 2B is a schematic top view of another integrated circuit provided by the embodiment of the present application.
  • Fig. 2C is a sectional view along the A1-A2 direction in Fig. 2B;
  • FIG. 3A is a schematic top view of another integrated circuit provided by the embodiment of the present application.
  • Fig. 3B is a sectional view along the B1-B2 direction in Fig. 3A;
  • FIG. 4 is a flow chart for the preparation of a semiconductor device provided in an embodiment of the present application.
  • 5A-5G are schematic diagrams of the fabrication process of a semiconductor device provided in the embodiment of the present application.
  • FIG. 6A is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application.
  • FIG. 6B is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 6C is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 7A is a schematic top view of another integrated circuit provided by the embodiment of the present application.
  • FIG. 7B is a schematic top view of another integrated circuit provided by the embodiment of the present application.
  • Figure 7C is a sectional view along the C1-C2 direction in Figure 7B;
  • FIG. 8 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • FIG. 9A is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 9B is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 9C is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 10A is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 10B is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 10C is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application.
  • a semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; among them, a semiconductor includes intrinsic semiconductors and impurity semiconductors.
  • a semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an extrinsic semiconductor.
  • the impurity doped in the impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons), and the impurity semiconductor that provides electron impurities (such as pentavalent phosphorus) is also called an electronic semiconductor or N (negative, negative) type semiconductors, doping impurity semiconductors that provide hole impurities (such as trivalent boron elements) are also called hole type semiconductors or P (positive, positive) type semiconductors, doping can improve the intrinsic semiconductor Conductivity, generally the higher the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity.
  • a layer structure in a device made of a semiconductor (or semiconductor material) is called a semiconductor layer.
  • At least one (layer) means one (layer) or multiple (layers), and “multiple (layers)” means two (layers) or more than two (layers).
  • At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • at least one (unit) of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be It can be single or multiple.
  • Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • An embodiment of the present application provides an electronic device, which can be, for example, different types of user equipment such as lidar drivers, lasers, detectors, radars, and 5G (the 5th generation mobile network, fifth-generation mobile communication technology) communication equipment. or a terminal device; the electronic device may also be a network device such as a base station. The electronic device may also be a device such as a power amplifier used in the above-mentioned electronic device.
  • the embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.
  • FIG. 1A shows a schematic structural diagram of a mobile phone 100 .
  • the mobile phone 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, Mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, earphone jack 170D, sensor module 180, camera 190 and display screen 191, etc.
  • a processor 110 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, Mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, earphone jack 170D, sensor module 180, camera 190 and
  • the structure shown in the embodiment of the present application does not constitute a specific limitation on the mobile phone 100 .
  • the mobile phone 100 may include more or fewer components than shown in the figure, or combine certain components, or separate certain components, or arrange different components.
  • the illustrated components can be realized in hardware, software or a combination of software and hardware.
  • the processor 110 may include one or more processing units, for example: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural network processor (neural-network processing unit, NPU), etc. Wherein, different processing units may be independent devices, or may be integrated in one or more processors.
  • application processor application processor, AP
  • modem processor graphics processing unit
  • GPU graphics processing unit
  • image signal processor image signal processor
  • ISP image signal processor
  • controller video codec
  • digital signal processor digital signal processor
  • baseband processor baseband processor
  • neural network processor neural-network processing unit
  • a memory may also be provided in the processor 110 for storing instructions and data.
  • the memory in processor 110 is a cache memory.
  • the memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to use the instruction or data again, it can be directly recalled from the memory. Repeated access is avoided, and the waiting time of the processor 110 is reduced, thereby improving the efficiency of the system.
  • processor 110 may include one or more interfaces.
  • the interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transmitter (universal asynchronous receiver/transmitter, UART) interface, mobile industry processor interface (mobile industry processor interface, MIPI), general-purpose input and output (general-purpose input/output, GPIO) interface, subscriber identity module (subscriber identity module, SIM) interface, and /or universal serial bus (universal serial bus, USB) interface, etc.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • PCM pulse code modulation
  • UART universal asynchronous transmitter
  • MIPI mobile industry processor interface
  • GPIO general-purpose input and output
  • subscriber identity module subscriber identity module
  • SIM subscriber identity module
  • USB universal serial bus
  • the charging management module 140 is configured to receive a charging input from a charger.
  • the charger may be a wireless charger or a wired charger.
  • the charging management module 140 can receive charging input from the wired charger through the USB interface 130 .
  • the charging management module 140 can receive wireless charging input through the wireless charging coil of the mobile phone 100 . While the charging management module 140 is charging the battery 142 , it can also provide power for the mobile phone through the power management module 141 .
  • the power management module 141 is used for connecting the battery 142 , the charging management module 140 and the processor 110 .
  • the power management module 141 receives the input from the battery 142 and/or the charging management module 140 to provide power for the processor 110 , the internal memory 121 , the display screen 191 , the camera 190 , and the wireless communication module 160 .
  • the power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle times, and battery health status (leakage, impedance).
  • the power management module 141 may also be disposed in the processor 110 .
  • the power management module 141 and the charging management module 140 may also be set in the same device.
  • the wireless communication function of the mobile phone 100 can be realized by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor.
  • Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals.
  • Each antenna in handset 100 can be used to cover single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization of the antennas.
  • Antenna 1 can be multiplexed as a diversity antenna of a wireless local area network.
  • the antenna may be used in conjunction with a tuning switch.
  • the mobile communication module 150 can provide wireless communication solutions including 2G/3G/4G/5G applied on the mobile phone 100 .
  • the mobile communication module 150 may include one or more filters, switches, power amplifiers, low noise amplifiers (low noise amplifier, LNA) and the like.
  • the mobile communication module 150 can receive electromagnetic waves through the antenna 1, filter and amplify the received electromagnetic waves, and send them to the modem processor for demodulation.
  • the mobile communication module 150 can also amplify the signals modulated by the modem processor, and convert them into electromagnetic waves through the antenna 1 for radiation.
  • at least part of the functional modules of the mobile communication module 150 may be set in the processor 110 .
  • at least part of the functional modules of the mobile communication module 150 and at least part of the modules of the processor 110 may be set in the same device.
  • a modem processor may include a modulator and a demodulator.
  • the modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal.
  • the demodulator is used to demodulate the received electromagnetic wave signal into a low frequency baseband signal. Then the demodulator sends the demodulated low-frequency baseband signal to the baseband processor for processing.
  • the low-frequency baseband signal is passed to the application processor after being processed by the baseband processor.
  • the application processor outputs sound signals through audio equipment (not limited to speaker 170A, receiver 170B, etc.), or displays images or videos through display screen 191 .
  • the modem processor may be a stand-alone device.
  • the modem processor may be independent of the processor 110, and be set in the same device as the mobile communication module 150 or other functional modules.
  • the wireless communication module 160 can provide wireless local area networks (wireless local area networks, WLAN) (such as wireless fidelity (Wireless Fidelity, Wi-Fi) network), bluetooth (bluetooth, BT), global navigation satellite system, etc. applied on the mobile phone 100 (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field communication technology (near field communication, NFC), infrared technology (infrared, IR) and other wireless communication solutions.
  • the wireless communication module 160 may be one or more devices integrating one or more communication processing modules.
  • the wireless communication module 160 receives electromagnetic waves via the antenna 2 , frequency-modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110 .
  • the wireless communication module 160 can also receive the signal to be sent from the processor 110 , frequency-modulate it, amplify it, and convert it into electromagnetic waves through the antenna 2 for radiation.
  • the antenna 1 of the mobile phone 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the mobile phone 100 can communicate with the network and other devices through wireless communication technology.
  • the wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and/or IR technology, etc.
  • the GNSS can include global positioning system (global positioning system, GPS), global navigation satellite system (global navigation satellite system, GLONASS), Beidou satellite navigation system (beidou navigation satellite system, BDS), quasi-zenith satellite system (quasi- zenith satellite system (QZSS) and/or satellite based augmentation systems (SBAS).
  • global positioning system global positioning system, GPS
  • global navigation satellite system global navigation satellite system
  • GLONASS global navigation satellite system
  • Beidou satellite navigation system beidou navigation satellite system, BDS
  • quasi-zenith satellite system quasi-zenith satellite system
  • QZSS quasi-zenith satellite system
  • SBAS satellite based augmentation systems
  • the mobile phone 100 realizes the display function through the GPU, the display screen 191 , and the application processor.
  • the GPU is a microprocessor for image processing, and is connected to the display screen 191 and the application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering.
  • Processor 110 may include one or more GPUs that execute program instructions to generate or change display information.
  • the display screen 191 is used to display images, videos and the like.
  • the display screen 191 includes a display panel.
  • the display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active matrix organic light emitting diode or an active matrix organic light emitting diode (active-matrix organic light emitting diode, AMOLED), flexible light-emitting diode (flex light-emitting diode, FLED), Miniled, MicroLed, Micro-oLed, quantum dot light emitting diodes (quantum dot light emitting diodes, QLED), etc.
  • the mobile phone 100 may include 1 or N display screens 191 , where N is a positive integer greater than 1.
  • the mobile phone 100 can realize the shooting function through ISP, camera 190 , video codec, GPU, display screen 191 and application processor.
  • the ISP is used for processing data fed back by the camera 190 .
  • the light is transmitted to the photosensitive element of the camera through the lens, and the optical signal is converted into an electrical signal, and the photosensitive element of the camera transmits the electrical signal to the ISP for processing, and converts it into an image visible to the naked eye.
  • ISP can also perform algorithm optimization on image noise, brightness, and skin color. ISP can also optimize the exposure, color temperature and other parameters of the shooting scene.
  • the ISP may be located in the camera 190 .
  • Camera 190 is used to capture still images or video.
  • the object generates an optical image through the lens and projects it to the photosensitive element.
  • the photosensitive element can be a charge coupled device (charge coupled device, CCD) or a complementary metal-oxide-semiconductor (complementary metal-oxide-semiconductor, CMOS) phototransistor.
  • CCD charge coupled device
  • CMOS complementary metal-oxide-semiconductor
  • the photosensitive element converts the light signal into an electrical signal, and then transmits the electrical signal to the ISP to convert it into a digital image signal.
  • the ISP outputs the digital image signal to the DSP for processing.
  • DSP converts digital image signals into standard RGB, YUV and other image signals.
  • the mobile phone 100 may include 1 or N cameras 190 , where N is a positive integer greater than 1.
  • the external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the mobile phone 100.
  • the external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function. Such as saving music, video and other files in the external memory card.
  • the internal memory 121 may be used to store one or more computer programs including instructions.
  • the processor 110 may execute the above-mentioned instructions stored in the internal memory 121 to make the mobile phone 100 execute various functional applications and data processing.
  • the internal memory 121 may include an area for storing programs and an area for storing data.
  • the stored program area can store an operating system; the stored program area can also store one or more application programs (such as a gallery, contacts, etc.) and the like.
  • the data storage area can store data (such as photos, contacts, etc.) created during the use of the mobile phone 100 .
  • the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, universal flash storage (universal flash storage, UFS) and the like.
  • the processor 110 executes instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor, so that the mobile phone 100 executes various functional applications and data processing.
  • the mobile phone 100 can realize the audio function through the audio module 170 , the speaker 170A, the receiver 170B, the microphone 170C, the earphone interface 170D, and the application processor. Such as music playback, recording, etc.
  • the audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signal.
  • the audio module 170 may also be used to encode and decode audio signals.
  • the audio module 170 may be set in the processor 110 , or some functional modules of the audio module 170 may be set in the processor 110 .
  • Speaker 170A also referred to as a "horn" is used to convert audio electrical signals into sound signals.
  • Cell phone 100 can listen to music through speaker 170A, or listen to hands-free calls.
  • Receiver 170B also called “earpiece” is used to convert audio electrical signals into sound signals.
  • the receiver 170B can be placed close to the human ear to listen to the voice.
  • the microphone 170C also called “microphone” or “microphone” is used to convert sound signals into electrical signals.
  • the user can put his mouth close to the microphone 170C to make a sound, and input the sound signal to the microphone 170C.
  • Cell phone 100 may be provided with one or more microphones 170C.
  • the mobile phone 100 can be provided with two microphones 170C, which can also implement a noise reduction function in addition to collecting sound signals.
  • the mobile phone 100 can also be provided with three, four or more microphones 170C to realize the collection of sound signals, noise reduction, identification of sound sources, and realization of directional recording functions, etc.
  • the earphone interface 170D is used for connecting wired earphones.
  • the earphone interface 170D can be a USB interface 130, or a 3.5mm open mobile terminal platform (OMTP) standard interface, or a cellular telecommunications industry association of the USA (CTIA) standard interface.
  • OMTP open mobile terminal platform
  • CTIA cellular telecommunications industry association of the USA
  • the sensor module 180 may include a pressure sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.
  • a touch sensor is also referred to as a "touch device”.
  • the touch sensor can be arranged on the display screen 191, and the touch sensor and the display screen 191 form a touch screen, also called “touch screen”.
  • the touch sensor is used to detect a touch operation on or near it.
  • the touch sensor can pass the detected touch operation to the application processor to determine the type of touch event.
  • Visual output related to the touch operation may be provided through the display screen.
  • a touch panel with a touch sensor array formed by a plurality of touch sensors may also be installed on the surface of the display panel in a hanging form.
  • the location of the touch sensor and the display screen 191 may also be different.
  • the form of the touch sensor is not limited, for example, it may be a capacitor or a piezoresistor.
  • the mobile phone 100 may further include one or more components such as keys, motors, indicators, and a subscriber identification module (subscriber identification module, SIM) card interface, which is not limited in this embodiment of the present application.
  • SIM subscriber identification module
  • the electronic equipment provided by the embodiments of the present application is a 5G base station
  • the 5G base station can be divided into a base band processing unit (base band unit, BBU)-active antenna unit (active antenna unit, AAU), a centralized unit-distribution unit (central unit-distribute unit, CU-DU)-AAU, BBU-radio remote unit (remote radio unit, RRU)-antenna, CU-DU-RRU-Antenna, integrated 5G base station (5G node base station , gNB)- and other different architectures.
  • base band unit base band unit
  • AAU active antenna unit
  • CU-DU central unit-distribute unit
  • BBU-radio remote unit remote radio unit
  • RRU remote radio unit
  • FIG. 1B illustrates a base station 200 with a BBU-RRU architecture.
  • the base station 200 may include a BBU21, an RRU22, and an antenna 23; wherein the BBU21 and the RRU22 are connected through optical fibers, and the interface between the two is based on an open common public radio interface (common public radio interface, CPRI) and an open base station architecture (open base station architecture initiative, OBSAI).
  • the BBU21 sends the generated baseband signal to the antenna 23 for transmission after being processed by the RRU22.
  • the RRU 22 includes a digital intermediate frequency module 221 , a transceiver module 222 , a power amplifier 223 (power amplifier, PA) and a filter 224 .
  • the digital intermediate frequency module 221 is used for the modulation and demodulation of the baseband signal transmitted by optical fiber, digital up-down conversion, digital to analog converter (digital to analog converter, D/A), etc. to form an intermediate frequency signal;
  • the transceiver module 222 completes the conversion of the intermediate frequency signal to the radio frequency Signal conversion;
  • the power amplifier 223 is used to amplify the power of the low-power radio frequency signal;
  • the filter 224 is used to filter the radio frequency signal, and then transmit the radio frequency signal through the antenna 23 .
  • the embodiment of the present application also provides a power amplifier circuit, which can be applied to the mobile communication module 150 or the power amplifier of the wireless communication module 160 in the mobile phone 100 shown in FIG. 1A, and can also be applied to the RRU22 in the base station 200 shown in FIG. 1B. in the power amplifier.
  • a power amplifier circuit which can be applied to the mobile communication module 150 or the power amplifier of the wireless communication module 160 in the mobile phone 100 shown in FIG. 1A, and can also be applied to the RRU22 in the base station 200 shown in FIG. 1B. in the power amplifier.
  • specific application scenarios are not limited to the mobile phone 100 shown in FIG. 1A and the base station 200 shown in FIG. 1B above. It can be understood that any of the above-mentioned electronic devices that need to use a power amplification circuit in a power amplifier to amplify a signal belongs to the application scenarios of the embodiments of the present application.
  • a power amplifier circuit 30 is shown in FIG. 1C .
  • the power amplifying circuit 30 includes an integrated circuit 31 and a packaging structure 32 , wherein the integrated circuit 31 is packaged inside the packaging structure 32 .
  • a specific package structure of the power amplifier circuit 30 is provided, and the integrated circuit 31 is packaged in the package structure 32 of the power amplifier circuit 30 .
  • the package structure 32 specifically includes: a heat dissipation substrate 321, wherein in order to improve the conductivity and heat dissipation of the heat dissipation substrate 321, the heat dissipation substrate 321 can be made of a composite material, such as a laminate formed of copper Cu/molybdenum Mo/copper Cu structure.
  • the integrated circuit 31 is bonded or directly welded on the heat dissipation substrate 321 by sintering silver.
  • the integrated circuit 31 includes at least one transistor, and some electrodes of the transistor (for example, the source S) are connected to the heat dissipation substrate 321 to realize the source S being grounded. Some electrodes of the transistor (such as the drain D and the gate G) are connected to the pins through gold wire bonding, and the pins are arranged on an insulating layer (such as insulating ceramics), and the insulating layer is bonded to the insulating layer by an insulating adhesive. on the heat dissipation substrate 321 .
  • some electrodes of the transistor for example, the source S
  • Some electrodes of the transistor are connected to the pins through gold wire bonding, and the pins are arranged on an insulating layer (such as insulating ceramics), and the insulating layer is bonded to the insulating layer by an insulating adhesive. on the heat dissipation substrate 321 .
  • the package structure 32 includes a package package 322, the package package 322 is bonded to the heat dissipation substrate 321 through an insulating adhesive, and one end of the pin is exposed from the package structure to connect to other circuits, wherein the integrated circuit 31 is arranged on the package package 322 and the space surrounded by the heat dissipation substrate 321.
  • a high electron mobility transistor (HEMT) device is a semiconductor device that is widely used due to its advantages of high breakdown electric field, high channel electron concentration, high electron mobility, and high temperature stability. as a transistor in the integrated circuit 31.
  • HEMT high electron mobility transistor
  • the integrated circuit 31 is a circuit structure in a power amplifier circuit
  • the length of the ground wire will be increased, resulting in an increase in inductance.
  • a back hole structure is usually used, and the source of the HEMT device is directly connected to the back ground of the HEMT device through the back hole. In this way, the overlapping of the source, gate and drain leads and the length of the grounding line can be reduced, and the parasitic capacitance and inductance of the HEMT device can be reduced.
  • the design of the back hole will increase the width of the source (source, S), thereby affecting the overall size of the HEMT device. Therefore, how to reduce the size of the source under the back hole structure, so as to reduce the influence of the size of the source on the size of the HEMT device, has become a technical problem to be solved by those skilled in the art.
  • the back hole in the active area is to set one or more back hole structures under the source;
  • the back hole in the passive area is to connect multiple sources, collect them in one passive area, and then place them in the passive area.
  • the back hole in the active area is to set one or more back hole structures under the source;
  • the back hole in the passive area is to connect multiple sources, collect them in one passive area, and then place them in the passive area.
  • the embodiment of the present application provides an integrated circuit 31.
  • the integrated circuit 31 includes a plurality of HEMT devices.
  • the back hole in the HEMT device is located outside the source S, and the back hole is located outside the source electrode S. Below the pad, make a back hole in the passive area to lead the source S of the HEMT device to the back ground.
  • the size of the source S can be set as required without increasing the area of the source S due to the existence of the back hole. Reduce the size of HEMT devices.
  • the structure of the back hole is provided in the passive area, and the source S in multiple HEMT devices needs to be electrically connected to the source lead-out pad. Therefore, in the area where the source S and the gate (gate, G) intersect, it is necessary to pass a dielectric bridge (the area where the source S and the gate G intersect is provided with a dielectric layer, and the source S on both sides of the gate G passes through the dielectric layer The bridge on the bridge is electrically connected) or the air bridge (the source S jumps up at the crossing area of the source S and the gate G, leaving a gap between the source S and the gate G) to make the source S Across the intersection area, it is electrically connected to the source lead-out pad.
  • a dielectric bridge the area where the source S and the gate G intersect is provided with a dielectric layer, and the source S on both sides of the gate G passes through the dielectric layer
  • the bridge on the bridge is electrically connected
  • the air bridge the source S jumps up at the crossing area of the source S and the gate G,
  • the back hole is located under the source S, which can reduce the signal transmission path to the source S and reduce the inductance of the HEMT device.
  • the material of the source S usually contains active metals, such as aluminum and other elements. Therefore, there are two main process problems in the fabrication process of HEMT devices. Firstly, in the process of forming the back hole by back etching, the source S cannot block the etching of the back hole, and the back hole etching cannot stay on the lower surface of the source S. Secondly, the wet etching in the back hole process will cause the metal of the source S to be corroded. Therefore, as shown in FIG. 2C (the cross-sectional view along the A1-A2 direction in FIG.
  • openings will be provided on the source S, and the direction from the source S to the drain D is defined as the width direction (first direction X), It is necessary to ensure that the width M1 of the opening is greater than the width M2 of the back hole, so as to avoid contact with the source S during the back hole process, thereby avoiding damage to the source S by the back hole process. That is to say, the contour of the opening surrounds the contour of the back hole, and there is a gap L between the contour of the opening and the contour of the back hole.
  • the slits L everywhere (for example, the slits L1 and L2 on the left and right sides in FIG. 2C ) can be the same or different. In order to ensure that the source S is not damaged, usually, the value of the gap L is within the range of 500nm-50000nm.
  • the width M of the source S is equal to the width M1 of the opening+the width of the non-opening
  • the thickened source it is necessary to form a thickened source on the source S, and the thickened source does not form an ohmic contact with the barrier layer.
  • the width M1 of the opening is reduced by reducing the width M2 of the back hole, thereby reducing the size of the source S.
  • reducing the width M2 of the back hole will increase the aspect ratio of the back hole and increase the process difficulty of forming the back hole. Moreover, reducing the width M2 of the back hole will increase the difficulty of forming the back conductive layer covering the surface of the back hole and contacting the source S, which will affect the yield and reliability of the back conductive layer, thereby affecting the yield and reliability of the HEMT device. sex.
  • another HEMT device structure is provided to solve the problem of large source S size.
  • the structure of the HEMT device will be described below with several examples.
  • the embodiment of the present application provides an integrated circuit 31.
  • the integrated circuit 31 includes a plurality of HEMT devices.
  • the back hole in the HEMT device is located below the source S, and the back hole is made in the active area to connect the HEMT device.
  • the source S leads to the back ground.
  • FIG. 3B the cross-sectional view along the B1-B2 direction in FIG. 3A .
  • the width M2 of the back hole has nothing to do with the width M of the source S. That is to say, increasing the width M2 of the back hole does not necessarily increase the width M of the source S, as long as the width M2 of the back hole is smaller than the width M of the source. In this way, the width M2 of the back hole can be designed to be large enough without necessarily increasing the size of the source S.
  • the preparation method of the HEMT device includes:
  • the stacked semiconductor layers on the substrate 41 include a nucleation layer, a graded buffer layer, a channel layer 42 , an insertion layer, a barrier layer 43 and a cap layer arranged in a stack.
  • the channel layer 42 and the barrier layer 43 form a heterojunction, and a two-dimensional electron gas (two-dimensional electron gas, 2DEG) 44 is generated above the channel layer 42 .
  • 2DEG two-dimensional electron gas
  • step S10 includes:
  • the substrate 41 may be, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a sapphire substrate, or a diamond substrate, etc., and the embodiment of the present application does not limit the material of the substrate 41 .
  • the nucleation layer is formed on the substrate 41 , that is, the nucleation layer is provided on the substrate 41 as shown in FIG. 5A .
  • a nucleation layer is provided on the surface of the substrate 41 .
  • the method for forming the nucleation layer may be, for example, metal-organic chemical vapor deposition (MOCVD) growth method or molecular beam epitaxy (molecular beam epitaxy, MBE) growth method.
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the material of the nucleation layer may include one or more of GaN (gallium nitride), AlGaN (aluminum gallium nitride), and AlN (aluminum nitride).
  • the role of the nucleation layer is to improve the quality of the epitaxy, which is beneficial to the growth of the upper epitaxy.
  • a graded buffer layer is formed on the side of the nucleation layer away from the substrate 41 .
  • the graded buffer layer is disposed on the side of the nucleation layer away from the substrate 41 .
  • the graded buffer layer is disposed on the surface of the nucleation layer away from the substrate 41 .
  • the method of forming the graded buffer layer can adopt the MOCVD process to epitaxially grow the AlGaN graded layer whose Al (aluminum) composition gradually decreases.
  • an Al 0.8 Ga 0.2 N layer, an Al 0.5 Ga 0.5 N layer, and an Al 0.2 Ga 0.8 N layer are sequentially formed on the side of the nucleation layer away from the substrate 41 by MOCVD process to form a graded buffer layer.
  • the graded buffer layer in order to reduce the decrease in mobility caused by electron scattering, the graded buffer layer generally adopts an undoped structure.
  • the function of the graded buffer layer is that the band gap between the graded buffer layer and the channel layer 42 is different, which can make the potential well depth of the heterojunction formed by the barrier layer 43 and the channel layer 42 deeper, thereby improving the two-dimensional electron gas limit.
  • the buffer layer is generally thicker and is the main structure for the device to withstand voltage.
  • the channel layer 42 is formed on the side of the graded buffer layer away from the substrate 41 .
  • both the nucleation layer and the graded buffer layer are formed on the substrate 41 . Therefore, the channel layer 42 formed on the side of the graded buffer layer away from the substrate 41 is also located on the substrate 41 .
  • the method of forming the channel layer 42 may be, for example, MOCVD growth method or MBE growth method.
  • the material of the channel layer 42 may include, for example, one or more of GaN, AlGaN, InAlN (indium aluminum nitride), AlN, ScAlN (scandium aluminum nitride).
  • the thickness of the channel layer 42 ranges from 100 nm to 5000 nm.
  • the thickness of the channel layer 42 is 500nm, 1000nm, 1500nm, 2000nm, 2500nm, 3000nm, 3500nm, 4000nm, 4500nm.
  • an insertion layer is formed on the side of the channel layer 42 away from the substrate 41 . That is to say, as shown in FIG. 5A , the insertion layer is disposed on the side of the channel layer 42 away from the substrate 41 .
  • the insertion layer is disposed on the surface of the channel layer 42 away from the substrate 41 for improving the mobility of the two-dimensional electron gas 44 .
  • the method of forming the insertion layer for example, can use MOCVD growth method or MBE growth method.
  • the barrier layer 43 is formed on the side of the insertion layer away from the substrate 41 . That is to say, as shown in FIG. 5A , the barrier layer 43 is disposed on the side of the insertion layer away from the substrate 41 .
  • the barrier layer 43 is provided on the surface of the insertion layer away from the substrate 41 .
  • the method of forming the barrier layer 43 may be, for example, MOCVD growth method or MBE growth method.
  • the material of the barrier layer 43 may include, for example, one or more of GaN, AlGaN, InAlN, AlN, and ScAlN.
  • the materials of the channel layer 42 and the barrier layer 43 are different, and the channel layer 42 and the barrier layer 43 form a heterostructure.
  • the material of the channel layer 42 includes GaN
  • the material of the barrier layer 43 includes AlGaN.
  • the thickness of the barrier layer 43 is in the range of 2 nm ⁇ 50 nm.
  • the barrier layer 43 is AlGaN with a thickness of 25 nm and a composition of 25% aluminum.
  • the thickness of the barrier layer 43 is 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm.
  • the barrier layer 43 is usually not doped, and the barrier layer with unidirectional flow capacity is formed under the gate by utilizing the work function difference between it and the subsequently formed gate (usually a metal material). While improving the ability of the gate to control the channel layer 42, it can also effectively reduce the leakage problem of the gate.
  • a cap layer is formed on the side of the barrier layer 43 away from the substrate 41 .
  • the cap layer is disposed on the side of the barrier layer 43 away from the substrate 41 .
  • the cap layer is disposed on the surface of the barrier layer 43 away from the substrate 41 .
  • the method of forming the cap layer may adopt MOCVD growth method or MBE growth method to form the cap layer.
  • the material of the cap layer may be GaN or Si 3 N 4 (silicon nitride). It can be understood that the setting of the cap layer should not affect the ohmic contact between the source and drain electrodes and the barrier layer 43 , and the above effects can be achieved by doping or patterning the cap layer (exposing the barrier layer 43 ).
  • the thickness of the cap layer is too small to protect the barrier layer 43 . Too much cap layer thickness will increase the thickness of the HEMT device. Therefore, in some embodiments, the thickness of the cap layer may be in the range of 1 nm ⁇ 20 nm, for example. For example, the thickness of the cap layer is 5 nm, 10 nm, or 15 nm.
  • the stacked semiconductor layers on the substrate 41 include a nucleation layer, a graded buffer layer, a channel layer 41 , an insertion layer, a barrier layer 43 and a cap layer.
  • the embodiment of the present application does not limit that the above-mentioned steps S11-S16 must be performed when forming stacked semiconductor layers, and only some of the steps may be performed, or other steps may be added, as long as at least the formation including A heterostructure of the channel layer 42 and the barrier layer 43 is sufficient.
  • the uppermost layer is the cap layer, and the source electrode 45 and the drain electrode 46 are formed on the cap layer.
  • the uppermost layer is the barrier layer 43 , and the source 45 and the drain 46 are formed on the barrier layer 43 . Regardless of the structure, it is sufficient to ensure that the source electrode 45 and the drain electrode 46 are in ohmic contact with the barrier layer 43 .
  • S20 includes:
  • photoresist can be coated on the stacked semiconductor layer first, and a light-shielding plate (reticle mask) is used to block the photoresist.
  • the shape of the light-shielding plate is as shown in FIG. 5B, which will be formed soon. Areas of electrodes (such as source electrodes and drain electrodes) are set as light-transmitting areas, and other areas are light-impermeable areas. Then, after the coated photoresist is cured, the photoresist in the light-transmitting region is activated by irradiating the light-shielding plate with light, and the photoresist in the light-transmitting region is removed to form source openings and drain openings.
  • a light-shielding plate reticle mask
  • the photoresists mentioned in the specific implementation manners of the examples of the present application are all positive photoresists, that is, the photoresist can be activated after being illuminated, and then the activated photoresist can be removed.
  • negative photoresists can also be used in actual operations. It should be noted that negative photoresists will not be activated after being illuminated, and will be activated without illumination. Therefore, when negative photoresist is used, the light-transmitting area and the opaque area of the light-shielding plate in the illustration need to be exchanged, that is, the original light-transmitting area becomes an opaque area, and the original opaque area becomes an opaque area. into a light-transmitting area, and the other steps remain unchanged. Whether positive photoresist or negative photoresist is used, all belong to the protection scope of the embodiments of the present application.
  • the ion implantation process can be used to implant the donor impurity through the opening of the source and the opening of the drain.
  • the donor impurity may be, for example, silicon ions, and the donor impurity may be a single element or a mixture of multiple elements.
  • the implantation of donor impurities can reduce the resistivity of the ohmic contact resistance between the source electrode 45 and the drain electrode 46 and the barrier layer 43 , and can also reduce the resistivity of the barrier layer 43 .
  • the carriers of the implanted donor impurity can also be activated by an annealing process in subsequent fabrication of other film layers.
  • the metal film can be fabricated by using a metal deposition process, a sputtering process, an evaporation process or an electroplating process.
  • the material of the source electrode 45 and the drain electrode 46 may be a single substance, or an alloy or a multi-layer laminated metal.
  • the work function of the material of the source 45 and the drain 46 is in the range of 4.3eV ⁇ 6eV.
  • the material of the source electrode 45 and the drain electrode 46 includes at least one of titanium (Ti, with a work function of 4.33eV), gold (Au, with a work function of 5.1eV), and platinum (Pt, with a work function of 5.65eV) .
  • the material of the source electrode 45 and the drain electrode 46 includes titanium nitride.
  • the material of the source electrode 45 and the drain electrode 46 does not contain aluminum (Al) element.
  • source 45 and drain 46 include at least one conductive layer.
  • the source electrode 45 and the drain electrode 46 include a conductive layer, and the material of the conductive layer may include titanium, gold, platinum and other elements.
  • the source electrode 45 and the drain electrode 46 have a single-layer structure, the preparation process is simple, and the production efficiency is high.
  • the source electrode 45 and the drain electrode 46 include multiple conductive layers, and the material of each conductive layer may be the same or different.
  • the source electrode 45 and the drain electrode 46 include multiple conductive layers, which can integrate properties of different materials, so that the stress and resistivity of the source electrode 45 and the drain electrode 46 can be adjusted.
  • the source electrode 45 and the drain electrode 46 can also include a conductive layer acting as a barrier to block the diffusion between multi-layer metals, thereby preventing the volume expansion of the source electrode 45 and the drain electrode 46 and causing damage to the HEMT device.
  • the material of the conductive layer may include titanium element, for example.
  • the source 45 and the drain 46 include multiple conductive layers
  • the source 45 includes a first conductive layer and a second conductive layer stacked in sequence
  • the first conductive layer includes titanium
  • the second conductive layer includes gold element
  • the first conductive layer is in contact with the barrier layer 43 .
  • the titanium element is arranged on the surface of the stacked semiconductor layer (such as the barrier layer 43), which can not only play a conductive role, but also play a role in adhesion, and improve the connection effect between the source electrode 45 and the drain electrode 46 and the stacked semiconductor layer. .
  • the thickness of each conductive layer in the source electrode 45 and the drain electrode 46 is in the range of 1 nm ⁇ 10000 nm.
  • the thickness of the conductive layer is 100nm, 500nm, 1000nm, 1500nm, 2000nm, 2500nm, 3000nm, 3500nm, 4000nm, 4500nm, 5000nm, 6000nm, 7000nm, 8000nm, 9000nm.
  • the thicknesses of the conductive layers of each layer may be equal or unequal, which is not limited in this embodiment of the present application, and may be set reasonably as required.
  • the resistance of the source electrode 45 and the drain electrode 46 can be reduced without setting auxiliary electrodes, the structure is simple, the process steps are few, and the manufacturing efficiency is high.
  • the source electrode 45 and the drain electrode 46 are arranged on the surface of the stacked semiconductor layer (such as the barrier layer 43), and the source electrode 45 is the conductive structure closest to the stacked semiconductor layer (such as the barrier layer 43). .
  • the source 45 and the drain 46 are the first conductive structure disposed on the stacked semiconductor layer (eg, the barrier layer 43 ), and no other conductive structures are disposed between them.
  • the source 45 is a planar structure.
  • the source electrode 45 is not provided with structures such as openings or hollow patterns.
  • the source electrode 45 has a planar structure with a simple structure and a simple manufacturing process. Moreover, there is no need to consider the issue of how to interconnect the multiple striped structures after the source electrode 45 is divided into structures including multiple striped patterns by providing openings on the source electrode 45 .
  • the material of the gate 49 may be, for example, a metal with a high work function.
  • the material of the gate 49 may be nickel (the work function of Ni is 4.6 eV), gold, etc., and the gate 49 is disposed on the barrier layer 43 to form a Schottky contact with the barrier layer 43 .
  • step S30 includes:
  • the material of the first dielectric layer 47 may be, for example, an insulating medium such as silicon nitride, silicon oxide, aluminum oxide, or the like.
  • the thickness of the first dielectric layer 47 may be in the range of 10 nm ⁇ 200 nm.
  • the thickness of the first dielectric layer 47 is 50nm, 100nm, 150nm.
  • the first dielectric layer 47 can be formed by plasma chemical vapor deposition, atomic layer deposition, low pressure chemical vapor deposition and other processes.
  • the first dielectric layer 47 formed in step S31 may expose the source electrode 45 and the drain electrode 46 as shown in FIG. 5C .
  • the first dielectric layer 47 formed in step S31 may also cover the source electrode 45 and the drain electrode 46 , and then be patterned in other subsequent steps to expose the source electrode 45 and the drain electrode 46 .
  • the way of forming the gate opening 48 can form a photoresist on the first dielectric layer 47 as a mask to expose the gate opening 48; then use an etching process (dry etching or wet etching), A gate opening 48 is formed; the photoresist is then removed.
  • etching process dry etching or wet etching
  • the process of forming the gate opening 48 on the first dielectric layer 47 can expose the source electrode 45 and the drain electrode with the first dielectric layer 47.
  • the process of 46 is completed synchronously, and can also be completed in batches.
  • the size of the gate opening 48 defines the size of the gate 49 to be formed.
  • the gate opening 48 is a groove.
  • the groove width of the groove is in the range of 10nm-1000nm.
  • the groove width of the groove is 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm.
  • the process for forming the gate 49 may be, for example, the same as the process for forming the source 45 and the drain 46 , and reference may be made to the above description.
  • the gate opening 48 on the first dielectric layer 47 is located between the source 45 and the drain 46 , and the finally formed gate 49 is also located between the source 45 and the drain 46 .
  • the source electrode 45 and the drain electrode 46 can be formed at the same time first, and then the gate electrode 49 can be formed. It is also possible to form the gate 49 first, and then form the source 45 and the drain 46 at the same time. It is also possible to form the source 45, the drain 46, and the gate 49 at the same time.
  • the material of the field plate 51 may be any conductive material.
  • the field plate 51 is arranged on the side of the gate 49 away from the substrate 41, above the region between the gate 49 and the drain 46.
  • the orthographic projection of the field plate 51 on the substrate 41 is the same as that of the gate 49 on the substrate 41. Orthographic projection overlay.
  • step S40 includes:
  • the material of the second dielectric layer 50 may be, for example, an insulating medium such as silicon nitride, silicon oxide, aluminum oxide, or the like.
  • the thickness of the second dielectric layer 50 may be in the range of 50 nm ⁇ 1000 nm.
  • the thickness of the second dielectric layer 50 is 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm.
  • the second dielectric layer 50 can be formed by plasma chemical vapor deposition, atomic layer deposition, low pressure chemical vapor deposition and other processes.
  • the second dielectric layer 50 formed in step S41 may expose the source electrode 45 and the drain electrode 46 as shown in FIG. 5D .
  • the second dielectric layer 50 formed in step S41 may also cover the source electrode 45 and the drain electrode 46 , and then be patterned in other subsequent steps to expose the source electrode 45 and the drain electrode 46 .
  • the method for forming the field plate 51 may be the same as the method for forming the source electrode 45 and the drain electrode 46 above, and reference may be made to the above description.
  • the field plate 51 may be in a suspended state without loading any signal.
  • the field plate 51 may also be in contact with the source 45 , and the field plate 51 may also be in contact with the gate 49 .
  • the electric field distribution in the HEMT device can be modulated to make the electric field distribution uniform and avoid electric field peaks.
  • the thickened source electrode 52 is disposed on the source electrode 45 and is in contact with the source electrode 45 .
  • the thickened drain 53 is disposed on the drain 46 and is in contact with the drain 46 .
  • the materials of the thickened source electrode 52 and the thickened drain electrode 53 are not limited, and may be the same as or different from those of the source electrode 45 and the drain electrode 46 .
  • the preparation method of the thickened source electrode 52 and the thickened drain electrode 53 may also be the same as that of the source electrode 45 and the drain electrode 46 , and reference may be made to the relevant description above.
  • the thicknesses of the thickened source electrode 52 and the thickened drain electrode 53 may be, for example, within a range of 500 nm ⁇ 10000 nm.
  • the thicknesses of the thickened source electrode 52 and the thickened drain electrode 53 are 1000 nm, 2000 nm, 3000 nm, 4000 nm, 5000 nm, 6000 nm, 7000 nm, 8000 nm, 9000 nm.
  • the thickened source electrode 52 and thickened drain electrode 53 By setting the thickened source electrode 52 and thickened drain electrode 53, it is equivalent to increasing the thickness of the source electrode 45 and the drain electrode 46, reducing the resistance of the source electrode 45 and the drain electrode 46, thereby improving the current conduction capability of the semiconductor device .
  • the size of the thickened source 52 and the thickened drain 53 is not required to be the same as the size of the source 45 and the drain 46, and can be larger or smaller than the size of the source 45 and the drain 46. To improve the role of current conduction ability.
  • a passivation layer including a dielectric material
  • a waterproof layer including a waterproof material
  • the back hole 54 penetrates from the substrate 41 to the region of the barrier layer 43 below the source 45 .
  • the back hole 54 penetrates from the back surface of the substrate 41 away from the channel layer 42 to the surface of the source 45 close to the substrate 41 . That is to say, the back hole 54 penetrates through the stacked semiconductor layers on the substrate 41 to reach the surface of the source 45 close to the substrate 41 .
  • step S70 includes:
  • the process on the back side of the substrate 41 needs to be performed to realize the connection of the source 45 through the back side of the device.
  • the requirement for the load-bearing capacity of the substrate 41 is reduced. Therefore, before the back hole 54 is formed on the substrate 41, the substrate 41 may be thinned first. On the one hand, the difficulty of forming the back hole 54 can be reduced, and on the other hand, the thickness of the final semiconductor device can be reduced.
  • the thickness of the thinned substrate 41 is in the range of 10 um-500 um.
  • the thickness of the substrate 41 after thinning is 100 um, 200 um, 300 um, 400 um.
  • the film layer on the side of the source electrode 45 close to the substrate 41 may be the substrate 41 and stacked semiconductor layers disposed on the substrate 41 .
  • the photoresist is first coated on the back side of the substrate 41; then the photoresist is exposed through the mask; area; then use a dry etching process or a wet etching process to open a hole in the film layer on the side of the source electrode 45 close to the substrate 41 to form a back hole 54; then remove the photoresist.
  • the substrate 41 can be used as a mask.
  • the width of the back hole 54 can be set larger, even equal to the width of the source electrode 45, so as to reduce the difficulty of preparing the back hole 54 and the subsequent back metal layer.
  • the embodiment of the present application does not limit the size of the back hole 54 , and it can be reasonably selected after comprehensively considering the process and other factors.
  • step of removing the photoresist may be removed during step S72, or may be removed after step S73.
  • the etchant for wet etching may include, for example, hydrochloric acid, nitric acid, potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and other solutions.
  • the back conductive layer 56 covers the surface of the back hole 54 and the back of the substrate 41 ; the source 45 is in direct contact with the back conductive layer 56 .
  • the material of the back conductive layer 56 may include gold, titanium gold, etc., for example.
  • the thickness of the back conductive layer 56 may be, for example, within a range of 500 nm to 30000 nm.
  • the back conductive layer 56 can be prepared by, for example, an electroplating process, an evaporation process or a sputtering process.
  • the method for manufacturing a semiconductor device provided in the embodiment of the present application is not limited to the above-mentioned steps, and other steps may be added or some of the above-mentioned steps may be reduced as required.
  • the order of the steps in the above preparation method is only an illustration, and can be adjusted and changed as needed.
  • the semiconductor device prepared by the above-mentioned preparation method includes: a substrate 41; a channel layer 42 and a barrier layer 43 sequentially stacked on the substrate 41, and the channel layer 42 and the barrier layer 43 A heterojunction is formed, and a two-dimensional electron gas 44 is generated in the channel layer 43; the source electrode 45 and the drain electrode 46 are arranged on the surface of the barrier layer 43, forming an ohmic contact with the barrier layer 43, and the source electrode 45 is planar structure, the source 45 is the conductive structure closest to the barrier layer 43; the gate 49 is arranged on the barrier layer 43, between the source 45 and the drain 46; the field plate 51 is arranged on the gate 49 away from the substrate 41 One side, located between the gate 49 and the drain 46 , overlaps the projection of the gate 49 .
  • the back hole 54 is located below the source 45, and the back hole 45 penetrates from the back of the substrate 41 away from the channel layer 42 to the surface of the source 45 close to the substrate 41; the back conductive layer 56 is arranged on the back of the substrate 41, through the back The hole 54 is in contact with the source 45 .
  • the semiconductor device further includes a thickened source 52 and a thickened drain 53 , the thickened source 52 is disposed on the source 45 and is in contact with the source 45 .
  • the thickened drain 53 is disposed on the drain 46 and is in contact with the drain 46 .
  • the semiconductor device further includes a nucleation layer and a graded buffer layer sequentially stacked between the substrate 41 and the channel layer 42, and between the channel layer 41 and the barrier layer 43. The insertion layer between them, and the cap layer arranged on the surface of the barrier layer 43 .
  • a cap layer is provided between the source electrode 45 and the drain electrode 46 and the barrier layer 43 .
  • the cap layer is provided with openings exposing the source 45 and the drain 46 , and the source 45 and the drain 46 are in direct contact with the barrier layer 43 .
  • the working principle of the HEMT device is as follows: the source 45 and the drain 46 respectively form conductive ohmic contacts with the barrier layer 43 , and the gate 49 forms a Schottky contact with the barrier layer 43 .
  • the dotted line in the channel layer 42 represents the 2DEG44 generated by polarization in the heterojunction formed by the channel layer 42 and the barrier layer 43 in the HEMT device.
  • the 2DEG44 is used to efficiently conduct electrons under the action of an electric field.
  • the source 45 and the drain 46 are used to make the 2DEG44 flow in the channel layer 42 between the source 45 and the drain 46 under the action of the electric field, and the conduction between the source 45 and the drain 46 occurs in the channel 2DEG44 in layer 42.
  • the gate 49 is disposed between the source 45 and the drain 46 and is used to allow or block the passage of the 2DEG 44 to control the HEMT device to be turned on or off.
  • the back conductive layers 56 of the multiple HEMT devices included in the integrated circuit 31 are contacted and connected. Or, in some embodiments, among the multiple HEMT devices included in the integrated circuit 31 , the conductive layer 56 on the back side of some HEMT devices is contact-connected. Alternatively, in some embodiments, among the multiple HEMT devices included in the integrated circuit 31 , the back conductive layers 56 of the respective HEMT devices are independent from each other.
  • the source electrode 45 is directly in ohmic contact with the barrier layer 43 , and the back hole 54 is located below the source electrode 45 .
  • the back hole 54 is disposed under the source electrode 45
  • the back conductive layer 56 is directly connected to the source electrode 45 through the back hole 54 .
  • the signal directly contacts the back conductive layer 56 from the source 45 , so that the transmission path to the source 45 is shorter, which can reduce the inductance of the semiconductor device and increase the frequency of the semiconductor device.
  • the width of the back hole 54 can be reasonably set according to needs without additional reduction of the width of the back hole 54, so as to reduce the difficulty and yield of the preparation process of the back hole 54, improve the yield and reliability of the back conductive layer 56, and improve the semiconductor performance.
  • Device yield and reliability Therefore, the size of the device source 45 is reduced, so that a small-sized, low-cost semiconductor device can be manufactured.
  • the material of the source electrode 45 as a metal with high work function and chemical stability (for example, including titanium, gold, platinum), no active metal (such as aluminum) will be included.
  • the source electrode 45 can block the etching of the back hole, and can also avoid corrosion in the wet process of the back hole process.
  • an alloy method or a method of process improvement may also be used, so that the source electrode 45 will not be corroded due to etching during the manufacturing process of the back hole 54 .
  • the source electrode 45 even if the source electrode 45 is touched in the back hole process, the source electrode 45 will not be damaged. Therefore, there is no need to intentionally separate the source electrode 45 from the back hole 54 in order to avoid the corrosion caused by the back hole process, thereby reducing the size of the source electrode 45 and thus reducing the size of the overall semiconductor device.
  • the difference between the second example and the first example is that the source 45 has an opening.
  • the source electrode 45 in the semiconductor device is no longer a planar structure, but has an opening 451 located above the back hole 54 .
  • the shape of the opening 451 is not limited, and the shape of the opening 451 in FIG. 7A is only for illustration.
  • the source 45 has an opening 451 , but the setting of the opening 451 should not affect the transmission of signals on the source 45 .
  • the source 45 has an opening 451 , but the source 45 is still interconnected everywhere.
  • the opening 451 on the source electrode 45 divides the source electrode 45 into a plurality of strip structures.
  • the strip The structure can be interconnected by thickening the source electrode 52, for example. That is to say, each part of the source electrode 45 is in contact with the thickened source electrode 52 to realize the interconnection of each part of the source electrode 45 .
  • the semiconductor device further includes a thickened source 52 and a thickened drain 53 .
  • the thickened source electrode 52 is in contact with the back conductive layer 56 through the opening 451 on the source electrode 45 .
  • the width M1 of the opening 451 is smaller than or equal to the width M2 of the back hole 54 .
  • the width M1 of the opening 451 is less than or equal to the width M2 of the back hole 54, which is equivalent to reducing the width M1 of the opening 451, thereby reducing the size of the source 45 width.
  • the structural relationship between the source 45 and the back conductive layer 56 is brought.
  • the back conductive layer 56 has a left side close to the gate 49 and a side far away from the gate 49. On the right side, the back conductive layer 56 is in contact with the source electrode 45 on the left and/or right side.
  • the left side and the right side of the back conductive layer 56 are in critical contact with the source 45 .
  • the left side of the back conductive layer 56 is in critical contact with the source 45 , and there is a gap between the right side of the back conductive layer 56 and the source 45 .
  • the opening 451 has no gap between the left side and the back hole 54 , and the opening 451 has a gap between the right side and the back hole 54 .
  • the left side of the back conductive layer 56 just overlaps the source 45 , and there is a gap between the right side of the back conductive layer 56 and the source 45 .
  • the opening 451 has no gap between the left side and the back hole 54 , and the opening 451 has a gap between the right side and the back hole 54 .
  • the left side of the back conductive layer 56 is overlapped with the source 45 , and the right side of the back conductive layer 56 is in critical contact with the source 45 .
  • the right side of the back conductive layer 56 is in critical contact with the source 45 , and there is a gap between the left side of the back conductive layer 56 and the source 45 .
  • the opening 451 has no gap between the right side and the back hole 54 , and the opening 451 has a gap between the left side and the back hole 54 .
  • the right side of the back conductive layer 56 just overlaps the source 45 , and there is a gap between the left side of the back conductive layer 56 and the source 45 .
  • the opening 451 has no gap between the right side and the back hole 54 , and the opening 451 has a gap between the left side and the back hole 54 .
  • the right side of the back conductive layer 56 is overlapped with the source 45 , and the left side of the back conductive layer 56 is in critical contact with the source 45 .
  • the right side of the back conductive layer 56 overlaps the source electrode 45
  • the left side of the back conductive layer 56 overlaps the source electrode 45 .
  • the back hole 54 is disposed under the source electrode 45 , and although the opening 451 is provided on the source electrode 45 , the source electrode 45 will not be corroded due to etching during the manufacturing process of the back hole 54 . That is to say, even if the source electrode 45 is touched in the back hole process, the source electrode 45 will not be damaged. Therefore, there is no need to set the opening on the source electrode 45 larger than the size of the back hole in order to avoid the corrosion caused by the back hole 54 process, that is, the width M1 of the opening 451 is less than or equal to the width M2 of the back hole 54, and the left side of the back hole 54 There is no gap between the side and/or right side and the opening 451 .
  • the back conductive layer 56 is in contact with the source 45 on the left side and/or the right side. Therefore, although the opening 451 is provided on the source 45 as needed, the size of the source 45 can be reduced by reducing the size of the opening 451 without increasing the size of the semiconductor device.
  • the semiconductor device provided in the embodiment of the present application is an example of a HEMT device, but it is not limited to the semiconductor device being a HEMT device.
  • the semiconductor device provided in the embodiment of the present application can be any semiconductor device whose source needs to be grounded .

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Abstract

本申请实施例提供一种半导体器件及其制备方法、功率放大电路、电子设备，涉及半导体技术领域，用于降低设置背孔对半导体器件带来的影响。半导体器件包括：衬底；沟道层和势垒层，依次层叠设置于衬底上；源极、栅极和漏极，设置于势垒层上；背孔，贯穿从衬底至源极下方的势垒层区域；背面导电层，覆盖于背孔和衬底的背面，源极与背面导电层接触连接。

Description

半导体器件及其制备方法、功率放大电路、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件及其制备方法、功率放大电路、电子设备。
背景技术
随着半导体科技的发展，具有热导率高、电子漂移速率高、耐高温、化学性质稳定的半导体器件，被广泛应用于高频、高温、微波领域。
例如，应用于功率放大电路等集成电路中时，半导体器件的源极需要接地。为了降低该半导体器件的寄生电容和电感，通常采用背孔结构，通过背孔将该半导体器件的源极连接到该半导体的背面，从而使该半导体器件的源极直接接地。
然而，现有技术中，在大功率器件中源极需要接地时，会将背孔设置在源极下方。这样一来，会增大源极的尺寸，从而影响半导体器件的尺寸和性能。因此，如何降低背孔的存在对半导体器件带来的影响，成为本领域技术人员当下需要解决的技术问题。
发明内容
本申请实施例提供一种半导体器件及其制备方法、功率放大电路、电子设备，用于降低设置背孔对半导体器件带来的影响。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种半导体器件，包括：衬底；沟道层和势垒层，依次层叠设置于衬底上；源极、栅极和漏极，设置于势垒层上；背孔，贯穿从衬底至源极下方的势垒层区域；背面导电层，覆盖于背孔和衬底的背面，源极与背面导电层接触连接。
本申请实施例中，源极直接与势垒层欧姆接触，背孔位于源极下方。这样一来，背孔设置在源极的下方，背面导电层通过背孔与源极直接接触连接。一方面，信号从源极直接接触到背面导电层，使得其传输至源极的路径更短，可减小半导体器件的电感，增大半导体器件的频率。另外，可以根据需要合理设置背孔的宽度，无需额外减小背孔的宽度，以降低背孔的制备工艺难度和良率、提高背面导电层的良率和可靠性，从而提高半导体器件的良率和可靠性。因此，减小了器件源极的尺寸，从而可以制备得到小尺寸、低成本的半导体器件。
在一些实施例中，源极的材料的功函数在4.3～6eV的区间范围内。通过将源极的材料选取为功函数高的、化学性质稳定的金属(例如包括钛、金、铂)或者包含元素的合金，不再包含活泼金属比如铝。在制备半导体器件的过程中，使得源极能够阻挡背孔的刻蚀，还能够避免背孔工艺湿法处理中的腐蚀。因此，即使背孔工艺中接触到源极，也不会对源极造成损坏。所以源极无需避开背孔，以制备得到上述半导体器件。制备工艺简单，无需增加工艺难度，易于实现。
在一些实施例中，源极的材料包括钛、金、铂元素中的至少一种。常用的几种金 属元素。
在一些实施例中，源极包括至少一层导电层。在源极包括一层导电层的情况下，结构简单，制备工艺简单。在源极包括多层导电层的情况下，可以将不同材料的特性融合到一起，使得源极的应力可调、电阻率可调。还能使源极中包括充当阻挡作用的导电层，用以阻挡多层金属之间的扩散，从而避免源极体积膨胀，导致半导体器件损坏。
在一些实施例中，源级包括依次堆叠第一导电层和第二导电层，第一导电层包括钛元素，第二导电层包括金元素，且第一导电层与势垒层接触连接。钛元素设置在堆叠半导体层(例如势垒层)的表面，在起到导电作用的同时，还可以起到粘附性的作用，提高源极和漏极与堆叠半导体层的连接效果。
在一些实施例中，每层导电层的厚度在1nm～10000nm的区间范围内。通过合理设置各层导电层的厚度，可以无需再通过设置辅助电极来减小源极和漏极的电阻，结构简单，工艺步骤少，制备效率高。
在一些实施例中，源极为面状结构。源极为面状结构，结构简单，制备工艺简单。而且，无需考虑在源极上设置开口，将源极划分为包括多个条状图案的结构后，多个条状结构如何互连的问题。
在一些实施例中，源极上具有开口；开口位于背孔上方。由于本申请实施例中，源极不会因为背孔的制作过程中的刻蚀导致被腐蚀，也就是说，即使背孔工艺中接触到源极，也不会对源极造成损坏。因此无需为了规避背孔工艺带来的腐蚀，而将源极上的开口设置的大于背孔的尺寸，从而降低了源极的尺寸，降低了整体的半导体器件的尺寸。
在一些实施例中，半导体器件还包括加厚源极；加厚源极设置在源极的表面。通过设置加厚源极，相当于增加了源极的厚度，减小了源极的电阻，从而提高半导体器件的电流导通能力。
在一些实施例中，半导体器件还包括加厚源极，加厚源极设置在源极的表面，加厚源极通过开口与背面导电层接触。
在一些实施例中，半导体器件还包括加厚漏极；加厚漏极设置在漏极的表面。通过设置加厚漏极，相当于增加了漏极的厚度，减小了漏极的电阻，从而提高半导体器件的电流导通能力。
在一些实施例中，半导体器件还包括场板；场板设置于栅极远离衬底一侧，位于栅极与漏极之间，与栅极的投影交叠。由于栅极位置处容易出现电场尖峰，通过在栅极上方设置场板，可以调制半导体器件内的电场分布，使电场分布均匀，避免出现电场尖峰。
第二方面，提供一种功率放大电路，包括封装结构以及如第一方面任一项的半导体器件，半导体器件封装于封装结构内部。
本申请实施例提供的功率放大电路包括第一方面的半导体器件，其有益效果与半导体器件的有益效果相同，此处不再赘述。
第三方面，提供一种电子设备，包括功率放大器及天线，功率放大器用于将射频信号放大后输出至天线向外辐射，功率放大器包括如第二方面的功率放大电路。
本申请实施例提供的电子设备包括第一方面的半导体器件，其有益效果与半导体器件的有益效果相同，此处不再赘述。
第四方面，提供一种半导体器件的制备方法，包括：在衬底上依次形成层叠设置的沟道层和势垒层；在势垒层上形成源极、栅极和漏极；在源极下方形成背孔；背孔贯穿从衬底至源极下方的势垒层区域；在衬底的背面形成背面导电层，背面导电层覆盖于背孔和衬底的背面；源极与背面导电层接触连接。
本申请实施例提供的半导体器件的制备方法，形成源极时，将源极的材料选取为功函数高的、化学性质稳定的金属(例如包括钛、金、铂)，不再包含活泼金属，通过调整制备工艺或者源极的材料，使源极直接与势垒层形成欧姆接触。在制备半导体器件的过程中，源极能够阻挡背孔的刻蚀，还能够避免背孔工艺湿法处理中的腐蚀。这样一来，最终形成的背孔设置在源极的下方，背面导电层通过背孔与源极直接接触连接。一方面，信号从源极直接接触到背面导电层，使得其传输至源极的路径更短，可减小半导体器件的电感，增大半导体器件的频率。另外，可以根据需要合理设置背孔的宽度，无需额外减小背孔的宽度，以降低背孔的制备工艺难度和良率、提高背面导电层的良率和可靠性，从而提高半导体器件的良率和可靠性。因此，减小了器件源极的尺寸，从而可以制备得到小尺寸、低成本的半导体器件。
在一些实施例中，在源极下方形成背孔，包括：从衬底的背面，采用干法刻蚀工艺对源极下方的膜层进行开孔，形成背孔；采用干法刻蚀或者湿法刻蚀去除残留在孔内的刻蚀副产物。
附图说明
图1A为本申请实施例提供的一种终端的框架示意图；
图1B为本申请实施例提供的一种基站的框架示意图；
图1C为本申请实施例提供的一种功率放大电路的框架示意图；
图2A为本申请实施例提供的一种集成电路的俯视示意图；
图2B为本申请实施例提供的另一种集成电路的俯视示意图；
图2C为沿图2B中A1-A2向的剖视图；
图3A为本申请实施例提供的又一种集成电路的俯视示意图；
图3B为沿图3A中B1-B2向的剖视图；
图4为本申请实施例提供的一种半导体器件的制备流程图；
图5A-图5G为本申请实施例提供的一种半导体器件的制备过程示意图；
图6A为本申请实施例提供的一种半导体器件的结构示意图；
图6B为本申请实施例提供的另一种半导体器件的结构示意图；
图6C为本申请实施例提供的又一种半导体器件的结构示意图；
图7A为本申请实施例提供的又一种集成电路的俯视示意图；
图7B为本申请实施例提供的又一种集成电路的俯视示意图；
图7C为沿图7B中C1-C2向的剖视图；
图8为本申请实施例提供的又一种半导体器件的结构示意图；
图9A为本申请实施例提供的又一种半导体器件的结构示意图；
图9B为本申请实施例提供的又一种半导体器件的结构示意图；
图9C为本申请实施例提供的又一种半导体器件的结构示意图；
图10A为本申请实施例提供的又一种半导体器件的结构示意图；
图10B为本申请实施例提供的又一种半导体器件的结构示意图；
图10C为本申请实施例提供的又一种半导体器件的结构示意图；
图11为本申请实施例提供的又一种半导体器件的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下对本申请的实施例中的技术术语说明如下：
半导体：半导体是一种常温下导电性能介于导体与绝缘体之间的材料；其中，半导体包括本征半导体和杂质半导体。不含杂质和缺陷的纯净半导体，其内部电子和空穴浓度相等，称为本征半导体。掺入一定量杂质的半导体称为杂质半导体或非本征半导体。其中，杂质半导体中掺入的杂质能够提供一定浓度的载流子(如空穴或电子)，其中掺杂提供电子杂质(如5价的磷元素)的杂质半导体也称作电子型半导体或N(negative，负)型半导体，掺杂提供空穴杂质(如3价的硼元素)的杂质半导体也称作空穴型半导体或P(positive，正)型半导体，掺杂能够改善本征半导体的导电性，通常载流子浓度越大，半导体的电阻率越低，导电性也越好。在本申请的实施例中，采用半导体(或者说采用半导体材料)制作的器件中的层结构称为半导体层。
以下，本申请实施例中，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“电性连接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“电性连接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“电性连接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
在本申请实施例中，“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存 在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。在本申请中，“至少一个(层)”是指一个(层)或者多个(层)，“多个(层)”是指两个(层)或两个(层)以上。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。
本申请实施例中参照作为理想化示例性附图的剖视图和/或平面图和/或等效电路图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本申请实施例提供一种电子设备，该电子设备例如可以为激光雷达驱动器、激光器、探测器、雷达、5G(the 5th generation mobile network，第五代移动通信技术)通信设备等不同类型的用户设备或终端设备；该电子设备也可以为基站等网络设备。电子设备也可以是用于上述电子设备中的功率放大器等装置。本申请实施例对上述电子设备的具体形式不做特殊限制。
示例性的，本申请实施例提供的电子设备为手机，图1A示出了一种手机100的结构示意图。手机100可以包括处理器110，外部存储器接口120，内部存储器121，通用串行总线(universal serial bus，USB)接口130，充电管理模块140，电源管理模块141，电池142，天线1，天线2，移动通信模块150，无线通信模块160，音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，传感器模块180，摄像头190以及显示屏191等。
可以理解的是，本申请的实施例示意的结构并不构成对手机100的具体限定。在本申请另一些实施例中，手机100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
处理器110可以包括一个或多个处理单元，例如：处理器110可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
处理器110中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器110中的存储器为高速缓冲存储器。该存储器可以保存处理器110刚用过或循环使用的指令或数据。如果处理器110需要再次使用该指令或数据，可从该存储器中直接 调用。避免了重复存取，减少了处理器110的等待时间，因而提高了系统的效率。
在一些实施例中，处理器110可以包括一个或多个接口。接口可以包括集成电路(inter-integrated circuit，I2C)接口，集成电路内置音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口，用户标识模块(subscriber identity module，SIM)接口，和/或通用串行总线(universal serial bus，USB)接口等。
充电管理模块140用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器。在一些有线充电的实施例中，充电管理模块140可以通过USB接口130接收有线充电器的充电输入。在一些无线充电的实施例中，充电管理模块140可以通过手机100的无线充电线圈接收无线充电输入。充电管理模块140为电池142充电的同时，还可以通过电源管理模块141为手机供电。
电源管理模块141用于连接电池142，充电管理模块140与处理器110。电源管理模块141接收电池142和/或充电管理模块140的输入，为处理器110，内部存储器121，显示屏191，摄像头190，和无线通信模块160等供电。电源管理模块141还可以用于监测电池容量，电池循环次数，电池健康状态(漏电，阻抗)等参数。在其他一些实施例中，电源管理模块141也可以设置于处理器110中。在另一些实施例中，电源管理模块141和充电管理模块140也可以设置于同一个器件中。
手机100的无线通信功能可以通过天线1，天线2，移动通信模块150，无线通信模块160，调制解调处理器以及基带处理器等实现。
天线1和天线2用于发射和接收电磁波信号。手机100中的每个天线可用于覆盖单个或多个通信频带。不同的天线还可以复用，以提高天线的利用率。例如：可以将天线1复用为无线局域网的分集天线。在另外一些实施例中，天线可以和调谐开关结合使用。
移动通信模块150可以提供应用在手机100上的包括2G/3G/4G/5G等无线通信的解决方案。移动通信模块150可以包括一个或多个滤波器，开关，功率放大器，低噪声放大器(low noise amplifier，LNA)等。移动通信模块150可以由天线1接收电磁波，并对接收的电磁波进行滤波，放大等处理，传送至调制解调处理器进行解调。移动通信模块150还可以对经调制解调处理器调制后的信号放大，经天线1转为电磁波辐射出去。在一些实施例中，移动通信模块150的至少部分功能模块可以被设置于处理器110中。在一些实施例中，移动通信模块150的至少部分功能模块可以与处理器110的至少部分模块被设置在同一个器件中。
调制解调处理器可以包括调制器和解调器。其中，调制器用于将待发送的低频基带信号调制成中高频信号。解调器用于将接收的电磁波信号解调为低频基带信号。随后解调器将解调得到的低频基带信号传送至基带处理器处理。低频基带信号经基带处理器处理后，被传递给应用处理器。应用处理器通过音频设备(不限于扬声器170A，受话器170B等)输出声音信号，或通过显示屏191显示图像或视频。在一些实施例中，调制解调处理器可以是独立的器件。在另一些实施例中，调制解调处理器可以独立于 处理器110，与移动通信模块150或其他功能模块设置在同一个器件中。
无线通信模块160可以提供应用在手机100上的包括无线局域网(wireless local area networks，WLAN)(如无线保真(wireless fidelity，Wi-Fi)网络)，蓝牙(bluetooth，BT)，全球导航卫星系统(global navigation satellite system，GNSS)，调频(frequency modulation，FM)，近距离无线通信技术(near field communication，NFC)，红外技术(infrared，IR)等无线通信的解决方案。无线通信模块160可以是集成一个或多个通信处理模块的一个或多个器件。无线通信模块160经由天线2接收电磁波，将电磁波信号调频以及滤波处理，将处理后的信号发送到处理器110。无线通信模块160还可以从处理器110接收待发送的信号，对其进行调频，放大，经天线2转为电磁波辐射出去。
在一些实施例中，手机100的天线1和移动通信模块150耦合，天线2和无线通信模块160耦合，使得手机100可以通过无线通信技术与网络以及其他设备通信。该无线通信技术可以包括全球移动通讯系统(global system for mobile communications，GSM)，通用分组无线服务(general packet radio service，GPRS)，码分多址接入(code division multiple access，CDMA)，宽带码分多址(wideband code division multiple access，WCDMA)，时分码分多址(time-division code division multiple access，TD-SCDMA)，长期演进(long term evolution，LTE)，BT，GNSS，WLAN，NFC，FM，和/或IR技术等。该GNSS可以包括全球卫星定位系统(global positioning system，GPS)，全球导航卫星系统(global navigation satellite system，GLONASS)，北斗卫星导航系统(beidou navigation satellite system，BDS)，准天顶卫星系统(quasi-zenith satellite system，QZSS)和/或星基增强系统(satellite based augmentation systems，SBAS)。
手机100通过GPU，显示屏191，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏191和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。处理器110可包括一个或多个GPU，其执行程序指令以生成或改变显示信息。
显示屏191用于显示图像，视频等。显示屏191包括显示面板。显示面板可以采用液晶显示屏(liquid crystal display，LCD)，有机发光二极管(organic light-emitting diode，OLED)，有源矩阵有机发光二极体或主动矩阵有机发光二极体(active-matrix organic light emitting diode，AMOLED)，柔性发光二极管(flex light-emitting diode，FLED)，Miniled，MicroLed，Micro-oLed，量子点发光二极管(quantum dot light emitting diodes，QLED)等。在一些实施例中，手机100可以包括1个或N个显示屏191，N为大于1的正整数。手机100可以通过ISP，摄像头190，视频编解码器，GPU，显示屏191以及应用处理器等实现拍摄功能。
ISP用于处理摄像头190反馈的数据。例如，拍照时，打开快门，光线通过镜头被传递到摄像头感光元件上，光信号转换为电信号，摄像头感光元件将电信号传递给ISP处理，转化为肉眼可见的图像。ISP还可以对图像的噪点，亮度，肤色进行算法优化。ISP还可以对拍摄场景的曝光，色温等参数优化。在一些实施例中，ISP可以设置在摄像头190中。
摄像头190用于捕获静态图像或视频。物体通过镜头生成光学图像投射到感光元件。感光元件可以是电荷耦合器件(charge coupled device，CCD)或互补金属氧化物半 导体(complementary metal-oxide-semiconductor，CMOS)光电晶体管。感光元件把光信号转换成电信号，之后将电信号传递给ISP转换成数字图像信号。ISP将数字图像信号输出到DSP加工处理。DSP将数字图像信号转换成标准的RGB，YUV等格式的图像信号。在一些实施例中，手机100可以包括1个或N个摄像头190，N为大于1的正整数。
外部存储器接口120可以用于连接外部存储卡，例如Micro SD卡，实现扩展手机100的存储能力。外部存储卡通过外部存储器接口120与处理器110通信，实现数据存储功能。例如将音乐，视频等文件保存在外部存储卡中。
内部存储器121可以用于存储一个或多个计算机程序，该一个或多个计算机程序包括指令。处理器110可以通过运行存储在内部存储器121的上述指令，从而使得手机100执行各种功能应用和数据处理等。内部存储器121可以包括存储程序区和存储数据区。其中，存储程序区可存储操作系统；该存储程序区还可以存储一个或多个应用程序(比如图库、联系人等)等。存储数据区可存储手机100使用过程中所创建的数据(比如照片，联系人等)等。此外，内部存储器121可以包括高速随机存取存储器，还可以包括非易失性存储器，例如一个或多个磁盘存储器件，闪存器件，通用闪存存储器(universal flash storage，UFS)等。在另一些实施例中，处理器110通过运行存储在内部存储器121的指令，和/或存储在设置于处理器中的存储器的指令，来使得手机100执行各种功能应用和数据处理。
手机100可以通过音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，以及应用处理器等实现音频功能。例如音乐播放，录音等。
音频模块170用于将数字音频信息转换成模拟音频信号输出，也用于将模拟音频输入转换为数字音频信号。音频模块170还可以用于对音频信号编码和解码。在一些实施例中，音频模块170可以设置于处理器110中，或将音频模块170的部分功能模块设置于处理器110中。
扬声器170A，也称“喇叭”，用于将音频电信号转换为声音信号。手机100可以通过扬声器170A收听音乐，或收听免提通话。
受话器170B，也称“听筒”，用于将音频电信号转换成声音信号。当手机100接听电话或语音信息时，可以通过将受话器170B靠近人耳接听语音。
麦克风170C，也称“话筒”，“传声器”，用于将声音信号转换为电信号。当拨打电话或发送语音信息时，用户可以通过人嘴靠近麦克风170C发声，将声音信号输入到麦克风170C。手机100可以设置一个或多个麦克风170C。在另一些实施例中，手机100可以设置两个麦克风170C，除了采集声音信号，还可以实现降噪功能。在另一些实施例中，手机100还可以设置三个，四个或更多麦克风170C，实现采集声音信号，降噪，还可以识别声音来源，实现定向录音功能等。
耳机接口170D用于连接有线耳机。耳机接口170D可以是USB接口130，也可以是3.5mm的开放移动电子设备平台(open mobile terminal platform，OMTP)标准接口，美国蜂窝电信工业协会(cellular telecommunications industry association of the USA，CTIA)标准接口。
传感器模块180可以包括压力传感器，陀螺仪传感器，气压传感器，磁传感器， 加速度传感器，距离传感器，接近光传感器，指纹传感器，温度传感器，触摸传感器，环境光传感器，骨传导传感器等。
在本申请的实施例中，触摸传感器，也称“触控器件”。触摸传感器可以设置于显示屏191，由触摸传感器与显示屏191组成触摸屏，也称“触控屏”。触摸传感器用于检测作用于其上或附近的触摸操作。触摸传感器可以将检测到的触摸操作传递给应用处理器，以确定触摸事件类型。可以通过显示屏提供与触摸操作相关的视觉输出。在另一些实施例中，也可以设置有多个触摸传感器形成的触控传感器阵列的触控面板以外挂形式设置于显示面板的表面。在另一些实施例中，触摸传感器也可以与显示屏191所处的位置不同。本申请的实施例中对触控传感器的形式不做限定，例如可以是电容、或压敏电阻等器件。
另外，上述手机100中还可以包括按键、马达、指示器以及用户标识模块(subscriber identification module，SIM)卡接口等一种或多种部件，本申请的实施例对此不做任何限制。
示例性的，本申请的实施例提供的电子设备为5G基站，5G基站可分为基带处理单元(base band unit，BBU)-有源天线单元(active antenna unit，AAU)、集中单元-分布单元(central unit-distribute unit，CU-DU)-AAU、BBU-射频拉远单元(remote radio unit，RRU)-天线(antenna)、CU-DU-RRU-Antenna、一体化5G基站(5G node base station，gNB)-等不同的架构。
图1B示例一种BBU-RRU架构的基站200。基站200可以包括BBU21、RRU22和天线23；其中BBU21与RRU22通过光纤连接，两者之间的接口是基于开放式通用公共射频接口(common public radio interface，CPRI)及开放式基站架构(open base station architecture initiative，OBSAI)。其中，BBU21将生成的基带信号通过RRU22处理后发送至天线23进行发射。RRU22包括数字中频模块221、收发信机模块222、功率放大器223(power amplifier，PA)以及滤波器224。其中，数字中频模块221用于光纤传输的基带信号的调制解调、数字上下变频、数字模拟转换(digital to analog converter，D/A)等形成中频信号；收发信机模块222完成中频信号到射频信号的变换；功率放大器223用于将小功率的射频信号进行功率放大；滤波器224用于对射频信号进行滤波，然后将射频信号通过天线23发射出去。
本申请实施例还提供一种功率放大电路，可以应用于图1A所示的手机100中移动通信模块150或无线通信模块160的功率放大器中，也可以应用于上述图1B所示的基站200中RRU22的功率放大器中。当然具体应用场景不限于上述图1A示出的手机100、图1B示出的基站200。可以理解的是，任意需要使用功率放大器中的功率放大电路对信号进行放大的上述电子设备均属于本申请的实施例的应用场景。
示例的，如图1C示意一种功率放大电路30。功率放大电路30包括集成电路31以及封装结构32，其中集成电路31封装于封装结构32内部。如图1C所示，提供了一种功率放大电路30的具体封装结构，集成电路31封装于功率放大电路30的封装结构32中。
如图1C所示，封装结构32具体包括：散热基板321，其中为了提高散热基板321的导电性以及散热性，散热基板321可以采用复合材料，例如铜Cu/钼Mo/铜Cu形成 的叠层结构。集成电路31通过烧结银粘接或者直接焊接在散热基板321上。
其中，该集成电路31包括至少一个晶体管，晶体管的部分电极(例如可以是源极S)与散热基板321导通，以实现源极S接地。晶体管的部分电极(例如漏极D和栅极G)通过金线引线键合连接到管脚，管脚设置在绝缘层(例如可以是绝缘陶瓷)上，绝缘层通过绝缘粘接剂粘接于散热基板321上。
此外，封装结构32包括封装管壳322，封装管壳322通过绝缘粘接剂与散热基板321粘接，并且管脚的一端从封装结构露出以连接其他电路，其中集成电路31设置于封装管壳322与散热基板321包围的空间中。
高电子迁移率晶体管(high electron mobility transistor，HEMT)器件是一种半导体器件，由于其具有高击穿电场、高沟道电子浓度、高电子迁移率和高温度稳定性等优点，因而被广泛用于作为集成电路31中的晶体管。下面以本申请实施例提供的半导体器件为HEMT器件为例进行示意说明。
在一些应用中(例如集成电路31为功率放大电路中的电路结构)，需要将HEMT器件的源极接地。由于从源极上方引出接地线，一方面，接地线会和HEMT器件中其他引线交叠而产生寄生电容；另一方面，如图1C所示，散热基板321位于HEMT器件背面，通过接地线引出至散热基板321上，会增加接地线的长度，导致电感增加。
因此，在一些实施例中，为了降低HEMT器件的寄生电容和电感，通常采用背孔结构，通过背孔将HEMT器件的源极直接连接到HEMT器件的背面接地。这样一来，可以减少源、栅、漏引线的相互交叠和接地线路长度，降低HEMT器件的寄生电容和电感。
与此同时，受工艺等因素的限制，背孔的设计，会导致源极(source，S)的宽度增大，从而影响HEMT器件的整体尺寸。因此，如何减小背孔结构下源极的尺寸，从而减小源极尺寸对HEMT器件尺寸的影响，成为本领域技术人员需要解决的技术问题。
根据背孔在HEMT器件中的位置，通常分为有源区背孔和无源区背孔。其中，有源区背孔是在源极下方设置一个或多个背孔结构；无源区背孔是通过将多个源极连接后，汇总在一个无源区位置，然后在无源区位置对应设置一个或多个背孔。
在一些实施例中，如图2A所示，本申请实施例提供一种集成电路31，集成电路31包括多个HEMT器件，HEMT器件中的背孔位于源极S外侧，背孔位于源极引出焊盘的下方，在无源区制作背孔将HEMT器件的源极S引到背面接地。
图2A所示的结构，由于背孔无需位于有源区源极S的下方，因此，可以根据需要设置源极S的大小，而无需因背孔的存在导致源极S的面积增大，可以降低HEMT器件的尺寸。
但是，如图2A所示，在无源区设置背孔的结构，多个HEMT器件中的源极S需要电性连接至源极引出焊盘。因此，在源极S与栅极(gate，G)交叉的区域，需要通过介质桥(源极S和栅极G交叉的区域处设置介质层，栅极G两侧的源极S通过介质层上的跨桥电性连接)或空气桥(源极S和栅极G交叉的区域处，源极S跳起，在源极S与栅极G之间留有间隙)的方式使源极S跨过交叉区域，电性连接至源极引出焊盘。
这就导致：一方面，HEMT器件中需要制作空气桥或者介质桥，工艺复杂。而且， 空气桥结构不稳定，在后续工艺中容易造成钝化层开裂。另一方面，源极S和栅极G交叉，会带来较大的寄生电容。再一方面，由于背孔设置在源极引出焊盘的下方，信号从源极引出焊盘传输至源极S的路径较长，会增大HEMT器件的电感，影响HEMT器件的频率特性。
基于此，为了降低HEMT器件的电感，在一些实施例中，如图2B所示，本申请实施例提供一种集成电路31，集成电路31包括多个HEMT器件，HEMT器件中的背孔位于源极S的下方，在有源区制作背孔将HEMT器件的源极S引到背面接地。
背孔位于源极S的下方，可减小信号传输至源极S的路径，减小HEMT器件的电感。
但是，由于源极S的材料中通常含有活泼金属，例如铝等元素。因此在HEMT器件的制作过程中存在两个主要的工艺问题。首先，在背面刻蚀形成背孔的过程中，源极S无法阻挡住背孔的刻蚀，背孔刻蚀无法停留在源极S的下表面。其次，背孔工艺中的湿法刻蚀会造成源极S的金属被腐蚀。因此，如图2C(沿图2B中A1-A2向的剖视图)所示，会在源极S上设置开口，定义从源极S到漏极D的方向为宽度方向(第一方向X)，需保证开口的宽度M1大于背孔的宽度M2，以避免背孔工艺中接触到源极S，从而避免背孔工艺对源极S的损坏。也就是说，开口的轮廓包围背孔的轮廓，开口的轮廓与背孔的轮廓之间具有缝隙L。各处的缝隙L(例如图2C中左右两侧的缝隙L1和L2)可以相同也可以不同。为了确保源极S不被破坏，通常情况下，缝隙L的在500nm～50000nm的区间范围内取值。
由于源极S的宽度M等于开口的宽度M1+非开口的宽度，因此，缝隙L的引入，会增大源极S上开口的宽度M1(M1＝M2+L1+L2)，从而增加HEMT器件的面积。而且，在源极S上形成开口后，为了阻挡背孔的刻蚀，需要在源极S上形成加厚源极，而加厚源极不与势垒层形成欧姆接触。
因此，为了减小源极S的宽度M1，在一些实施例中，通过减小背孔的宽度M2，来减小开口的宽度M1，从而减小源极S的尺寸。
但是，降低背孔的宽度M2，会增加背孔的深宽比，增加形成背孔的工艺难度。而且，降低背孔宽度M2，会增大覆盖在背孔表面，与源极S接触的背面导电层的形成难度，影响背面导电层的良率和可靠性，从而影响HEMT器件的良率和可靠性。
基于此，在一些实施例中，提供了一种其他的HEMT器件结构，来解决源极S尺寸大的问题。下面以几个示例，对HEMT器件的结构进行说明。
示例一
如图3A所示，本申请实施例提供一种集成电路31，集成电路31包括多个HEMT器件，HEMT器件中的背孔位于源极S的下方，在有源区制作背孔将HEMT器件的源极S引到背面接地。
其中，如图3B(沿图3A中B1-B2向的剖视图)所示，源极S上无需设置开口。
由于源极S上无需设置开口，也就不存在图2C中的缝隙L1和L2。因此，背孔的宽度M2与源极S的宽度M无关。也就是说，增大背孔的宽度M2不会必然的需要增加源极S的宽度M，只要背孔宽度M2的尺寸小于源极宽度M。这样一来，可以将背孔的宽度M2设计到足够大，又不会必然增加源极S的尺寸。
下面，示意一种制备图3B所示的HEMT器件的制备方法。
如图4所示，HEMT器件的制备方法，包括：
S10、如图5A所示，在衬底41上形成堆叠半导体层。
在一些实施例中，衬底41上的堆叠半导体层包括层叠设置的成核层、渐变缓冲层、沟道层42、插入层、势垒层43以及帽层。沟道层42和势垒层43形成异质结，沟道层42的上方产生二维电子气(two-dimensional electron gas，2DEG)44。
形成堆叠半导体层的方法，如图5A所示，步骤S10包括：
S11、在衬底41上形成成核层。
其中，衬底41例如可以是碳化硅(SiC)衬底、硅(Si)衬底、蓝宝石衬底或者金刚石衬底等，本申请实施例对衬底41的材料不做限定。
在衬底41上形成成核层，也就是说，如图5A所示，成核层设置在衬底41上。例如，成核层设置在衬底41的表面上。
形成成核层的方法，例如可以通过金属有机化合物化学气相沉淀(metal-organic chemical vapor deposition，MOCVD)生长法或分子束外延(molecular beam epitaxy，MBE)生长法等。
成核层的材料，例如，可以包括GaN(氮化镓)、AlGaN(铝镓氮)、AlN(氮化铝)中一种或多种。
成核层的作用是提高外延质量，利于上层外延的生长。
S12、在成核层上形成渐变缓冲层。
或者理解为，在成核层远离衬底41一侧形成渐变缓冲层。
也就是说，如图5A所示，渐变缓冲层设置在成核层远离衬底41一侧。例如，渐变缓冲层设置在成核层远离衬底41的表面上。
其中，形成渐变缓冲层的方法，例如可以采用MOCVD工艺外延生长Al(铝)组分逐渐降低的AlGaN渐变层。
示例的，通过MOCVD工艺，在成核层远离衬底41一侧依次形成Al 0.8Ga 0.2N层、Al 0.5Ga 0.5N层、Al 0.2Ga 0.8N层，以形成渐变缓冲层。
其中，为了减少电子的散射带来的迁移率降低，渐变缓冲层一般采用不掺杂的结构。
渐变缓冲层的作用是，渐变缓冲层和沟道层42的禁带宽度不同，可以使得势垒层43与沟道层42形成的异质结的势阱深度更深，从而提高二维电子气的限制。另外，缓冲层一般厚度较厚，是器件承受电压的主要结构。
S13、在渐变缓冲层上形成沟道层42。
或者理解为，在渐变缓冲层远离衬底41一侧形成沟道层42。
通过上述描述可知，成核层和渐变缓冲层均形成在衬底41上。因此，在渐变缓冲层远离衬底41一侧形成的沟道层42，也位于衬底41上。
其中，形成沟道层42的方法，例如可以通过MOCVD生长法或MBE生长法等。
沟道层42的材料例如可以包括GaN、AlGaN、InAlN(铟氮化铝)、AlN、ScAlN(钪氮化铝)中一种或多种。
在一些实施例中，沟道层42的厚度在100nm～5000nm的区间范围内。例如，沟道 层42的厚度为500nm、1000nm、1500nm、2000nm、2500nm、3000nm、3500nm、4000nm、4500nm。
S14、在沟道层42上形成插入层。
或者理解为，在沟道层42远离衬底41一侧形成插入层。也就是说，如图5A所示，插入层设置在沟道层42远离衬底41一侧。例如，插入层设置在沟道层42远离衬底41的表面上，用于提高二维电子气44的迁移率。
其中，形成插入层的方法，例如可以采用MOCVD生长法或MBE生长法等。
S15、在插入层上形成势垒层43。
或者理解为，在插入层远离衬底41一侧形成势垒层43。也就是说，如图5A所示，势垒层43设置在插入层远离衬底41一侧。例如，势垒层43设置在插入层远离衬底41的表面上。
其中，形成势垒层43的方法，例如可以通过MOCVD生长法或MBE生长法等。
势垒层43的材料例如可以包括GaN、AlGaN、InAlN、AlN、ScAlN中一种或多种。
其中，沟道层42和势垒层43的材料不相同，沟道层42和势垒层43构成异质结构。示例的，沟道层42的材料包括GaN，势垒层43的材料包括AlGaN。
在一些实施例中，势垒层43的厚度在2nm～50nm的区间范围内。例如，势垒层43为25nm厚，25％铝组分的AlGaN。例如，势垒层43的厚度为10nm、15nm、20nm、25nm、30nm、35nm、40nm、45nm。
其中，势垒层43往往是不掺杂的，利用其与后续形成的栅极(通常为金属材料)的功函数差，在栅极下方形成具有单向通流能力的势垒层，在保障了栅极控制沟道层42的能力的同时还能有效降低栅极的漏电问题。
S16、在势垒层43上形成帽层。
或者理解为，在势垒层43远离衬底41一侧形成帽层。如图5A所示，帽层设置在势垒层43远离衬底41一侧。例如，帽层设置在势垒层43远离衬底41的表面上。
其中，形成帽层的方法，例如可以采用MOCVD生长法或MBE生长法形成帽层。
帽层的材料，例如，可以为GaN或者Si 3N 4(氮化硅)。可以理解的是，帽层的设置应不影响源极和漏极与势垒层43的欧姆接触，可以通过掺杂或对帽层进行图案化(露出势垒层43)，来达到上述效果。
帽层的厚度太小，对势垒层43起不到保护作用。帽层厚度太大会增大HEMT器件的厚度。因此，在一些实施例中，帽层的厚度例如可以在1nm～20nm的区间范围内。例如帽层的厚度为5nm、10nm、15nm。
也就是说，如图5A所示，衬底41上的堆叠半导体层包括层叠设置的成核层、渐变缓冲层、沟道层41、插入层、势垒层43以及帽层。
但是，本申请实施例并不限定在形成堆叠半导体层时，上述步骤S11-S16都必须执行，可以仅执行其中的某些步骤，也可以再增加其他步骤，只要在衬底41上至少形成包括沟道层42和势垒层43的异质结构即可。
以下为了便于说明，如图5B所示，在后续过程中，仅以衬底41上形成的堆叠半导体层包括沟道层42和势垒层43为例进行示意。
S20、如图5B所示，在堆叠半导体层上形成源极45和漏极46。
例如，堆叠半导体层中，位于最上层的为帽层，则在帽层上形成源极45和漏极46。或者，例如，堆叠半导体层中，位于最上层的为势垒层43，则在势垒层43上形成源极45和漏极46。无论哪种结构，保证源极45和漏极46与势垒层43形成欧姆接触即可。
关于形成源极45和漏极46的方式，如图5B所示，S20包括：
S21、制作覆盖堆叠半导体层的光刻胶，并进行光刻，在待形成源极45的区域形成源极开窗，在待形成漏极46的区域形成漏极开窗。
示例的，参照图5B所示，可以首先在堆叠半导体层上涂覆光刻胶，并采遮光板(光罩mask)对光刻胶进行遮挡，遮光板的形状如图5B所示，即将形成电极(例如源极和漏极)的区域设置为透光区域，其余区域为不透光区域。那么，在涂覆的光刻胶固化之后，通过光线照射该遮光板对透光区域的光刻胶进行激活，并去除透光区域的光刻胶，形成源极开窗和漏极开窗。
需要注意的是本申请的实施例的具体实施方式中所提及的光刻胶均为正性光刻胶，即光照后可将光刻胶激活，然后去除激活的光刻胶。当然在现实的操作中也可以采用负性光刻胶，需要注意的是负性光刻胶是光照后不会被激活，没有光照的会被激活。所以在采用负性光刻胶的时候，图示中的遮光板的透光区域和不透光区域需要调换，即原来透光的区域变成不透光的区域，原来不透光的区域变成透光的区域，其他步骤不作更改。无论是使用正性光刻胶和负性光刻胶，均属于本申请的实施例的保护范围。
S22、通过源极开窗和漏极开窗注入施主杂质，激活后形成掺杂区。
其中，可以采用离子注入的工艺通过源极开窗和漏极开窗注入施主杂质。施主杂质例如可以是硅离子，施主杂质可以是单一元素也可以是多种元素的混合物。施主杂质的注入，可以降低源极45和漏极46与势垒层43的欧姆接触电阻的电阻率，还可以降低势垒层43的电阻率。
S23、去除光刻胶，通过退火工艺激活施主杂质的载流子，形成N型掺杂区。
当然，也可以采用后续其他膜层制作中的退火工艺对注入的施主杂质的载流子进行激活。
S24、再制作覆盖堆叠半导体层的光刻胶，并进行光刻，在待形成源极45的区域形成源极开窗，在待形成漏极46的区域形成漏极开窗。
S25、形成覆盖光刻胶的金属膜，金属膜填充源极开窗和漏极开窗。
例如，可以采用金属沉积工艺、溅射工艺、蒸镀工艺或者电镀工艺制作金属膜。
S26、去除光刻胶，保留位于源极开窗中的源极45，和位于漏极开窗中的漏极46。
其中，源极45和漏极46的材料可以是单质，也可以是合金或多层叠层金属。
在一些实施例中，源极45和漏极46的材料的功函数在4.3eV～6eV的区间范围内。
例如，源极45和漏极46的材料包括钛(Ti，功函数为4.33eV)、金(Au，功函数为5.1eV)、铂(Pt，功函数为5.65eV)元素中的至少一种。示例的，源极45和漏极46的材料包括氮化钛。
在一些实施例中，源极45和漏极46的材料不包含铝(Al)元素。
在一些实施例中，源极45和漏极46包括至少一层导电层。
示例的，源极45和漏极46包括一层导电层，该导电层的材料可以包括钛、金、铂等元素。源极45和漏极46为单层结构，制备工艺简单，生产效率高。
或者，示例的，源极45和漏极46包括多层导电层，每层导电层的材料可以相同，也可以不同。
源极45和漏极46包括多层导电层，可以将不同材料的特性融合到一起，使得源极45和漏极46的应力可调、电阻率可调。还能使源极45和漏极46中包括充当阻挡作用的导电层，用以阻挡多层金属之间的扩散，从而避免源极45和漏极46体积膨胀，导致HEMT器件损坏。
在一些实施例中，在源极45和漏极46包括一层导电层的情况下，该层导电层的材料例如可以包括钛元素。
在源极45和漏极46包括多层导电层的情况下，以源极45为例，例如，源级45包括依次堆叠第一导电层和第二导电层，第一导电层包括钛元素，第二导电层包括金元素，第一导电层与势垒层43接触连接。
钛元素设置在堆叠半导体层(例如势垒层43)的表面，在起到导电作用的同时，还可以起到粘附性的作用，提高源极45和漏极46与堆叠半导体层的连接效果。
综合考虑源极45和漏极46的应力以及电阻率后，在一些实施例中，源极45和漏极46中每层导电层的厚度在1nm～10000nm的区间范围内。例如，导电层的厚度为100nm、500nm、1000nm、1500nm、2000nm、2500nm、3000nm、3500nm、4000nm、4500nm、5000nm、6000nm、7000nm、8000nm、9000nm。
当然，各层导电层的厚度可以相等，也可以不相等，本申请实施例对此不做限定，根据需要合理设置即可。
通过合理设置各层导电层的厚度，可以无需再通过设置辅助电极来减小源极45和漏极46的电阻，结构简单，工艺步骤少，制备效率高。
其中，如图5B所示，源极45和漏极46设置在堆叠半导体层(例如势垒层43)的表面上，源极45为最靠近堆叠半导体层(例如势垒层43)的导电结构。
或者理解为，源极45和漏极46为设置在堆叠半导体层(例如势垒层43)上的第一层导电结构，二者之间未设置其他导电结构。
在一些实施例中，如图5B所示，源极45为面状结构。
或者理解为，源极45上未设置开口或者镂空图案等结构。
源极45为面状结构，结构简单，制备工艺简单。而且，无需考虑在源极45上设置开口，将源极45划分为包括多个条状图案的结构后，多个条状结构如何互连的问题。
S30、如图5C所示，形成位于源极45和漏极46之间的栅极49。
其中，栅极49的材料例如可以是高功函数金属。示例的，栅极49的材料例如可以是镍(Ni功函数为4.6eV)、金等，栅极49设置于势垒层43上，与势垒层43形成肖特基接触。
在一些实施例中，如图5C所示，步骤S30包括：
S31、在源极45和漏极46上形成第一介质层47。
其中，第一介质层47的材料，例如可以是氮化硅、氧化硅、氧化铝等绝缘介质。第一介质层47的厚度可以在10nm～200nm的区间范围内。例如，第一介质层47的厚 度为50nm、100nm、150nm。
例如，可以通过等离子体化学气相沉积、原子层沉积、低压化学气相沉积等工艺形成第一介质层47。
需要说明的是，步骤S31中形成的第一介质层47，如图5C所示，可以是露出源极45和漏极46。步骤S31中形成的第一介质层47也可以覆盖源极45和漏极46，在后续其他步骤中再进行图案化，以露出源极45和漏极46。
S32、在第一介质层47上形成栅极开窗48。
形成栅极开窗48的方式，例如可以在第一介质层47上形成光刻胶作为掩膜，露出栅极开窗48；然后采用刻蚀工艺(干法刻蚀或湿法刻蚀)，形成栅极开窗48；然后去除光刻胶。
其中，在第一介质层47露出源极45和漏极46的情况下，在第一介质层47上形成栅极开窗48的过程，可以和第一介质层47露出源极45和漏极46的过程同步完成，也可以分次完成。
其中，栅极开窗48的大小，限定了待形成的栅极49的尺寸。在一些实施例中，栅极开窗48为凹槽。凹槽的槽宽在10nm-1000nm的区间范围内。例如，凹槽的槽宽为100nm、200nm、300nm、400nm、500nm、600nm、700nm、800nm、900nm。
S33、形成栅极49。
形成栅极49的工艺，例如，可以和形成源极45和漏极46的工艺相同，可参考上述描述。第一介质层47上的栅极开窗48位于源极45和漏极46之间，最终形成的栅极49也位于源极45和漏极46之间。
需要说明的是，本申请实施例中，可以如上述步骤所示，先同时形成源极45和漏极46，再形成栅极49。也可以先形成栅极49，再同时形成源极45和漏极46。还可以同时形成源极45、漏极46和栅极49。
S40、如图5D所示，形成场板(field plate，FP)51。
其中，场板51的材料可以为任意导电材料。场板51设置于栅极49远离衬底41一侧，位于栅极49与漏极46之间的区域上方，场板51在衬底41上的正投影与栅极49在衬底41上的正投影交叠。
在一些实施例中，如图5D所示，步骤S40包括：
S41、形成第二介质层50。
其中，第二介质层50的材料，例如可以是氮化硅、氧化硅、氧化铝等绝缘介质。第二介质层50的厚度可以在50nm～1000nm的区间范围内。例如，第二介质层50的厚度为100nm、200nm、300nm、400nm、500nm、600nm、700nm、800nm、900nm。
例如，可以通过等离子体化学气相沉积、原子层沉积、低压化学气相沉积等工艺形成第二介质层50。
需要说明的是，步骤S41中形成的第二介质层50，如图5D所示，可以是露出源极45和漏极46。步骤S41中形成的第二介质层50也可以覆盖源极45和漏极46，在后续其他步骤中再进行图案化，以露出源极45和漏极46。
S42、形成场板51。
形成场板51的方法，可以与上述形成源极45和漏极46的方法相同，可参考上述 描述。
其中，场板51可以为悬浮状态，不加载任何信号。场板51也可以与源极45接触连接，场板51还可以与栅极49接触连接。
由于栅极49位置处容易出现电场尖峰，通过在栅极49上方设置场板51，可以调制HEMT器件内的电场分布，使电场分布均匀，避免出现电场尖峰。
S50、如图5E所示，形成加厚源极52和加厚漏极53。
加厚源极52设置在源极45上，与源极45接触连接。加厚漏极53设置在漏极46上，与漏极46接触连接。
不对加厚源极52和加厚漏极53的材料进行限定，可以与源极45和漏极46的材料相同，也可以不同。加厚源极52和加厚漏极53的制备方式，也可以与源极45和漏极46的制备方式相同，可参考上述相关描述。
加厚源极52和加厚漏极53的厚度，例如，可以在500nm～10000nm的区间范围内。例如，加厚源极52和加厚漏极53的厚度为1000nm、2000nm、3000nm、4000nm、5000nm、6000nm、7000nm、8000nm、9000nm。
通过设置加厚源极52和加厚漏极53，相当于增加了源极45和漏极46的厚度，减小了源极45和漏极46的电阻，从而提高半导体器件的电流导通能力。但值得注意的是，加厚源极52和加厚漏极53的大小不要求与源极45和漏极46大小相同，可以大于也可以小于源极45和漏极46的大小，都可以起到提高电流导通能力的作用。
S60、对器件进行外围钝化层或防水层沉积。
也就是说，在器件的外围包裹钝化层(包括介质材料)或者防水层(包括防水材料)，对器件进行保护。
S70、如图5F所示，在源极45下方形成背孔54。
其中，背孔54贯穿从衬底41至源极45下方的势垒层43区域。或者理解为，背孔54从衬底41远离沟道层42的背面贯穿至源极45靠近衬底41的表面。也就是说，背孔54贯穿衬底41上的堆叠半导体层到达源极45靠近衬底41的表面。
在一些实施例中，如图5F所示，步骤S70包括：
S71、对衬底41进行背面减薄。
衬底41正面的工艺结束后，需要进行衬底41背面的工艺，以实现源极45通过器件的背面连接。衬底41正面工艺完成后，对衬底41的承载能力要求降低。因此，在衬底41上形成背孔54之前，可先对衬底41进行减薄。一方面可降低背孔54的形成难度，另一方面可以减小最终形成的半导体器件的厚度。
在一些实施例中，减薄后衬底41的厚度在10um～500um的区间范围内。例如，减薄后衬底41的厚度为100um、200um、300um、400um。
S72、从衬底41的背面，对源极45靠近衬底41一侧的膜层进行开孔，形成背孔54。
其中，源极45靠近衬底41一侧的膜层，可以是衬底41和设置在衬底41上的堆叠半导体层。
例如，先在衬底41的背面涂覆光刻胶；然后通过掩膜版对光刻胶进行曝光；然后对光刻胶进行显影，以光刻胶作为掩膜，露出待形成背孔54的区域；然后采用干法刻 蚀工艺或者湿法刻蚀工艺，在源极45靠近衬底41一侧的膜层上开孔，形成背孔54；然后去除光刻胶。
当然，也可以是形成金属层掩膜层，或者介质掩膜层等其他掩膜层作为开孔掩膜。另外，在刻蚀衬底41上的堆叠半导体层时，可以以衬底41作为掩膜。
其中，背孔54的宽度可以设置的较大，甚至可以和源极45的宽度相等，以降低背孔54和后续背面金属层的制备难度。本申请实施例不对背孔54的大小进行限定，综合考虑工艺等因素后，合理选择即可。
S73、采用干法刻蚀或者湿法刻蚀去除残留在背孔54内的刻蚀副产物55。
其中，去除光刻胶的步骤，可以在步骤S72时去除，也可以在步骤S73后去除。
湿法刻蚀的刻蚀液，例如可以包括盐酸、硝酸、氢氧化钾(KOH)、四甲基氢氧化铵(TMAH)等溶液。
S80、如图5G所示，在衬底41的背面形成背面导电层56，背面导电层56通过背孔54与源极45接触连接。
其中，如图5G所示，背面导电层56覆盖于背孔54的表面和衬底41的背面；源极45与背面导电层56直接接触连接。
背面导电层56的材料，例如可以包括金、钛金等。背面导电层56的厚度，例如可以在500nm～30000nm的区间范围内。背面导电层56例如可以通过电镀工艺、蒸发工艺或者溅射工艺制备得到。
需要说明的是，本申请实施例提供的半导体器件的制备方法，并不限定为由上述步骤构成，可以根据需要增加其他步骤或减少上述部分步骤。另外，上述制备方法中的步骤顺序仅为一种示意，可以根据需要调整变换。
通过上述制备方法制备得到的半导体器件，如图6A所示，包括：衬底41；依次层叠设置于衬底41上的沟道层42和势垒层43，沟道层42和势垒层43构成异质结，在沟道层43内产生二维电子气44；源极45和漏极46设置于势垒层43的表面上，与势垒层43形成欧姆接触，源极45为面状结构，源极45为最靠近势垒层43的导电结构；栅极49设置于势垒层43上，位于源极45和漏极46之间；场板51设置于栅极49远离衬底41一侧，位于栅极49与漏极46之间，与栅极49的投影交叠。
背孔54位于源极45的下方，背孔45从衬底41远离沟道层42的背面贯穿至源极45靠近衬底41的表面；背面导电层56设置于衬底41的背面，通过背孔54与源极45接触连接。
在一些实施例中，如图5G所示，半导体器件还包括加厚源极52和加厚漏极53，加厚源极52设置在源极45上，与源极45接触连接。加厚漏极53设置在漏极46上，与漏极46接触连接。
在一些实施例中，如图6B所示，半导体器件还包括依次层叠设置在衬底41与沟道层42之间的成核层和渐变缓冲层，设在沟道层41与势垒层43之间的插入层、以及设置在势垒层43表面的帽层。
其中，根据帽层材料的不同，示例的，如图6B所示，源极45和漏极46与势垒层43之间设置有帽层。
或者，示例的，如图6C所示，帽层上设置有露出源极45和漏极46的开口，源 极45和漏极46直接与势垒层43接触。
其中，HEMT器件的工作原理为：源极45和漏极46分别与势垒层43形成导电欧姆接触，栅极49与势垒层43形成肖特基接触。沟道层42中虚线代表HEMT器件中沟道层42和势垒层43形成的异质结中通过极化作用产生的2DEG44。2DEG44用于在电场的作用下，高效地传导电子。源极45和漏极46用于在电场的作用下使2DEG44在源极45和漏极46之间的沟道层42内流动，源极45和漏极46之间的导通发生在沟道层42中的2DEG44处。栅极49设置在源极45和漏极46之间，用于允许或阻碍2DEG44的通过，以控制HEMT器件导通或者截止。
需要说明的是，在上述任一种HEMT器件的基础上，将HEMT器件应用于集成电路31中后，在一些实施例中，集成电路31包括的多个HEMT器件的背面导电层56接触连接。或者，在一些实施例中，集成电路31包括的多个HEMT器件中，部分HEMT器件的背面导电层56接触连接。或者，在一些实施例中，集成电路31包括的多个HEMT器件中，各个HEMT器件的背面导电层56相互独立。
本申请实施例中，源极45直接与势垒层43欧姆接触，背孔54位于源极45下方。这样一来，背孔54设置在源极45的下方，背面导电层56通过背孔54与源极45直接接触连接。一方面，信号从源极45直接接触到背面导电层56，使得其传输至源极45的路径更短，可减小半导体器件的电感，增大半导体器件的频率。另外，可以根据需要合理设置背孔54的宽度，无需额外减小背孔54的宽度，以降低背孔54的制备工艺难度和良率、提高背面导电层56的良率和可靠性，从而提高半导体器件的良率和可靠性。因此，减小了器件源极45的尺寸，从而可以制备得到小尺寸、低成本的半导体器件。
可选的，在制备半导体器件的过程中，通过将源极45的材料选取为功函数高的、化学性质稳定的金属(例如包括钛、金、铂)，不再包含活泼金属(比如铝)。使得源极45能够阻挡背孔的刻蚀，还能够避免背孔工艺湿法处理中的腐蚀。
可选的，也可以采用合金的方式，或者工艺改进的方式，使得源极45不会因为背孔54的制作过程中的刻蚀导致被腐蚀。
因此，即使背孔工艺中接触到源极45，也不会对源极45造成损坏。因此无需为了规避此背孔工艺带来的腐蚀，而特意的将源极45跟背孔54远离，从而降低了源极45的尺寸，从而降低了整体的半导体器件的尺寸。
示例二
示例二与示例一的不同之处在于，源极45上具有开口。
如图7A所示，半导体器件中的源极45不再为面状结构，而是具有开口451，开口451位于背孔54上方。
其中，不对开口451的形状进行限定，图7A中开口451的形状仅为一种示意。
可以理解的是，源极45上具有开口451，但开口451的设置应不影响源极45上信号的传输。
在一些实施例中，如图7A所示，源极45上具有开口451，但源极45仍是各处互连的结构。
在另一些实施例中，如图7B所示，源极45上的开口451将源极45划分为多个 条状结构，如图7C(图7B中C1-C2向的剖视图)所示，条状结构例如可以通过加厚源极52实现互连。也就是说，源极45的各部分与加厚源极52接触连接，以实现源极45的各部分的互连。
也就是说，如图8所示，在一些实施例中，半导体器件还包括加厚源极52和加厚漏极53。加厚源极52通过源极45上的开口451与背面导电层56接触连接。
关于开口451与背孔54的结构关系，在一些实施例中，开口451的宽度M1小于或者等于背孔54的宽度M2。
相比于开口451的宽度M1需大于背孔54的宽度M2，开口451的宽度M1小于或者等于背孔54的宽度M2，相当于减小了开口451的宽度M1，从而可减小源极45的宽度。
基于开口451与背孔54的结构关系，带来的源极45与背面导电层56的结构关系，在一些实施例中，背面导电层56具有靠近栅极49的左侧和远离栅极49的右侧，背面导电层56在左侧和/或右侧与源极45接触连接。
在一些实施例中，如图8所示，背面导电层56的左侧和右侧恰好与源极45临界接触。
也就是说，开口451在左侧和右侧与背孔54之间均没有间隙。
在另一些实施例中，如图9A所示，背面导电层56的左侧恰好与源极45临界接触，背面导电层56的右侧与源极45之间具有间隙。
也就是说，开口451在左侧与背孔54之间没有间隙，开口451在右侧与背孔54之间具有间隙。
在又一些实施例中，如图9B所示，背面导电层56的左侧恰好与源极45搭接，背面导电层56的右侧与源极45之间具有间隙。
也就是说，开口451在左侧与背孔54之间没有间隙，开口451在右侧与背孔54之间具有间隙。
在又一些实施例中，如图9C所示，背面导电层56的左侧与源极45搭接，背面导电层56的右侧与源极45恰好临界接触。
也就是说，开口451在左侧和右侧与背孔54之间均没有间隙。
在另一些实施例中，如图10A所示，背面导电层56的右侧恰好与源极45临界接触，背面导电层56的左侧与源极45之间具有间隙。
也就是说，开口451在右侧与背孔54之间没有间隙，开口451在左侧与背孔54之间具有间隙。
在又一些实施例中，如图10B所示，背面导电层56的右侧恰好与源极45搭接，背面导电层56的左侧与源极45之间具有间隙。
也就是说，开口451在右侧与背孔54之间没有间隙，开口451在左侧与背孔54之间具有间隙。
在又一些实施例中，如图10C所示，背面导电层56的右侧与源极45搭接，背面导电层56的左侧与源极45恰好临界接触。
也就是说，开口451在左侧和右侧与背孔54之间均没有间隙。
在又一些实施例中，如图11所示，背面导电层56的右侧与源极45搭接，背面导 电层56的左侧与源极45搭接。
也就是说，开口451在左侧和右侧与背孔54之间均没有间隙。
本申请实施例中，背孔54设置在源极45的下方，源极45上虽然设置开口451，但源极45不会因为背孔54的制作过程中的刻蚀导致被腐蚀。也就是说，即使背孔工艺中接触到源极45，也不会对源极45造成损坏。因此无需为了规避背孔54工艺带来的腐蚀，而将源极45上的开口设置的大于背孔的尺寸，即开口451的宽度M1小于或者等于背孔54的宽度M2，背孔54的左侧和/或右侧与开口451之间没有间隙。也就是说，背面导电层56在左侧和/或右侧与源极45接触连接。因此，虽然根据需要在源极45上设置开口451，但是可以通过减小开口451的尺寸来减小源极45的尺寸，也不会增加半导体器件的尺寸。
需要说明的是，上述以本申请实施例提供的半导体器件为HEMT器件为例，但并不限定为半导体器件为HEMT器件，本申请实施例提供的半导体器件可以为任意源极需要接地的半导体器件。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种半导体器件，其特征在于，包括：
    衬底；
    沟道层和势垒层，依次层叠设置于所述衬底上；
    源极、栅极和漏极，设置于所述势垒层上；
    背孔，贯穿从所述衬底至所述源极下方的势垒层区域；
    背面导电层，覆盖于所述背孔和所述衬底的背面；所述源极与所述背面导电层接触连接。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述源极的材料的功函数在4.3～6eV的区间范围内。
  3. 根据权利要求1或2所述的半导体器件，其特征在于，所述源极的材料包括钛、金、铂元素中的至少一种。
  4. 根据权利要求1-3任一项所述的半导体器件，其特征在于，所述源极包括至少一层导电层。
  5. 根据权利要求4所述的半导体器件，其特征在于，所述源级包括依次堆叠第一导电层和第二导电层，所述第一导电层包括钛元素，所述第二导电层包括金元素，且所述第一导电层与所述势垒层接触连接。
  6. 根据权利要求4或5所述的半导体器件，其特征在于，每层所述导电层的厚度在1nm～10000nm的区间范围内。
  7. 根据权利要求1-6任一项所述的半导体器件，其特征在于，所述源极为面状结构。
  8. 根据权利要求1-7任一项所述的半导体器件，其特征在于，所述源极上具有开口；所述开口位于所述背孔上方。
  9. 根据权利要求1-8任一项所述的半导体器件，其特征在于，所述半导体器件还包括加厚源极；
    所述加厚源极设置在所述源极的表面。
  10. 根据权利要求8所述的半导体器件，其特征在于，所述半导体器件还包括加厚源极；所述加厚源极设置在所述源极的表面，所述加厚源极通过所述开口与所述背面导电层接触。
  11. 根据权利要求1-10任一项所述的半导体器件，其特征在于，所述半导体器件还包括场板；
    所述场板设置于所述栅极远离所述衬底一侧，位于所述栅极与所述漏极之间，与所述栅极的投影交叠。
  12. 一种功率放大电路，其特征在于，包括封装结构以及如权利要求1-11任一项所述的半导体器件，所述半导体器件封装于所述封装结构内部。
  13. 一种电子设备，包括功率放大器及天线，所述功率放大器用于将射频信号放大后输出至所述天线向外辐射，所述功率放大器包括如权利要求12所述的功率放大电路。
  14. 一种半导体器件的制备方法，其特征在于，包括：
    在衬底上依次形成层叠设置的沟道层和势垒层；
    在势垒层上形成源极、栅极和漏极；
    在所述源极下方形成背孔；所述背孔贯穿从所述衬底至所述源极下方的势垒层区域；
    在所述衬底的背面形成背面导电层，所述背面导电层覆盖于所述背孔和所述衬底的背面；所述源极与所述背面导电层接触连接。
  15. 根据权利要求14所述的半导体器件的制备方法，其特征在于，在所述源极下方形成背孔，包括：
    从所述衬底的背面，采用干法刻蚀工艺对所述源极下方的膜层进行开孔，形成所述背孔；
    采用干法刻蚀或者湿法刻蚀去除残留在孔内的刻蚀副产物。
PCT/CN2021/118619 2021-09-15 2021-09-15 半导体器件及其制备方法、功率放大电路、电子设备 WO2023039768A1 (zh)

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