WO2023159578A1 - 半导体结构及其工作方法、功率放大电路、电子设备 - Google Patents

半导体结构及其工作方法、功率放大电路、电子设备 Download PDF

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Publication number
WO2023159578A1
WO2023159578A1 PCT/CN2022/078332 CN2022078332W WO2023159578A1 WO 2023159578 A1 WO2023159578 A1 WO 2023159578A1 CN 2022078332 W CN2022078332 W CN 2022078332W WO 2023159578 A1 WO2023159578 A1 WO 2023159578A1
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Prior art keywords
drain
gate
pad
semiconductor structure
source
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PCT/CN2022/078332
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English (en)
French (fr)
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马平
李海军
仲正
乐伶聪
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华为技术有限公司
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Priority to PCT/CN2022/078332 priority Critical patent/WO2023159578A1/zh
Priority to CN202280076544.9A priority patent/CN118235255A/zh
Publication of WO2023159578A1 publication Critical patent/WO2023159578A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Definitions

  • the present application relates to the field of semiconductor technology, in particular to a semiconductor structure and its working method, a power amplifier circuit, and electronic equipment.
  • semiconductor devices with high thermal conductivity, high electron drift rate, high temperature resistance, and stable chemical properties are widely used in high frequency, high temperature, and microwave fields.
  • High-power semiconductor devices such as gallium nitride high electron mobility transistor (GaN HEMT) devices, due to their unique high electron mobility, high two-dimensional electron gas surface density, high breakdown electric field, high The advantages of channel electron concentration and high temperature stability make it have higher output power density, so it is widely used in integrated circuits such as radio frequency/microwave power amplifier circuits.
  • GaN HEMT gallium nitride high electron mobility transistor
  • the total grid width is usually increased by increasing the number of grid bars.
  • the number of grid bars that can be arranged is limited.
  • the total gate width can be increased by increasing the gate width of a single finger.
  • the increase of the gate width of a single finger will reduce the gain of the device and affect the performance of the device.
  • Embodiments of the present application provide a semiconductor structure and its working method, a power amplifier circuit, and electronic equipment, which are used to increase the total output power of high-power semiconductor devices.
  • a semiconductor structure includes a plurality of semiconductor groups.
  • Each semiconductor group includes a plurality of sources, a plurality of drains and a plurality of gates, a drain pad and a gate pad, and at least one back hole disposed under each source.
  • multiple bonding points are arranged on the drain pad and the gate pad, and each bonding point is also connected with a bonding wire.
  • a plurality of sources, a plurality of drains, and a plurality of gates are located between the drain pad and the gate pad, the plurality of drains are coupled to the drain pad, and the plurality of gates are coupled to the gate pad. catch.
  • the source, the drain and the gate are alternately arranged, and the gate is located between the source and the drain.
  • Both the drain pad and the gate pad extend along a second direction, the first direction is a direction from the drain pad to the gate pad, and the first direction intersects the second direction.
  • the drain pad and the gate pad are located on opposite sides of the alternate arrangement direction of the source and the drain, and the alternate arrangement direction of the source and drain is the same as that of the drain pad and the gate pad.
  • the direction of disk extension intersects, and the gate is located between the source and drain.
  • the number of gates can be increased as much as possible, so that the single gate can be realized without increasing the size of a single gate, that is, without increasing the gate width of a single finger.
  • the total gate width of the semiconductor structure is increased, thereby increasing the output power of the semiconductor structure, and improving the gain and efficiency of the semiconductor structure.
  • the back hole is arranged under the source to realize the grounding of the source and reduce the complexity of the process.
  • the signal transmission path to the source is shortened, reducing the parasitic inductance of the semiconductor structure.
  • the source is grounded through the back hole, so there is no need to set the source pad and the source bus connecting the source and the source pad, which can avoid the overlap between the source bus and the drain or gate. parasitic capacitance, thereby improving the reliability of the semiconductor structure.
  • the semiconductor structure further includes a drain bus and a gate bus; the drain bus is coupled to the plurality of drains and the drain pads respectively; the gate pad is coupled to the plurality of gates and the gate pads respectively Coupling; both the drain bus line and the gate bus line extend along the first direction; the drain bus line and the gate bus line are located on opposite sides of the drain along the second direction.
  • the drain bus is used to couple the drain to the drain pad
  • the gate bus is used to couple the gate to the gate pad
  • the drain bus and the gate bus are located on opposite sides of the drain along the second direction, Avoid overlapping the drain bus line and the gate bus line with the source, drain or gate, thereby avoiding the parasitic capacitance generated by the overlap between the drain bus line and the gate bus line and the source, drain or gate.
  • the size of the drain bus line along the second direction is smaller than the size of the bonding point along the second direction
  • the size of the gate bus line along the second direction is smaller than the size of the bonding point along the second direction. Bonding points and bonding wires connected to the bonding points cannot be provided on either the drain bus line or the gate bus line.
  • the multiple sources, the multiple drains and the multiple gates are divided into multiple groups arranged side by side along the second direction, and the sources and drains in each group are alternately arranged along the first direction.
  • the area occupied by the drain bus line or the gate bus line along the second direction is saved.
  • the positions of the drain bus line and the gate bus line can be reasonably set according to actual conditions.
  • the positions of the drain bus line and the gate bus line can be reasonably set according to actual conditions.
  • the positions of the drain bus line and the gate bus line can be reasonably set according to actual conditions.
  • one of the drain bus line and the gate bus line is located on a side of the drain away from the gap, and the other is located on a side of the drain close to the gap. There is no overlap between the drain bus line and the gate bus line, and no parasitic capacitance occurs.
  • the plurality of sources, the plurality of drains and the plurality of gates are divided into two groups arranged side by side along the second direction; the drains in each group are coupled to the same drain bus line, and each drain The pole bus is located on the side of the drain away from the gap; multiple gates are coupled to the same gate bus, and the gate bus is located on the side of the drain close to the gap.
  • the drain bus and the gate bus are arranged on different sides of the drain to avoid overlapping between the drain bus and the source, drain and gate, and to avoid overlap between the gate bus and the source, drain and gate. The overlapping also avoids overlapping between the drain bus line and the gate bus line, thereby avoiding the parasitic capacitance generated by the overlap between the source, the drain, the gate-drain bus line and the gate bus line.
  • the plurality of sources, the plurality of drains and the plurality of gates are divided into two groups arranged side by side along the second direction; the gates in each group are coupled to the same gate bus line, and each gate
  • the drain bus is located on the side of the drain away from the gap; multiple drains are coupled to the same drain bus, and the drain bus is located on the side of the drain close to the gap.
  • the drain bus and the gate bus are arranged on different sides of the drain to avoid overlapping between the drain bus and the source, drain and gate, and to avoid overlap between the gate bus and the source, drain and gate. The overlapping also avoids overlapping between the drain bus line and the gate bus line, thereby avoiding the parasitic capacitance generated by the overlap between the source, the drain, the gate-drain bus line and the gate bus line.
  • At least two back holes are disposed under the source electrode. Setting the back hole under the source can reduce the parasitic inductance of the semiconductor structure and improve the frequency characteristic of the semiconductor structure.
  • the plurality of semiconductor groups are arranged along the second direction, the bonding points are arranged on the drain pad along the second direction, and the bonding points are arranged on the gate pad along the second direction.
  • the semiconductor structure formed by arranging multiple semiconductor groups in parallel is a high-power device.
  • the gate pads in the plurality of semiconductor groups are coupled, and the drain pads in the plurality of semiconductor groups are coupled.
  • the synchronous transmission of signals is realized.
  • the semiconductor structure further includes: a substrate, a channel layer, and a barrier layer that are sequentially stacked; and the source, drain, and gate are all disposed on the barrier layer.
  • the source and drain are in ohmic contact with the barrier layer respectively
  • the back hole penetrates from the substrate to the barrier layer; the semiconductor structure further includes a back conductive layer; the back conductive layer covers the back of the substrate and the back hole; the source is in contact with the back conductive layer.
  • the conductive layer on the back is in direct contact with the source through the back hole, so as to realize the grounding of the source and reduce the complexity of the process.
  • the source is directly in contact with the conductive layer on the back, so that the signal transmission path to the source is shorter, and the parasitic inductance of the semiconductor structure is reduced.
  • the second aspect of the embodiment of the present application provides a working method of a semiconductor structure
  • the semiconductor structure includes a plurality of semiconductor groups, each semiconductor group includes: a plurality of sources, a plurality of drains and a plurality of gates; plate and a gate pad; multiple drains are coupled to the drain pad, and multiple gates are coupled to the gate pad; multiple bonding points are arranged on the drain pad and the gate pad; wherein , a plurality of sources, a plurality of drains and a plurality of gates are located between the drain pad and the gate pad, and in the first direction, the sources, drains and gates are alternately arranged; the gate is located between the source and the drain; both the drain pad and the gate pad extend along a second direction, and the first direction is a direction from the drain pad to the gate pad; the first direction intersects the second direction; multiple a back hole, at least one back hole is arranged under each source in the plurality of sources; the source is grounded through the back hole; the working method of the semiconductor structure includes: the
  • the semiconductor structure includes the semiconductor structure of the first aspect, and its beneficial effect is the same as that of the semiconductor structure, so it will not be repeated here.
  • a third aspect of the embodiments of the present application provides a power amplifier circuit, including a packaging structure and the semiconductor structure according to any one of the first aspect, and the semiconductor structure is packaged inside the packaging structure.
  • the power amplifying circuit provided by the embodiment of the present application includes the semiconductor structure of the first aspect, and its beneficial effect is the same as that of the semiconductor structure, so it will not be repeated here.
  • the fourth aspect of the embodiments of the present application provides an electronic device, including a power amplifier and an antenna.
  • the power amplifier is used to amplify a radio frequency signal and output it to the antenna for external radiation.
  • the power amplifier includes the power amplifier circuit as in the third aspect.
  • the electronic device provided by the embodiment of the present application includes the semiconductor structure of the first aspect, and its beneficial effect is the same as that of the semiconductor structure, so it will not be repeated here.
  • FIG. 1A is a schematic framework diagram of an electronic device provided in an embodiment of the present application.
  • FIG. 1B is a schematic framework diagram of a base station provided in an embodiment of the present application.
  • FIG. 1C is a schematic framework diagram of a power amplifier circuit provided by an embodiment of the present application.
  • FIG. 2A is a schematic structural diagram of a semiconductor structure provided in an embodiment of the present application.
  • FIG. 2B is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 3A is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present application.
  • FIG. 3B is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 4A is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 4B is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 4C is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 4D is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 4E is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 5A is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 5B is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 5C is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 5D is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 5E is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 6A is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 6B is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 6C is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 6D is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 7A is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 7B is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 7C is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 7D is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • FIG. 7E is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present application.
  • Fig. 8 is a sectional view along the A1-A2 direction in Fig. 7E;
  • FIG. 9 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present application.
  • FIG. 10 is a flow chart of the working method of the semiconductor structure provided by the embodiment of the present application.
  • a semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; among them, a semiconductor includes intrinsic semiconductors and impurity semiconductors.
  • a semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an extrinsic semiconductor.
  • the impurity doped in the impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons), and the impurity semiconductor that provides electron impurities (such as pentavalent phosphorus) is also called an electronic semiconductor or N (negative, negative) type semiconductor, impurity semiconductor doped to provide hole impurities (such as trivalent boron element), also known as hole type semiconductor or P (positive, positive) type semiconductor, doping can improve the intrinsic semiconductor Conductivity, generally the higher the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity.
  • a layer structure in a device made of a semiconductor (or semiconductor material) is called a semiconductor layer.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact.
  • the term “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • At least one (layer) means one (layer) or multiple (layers), and “multiple (layers)” means two (layers) or more than two (layers).
  • At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • at least one (unit) of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be It can be single or multiple.
  • Exemplary embodiments are described in the embodiments of the present application with reference to cross-sectional views and/or plan views and/or equivalent circuit diagrams that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • An embodiment of the present application provides an electronic device, which can be, for example, different types of user equipment such as lidar drivers, lasers, detectors, radars, and 5G (the 5th generation mobile network, fifth-generation mobile communication technology) communication equipment. or a terminal device; the electronic device may also be a network device such as a base station. The electronic device may also be a device such as a power amplifier used in the above-mentioned electronic device.
  • the embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.
  • FIG. 1A shows a schematic structural diagram of an electronic device 100 .
  • the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, and an antenna 2 , mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, earphone jack 170D, sensor module 180, camera 190 and display screen 191, etc.
  • a processor 110 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, and an antenna 2 , mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, earphone jack 170D, sensor module 180
  • the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100 .
  • the electronic device 100 may include more or fewer components than shown in the figure, or combine certain components, or separate certain components, or arrange different components.
  • the illustrated components can be realized in hardware, software or a combination of software and hardware.
  • the processor 110 may include one or more processing units, for example: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural network processor (neural-network processing unit, NPU), etc. Wherein, different processing units may be independent devices, or may be integrated in one or more processors.
  • application processor application processor, AP
  • modem processor graphics processing unit
  • GPU graphics processing unit
  • image signal processor image signal processor
  • ISP image signal processor
  • controller video codec
  • digital signal processor digital signal processor
  • baseband processor baseband processor
  • neural network processor neural-network processing unit
  • a memory may also be provided in the processor 110 for storing instructions and data.
  • the memory in processor 110 is a cache memory.
  • the memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to use the instruction or data again, it can be directly recalled from the memory. Repeated access is avoided, and the waiting time of the processor 110 is reduced, thereby improving the efficiency of the system.
  • processor 110 may include one or more interfaces.
  • the interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transmitter (universal asynchronous receiver/transmitter, UART) interface, mobile industry processor interface (mobile industry processor interface, MIPI), general-purpose input and output (general-purpose input/output, GPIO) interface, subscriber identity module (subscriber identity module, SIM) interface, and /or universal serial bus (universal serial bus, USB) interface, etc.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • PCM pulse code modulation
  • UART universal asynchronous transmitter
  • MIPI mobile industry processor interface
  • GPIO general-purpose input and output
  • subscriber identity module subscriber identity module
  • SIM subscriber identity module
  • USB universal serial bus
  • the charging management module 140 is configured to receive a charging input from a charger.
  • the charger may be a wireless charger or a wired charger.
  • the charging management module 140 can receive charging input from the wired charger through the USB interface 130 .
  • the charging management module 140 may receive a wireless charging input through a wireless charging coil of the electronic device 100 . While the charging management module 140 is charging the battery 142 , it can also supply power to the electronic device 100 through the power management module 141 .
  • the power management module 141 is used for connecting the battery 142 , the charging management module 140 and the processor 110 .
  • the power management module 141 receives the input from the battery 142 and/or the charging management module 140 to provide power for the processor 110 , the internal memory 121 , the display screen 191 , the camera 190 , and the wireless communication module 160 .
  • the power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle times, and battery health status (leakage, impedance).
  • the power management module 141 may also be disposed in the processor 110 .
  • the power management module 141 and the charging management module 140 may also be set in the same device.
  • the wireless communication function of the electronic device 100 can be realized by the antenna 1 , the antenna 2 , the mobile communication module 150 , the wireless communication module 160 , a modem processor, a baseband processor, and the like.
  • Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals.
  • Each antenna in electronic device 100 may be used to cover single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization of the antennas.
  • Antenna 1 can be multiplexed as a diversity antenna of a wireless local area network.
  • the antenna may be used in conjunction with a tuning switch.
  • the mobile communication module 150 can provide wireless communication solutions including 2G/3G/4G/5G applied on the electronic device 100 .
  • the mobile communication module 150 may include one or more filters, switches, power amplifiers, low noise amplifiers (low noise amplifier, LNA) and the like.
  • the mobile communication module 150 can receive electromagnetic waves through the antenna 1, filter and amplify the received electromagnetic waves, and send them to the modem processor for demodulation.
  • the mobile communication module 150 can also amplify the signals modulated by the modem processor, and convert them into electromagnetic waves and radiate them through the antenna 1 .
  • at least part of the functional modules of the mobile communication module 150 may be set in the processor 110 .
  • at least part of the functional modules of the mobile communication module 150 and at least part of the modules of the processor 110 may be set in the same device.
  • a modem processor may include a modulator and a demodulator.
  • the modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal.
  • the demodulator is used to demodulate the received electromagnetic wave signal into a low frequency baseband signal. Then the demodulator sends the demodulated low-frequency baseband signal to the baseband processor for processing.
  • the low-frequency baseband signal is passed to the application processor after being processed by the baseband processor.
  • the application processor outputs sound signals through audio equipment (not limited to speaker 170A, receiver 170B, etc.), or displays images or videos through display screen 191 .
  • the modem processor may be a stand-alone device.
  • the modem processor may be independent from the processor 110, and be set in the same device as the mobile communication module 150 or other functional modules.
  • the wireless communication module 160 can provide wireless local area networks (wireless local area networks, WLAN) (such as wireless fidelity (Wireless Fidelity, Wi-Fi) network), bluetooth (bluetooth, BT), global navigation satellite, etc. applied on the electronic device 100.
  • System global navigation satellite system, GNSS
  • frequency modulation frequency modulation, FM
  • near field communication technology near field communication, NFC
  • infrared technology infrared, IR
  • the wireless communication module 160 may be one or more devices integrating one or more communication processing modules.
  • the wireless communication module 160 receives electromagnetic waves via the antenna 2 , frequency-modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110 .
  • the wireless communication module 160 can also receive the signal to be sent from the processor 110 , frequency-modulate it, amplify it, and convert it into electromagnetic waves through the antenna 2 for radiation.
  • the antenna 1 of the electronic device 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology.
  • the wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and/or IR technology, etc.
  • the GNSS can include global positioning system (global positioning system, GPS), global navigation satellite system (global navigation satellite system, GLONASS), Beidou satellite navigation system (beidou navigation satellite system, BDS), quasi-zenith satellite system (quasi- zenith satellite system (QZSS) and/or satellite based augmentation systems (SBAS).
  • global positioning system global positioning system, GPS
  • global navigation satellite system global navigation satellite system
  • GLONASS global navigation satellite system
  • Beidou satellite navigation system beidou navigation satellite system, BDS
  • quasi-zenith satellite system quasi-zenith satellite system
  • QZSS quasi-zenith satellite system
  • SBAS satellite based augmentation systems
  • the electronic device 100 implements a display function through a GPU, a display screen 191 , and an application processor.
  • the GPU is a microprocessor for image processing, and is connected to the display screen 191 and the application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering.
  • Processor 110 may include one or more GPUs that execute program instructions to generate or change display information.
  • the display screen 191 is used to display images, videos and the like.
  • the display screen 191 includes a display panel.
  • the display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active matrix organic light emitting diode or an active matrix organic light emitting diode (active-matrix organic light emitting diode, AMOLED), flexible light-emitting diode (flex light-emitting diode, FLED), Miniled, MicroLed, Micro-oLed, quantum dot light emitting diodes (quantum dot light emitting diodes, QLED), etc.
  • the electronic device 100 may include 1 or N display screens 191 , where N is a positive integer greater than 1.
  • the electronic device 100 can realize the shooting function through the ISP, the camera 190 , the video codec, the GPU, the display screen 191 and the application processor.
  • the ISP is used for processing data fed back by the camera 190 .
  • the light is transmitted to the photosensitive element of the camera through the lens, and the optical signal is converted into an electrical signal, and the photosensitive element of the camera transmits the electrical signal to the ISP for processing, and converts it into an image visible to the naked eye.
  • ISP can also perform algorithm optimization on image noise, brightness, and skin color. ISP can also optimize the exposure, color temperature and other parameters of the shooting scene.
  • the ISP may be located in the camera 190 .
  • Camera 190 is used to capture still images or video.
  • the object generates an optical image through the lens and projects it to the photosensitive element.
  • the photosensitive element may be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor.
  • CMOS complementary metal-oxide-semiconductor
  • the photosensitive element converts the light signal into an electrical signal, and then transmits the electrical signal to the ISP to convert it into a digital image signal.
  • the ISP outputs the digital image signal to the DSP for processing.
  • DSP converts digital image signals into standard RGB, YUV and other image signals.
  • the electronic device 100 may include 1 or N cameras 190 , where N is a positive integer greater than 1.
  • the external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, so as to expand the storage capacity of the electronic device 100.
  • the external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function. Such as saving music, video and other files in the external memory card.
  • the internal memory 121 may be used to store one or more computer programs including instructions.
  • the processor 110 may execute the above-mentioned instructions stored in the internal memory 121 , so that the electronic device 100 executes various functional applications, data processing, and the like.
  • the internal memory 121 may include an area for storing programs and an area for storing data.
  • the stored program area can store an operating system; the stored program area can also store one or more application programs (such as a gallery, contacts, etc.) and the like.
  • the data storage area can store data (such as photos, contacts, etc.) created during the use of the electronic device 100 .
  • the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, universal flash storage (universal flash storage, UFS) and the like.
  • the processor 110 enables the electronic device 100 to execute various functional applications and data processing by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.
  • the electronic device 100 can implement audio functions through the audio module 170 , the speaker 170A, the receiver 170B, the microphone 170C, the earphone interface 170D, and the application processor. Such as music playback, recording, etc.
  • the audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signal.
  • the audio module 170 may also be used to encode and decode audio signals.
  • the audio module 170 may be set in the processor 110 , or some functional modules of the audio module 170 may be set in the processor 110 .
  • Speaker 170A also referred to as a "horn" is used to convert audio electrical signals into sound signals.
  • Electronic device 100 can listen to music through speaker 170A, or listen to hands-free calls.
  • Receiver 170B also called “earpiece” is used to convert audio electrical signals into sound signals.
  • the receiver 170B can be placed close to the human ear to receive the voice.
  • the microphone 170C also called “microphone” or “microphone” is used to convert sound signals into electrical signals. When making a phone call or sending a voice message, the user can put his mouth close to the microphone 170C to make a sound, and input the sound signal to the microphone 170C.
  • the electronic device 100 may be provided with one or more microphones 170C. In some other embodiments, the electronic device 100 may be provided with two microphones 170C, which may also implement a noise reduction function in addition to collecting sound signals. In some other embodiments, the electronic device 100 can also be provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify sound sources, and realize directional recording functions, etc.
  • the earphone interface 170D is used for connecting wired earphones.
  • the earphone interface 170D can be a USB interface 130, or a 3.5mm open mobile terminal platform (OMTP) standard interface, or a cellular telecommunications industry association of the USA (CTIA) standard interface.
  • OMTP open mobile terminal platform
  • CTIA cellular telecommunications industry association of the USA
  • the sensor module 180 may include a pressure sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.
  • a touch sensor is also referred to as a "touch device”.
  • the touch sensor can be arranged on the display screen 191, and the touch sensor and the display screen 191 form a touch screen, also called “touch screen”.
  • the touch sensor is used to detect a touch operation on or near it.
  • the touch sensor can pass the detected touch operation to the application processor to determine the type of touch event.
  • Visual output related to the touch operation may be provided through the display screen.
  • a touch panel with a touch sensor array formed by a plurality of touch sensors may also be installed on the surface of the display panel in a hanging form.
  • the location of the touch sensor and the display screen 191 may also be different.
  • the form of the touch sensor is not limited, for example, it may be a capacitor or a piezoresistor.
  • the electronic device 100 may further include one or more components such as keys, motors, indicators, and a subscriber identification module (subscriber identification module, SIM) card interface, which is not limited in this embodiment of the present application.
  • SIM subscriber identification module
  • the electronic equipment provided by the embodiments of the present application is a 5G base station
  • the 5G base station can be divided into a base band processing unit (base band unit, BBU)-active antenna unit (active antenna unit, AAU), a centralized unit-distribution unit (central unit-distribute unit, CU-DU)-AAU, BBU-radio remote unit (remote radio unit, RRU)-antenna, CU-DU-RRU-Antenna, integrated 5G base station (5G node base station , gNB)- and other different architectures.
  • base band unit base band unit
  • AAU active antenna unit
  • CU-DU central unit-distribute unit
  • BBU-radio remote unit remote radio unit
  • RRU remote radio unit
  • FIG. 1B illustrates a base station 200 with a BBU-RRU architecture.
  • the base station 200 may include a BBU21, an RRU22, and an antenna 23; wherein the BBU21 and the RRU22 are connected through an optical fiber, and the interface between the two is based on an open common public radio interface (common public radio interface, CPRI) and an open base station architecture (open base station architecture initiative, OBSAI).
  • the BBU21 sends the generated baseband signal to the antenna 23 for transmission after being processed by the RRU22.
  • the RRU 22 includes a digital intermediate frequency module 221 , a transceiver module 222 , a power amplifier 223 (power amplifier, PA) and a filter 224 .
  • the digital intermediate frequency module 221 is used for the modulation and demodulation of the baseband signal transmitted by optical fiber, digital up-down conversion, digital to analog converter (digital to analog converter, D/A), etc. to form an intermediate frequency signal;
  • the transceiver module 222 completes the conversion of the intermediate frequency signal to the radio frequency Signal conversion;
  • the power amplifier 223 is used to amplify the power of the low-power radio frequency signal;
  • the filter 224 is used to filter the radio frequency signal, and then transmit the radio frequency signal through the antenna 23 .
  • the embodiment of the present application also provides a power amplifier circuit, which can be applied to the power amplifier of the mobile communication module 150 or the wireless communication module 160 in the electronic device 100 shown in FIG. 1A , and can also be applied to the base station 200 shown in FIG. 1B above. In the power amplifier of RRU22.
  • a power amplifier circuit which can be applied to the power amplifier of the mobile communication module 150 or the wireless communication module 160 in the electronic device 100 shown in FIG. 1A , and can also be applied to the base station 200 shown in FIG. 1B above.
  • specific application scenarios are not limited to the electronic device 100 shown in FIG. 1A and the base station 200 shown in FIG. 1B above. It can be understood that any of the above-mentioned electronic devices that need to use a power amplification circuit in a power amplifier to amplify a signal belongs to the application scenarios of the embodiments of the present application.
  • a power amplifier circuit 30 is shown in FIG. 1C .
  • the power amplifying circuit 30 includes an integrated circuit 31 and a packaging structure 32 , wherein the integrated circuit 31 is packaged inside the packaging structure 32 .
  • a specific package structure of the power amplifier circuit 30 is provided, and the integrated circuit 31 is packaged in the package structure 32 of the power amplifier circuit 30 .
  • the package structure 32 specifically includes: a heat dissipation substrate 321, wherein in order to improve the conductivity and heat dissipation of the heat dissipation substrate 321, the heat dissipation substrate 321 can be made of a composite material, such as a laminate formed of copper Cu/molybdenum Mo/copper Cu structure.
  • the integrated circuit 31 is bonded or directly welded on the heat dissipation substrate 321 by sintering silver.
  • the integrated circuit 31 includes at least one transistor, and some electrodes of the transistor (for example, the source S) are connected to the heat dissipation substrate 321 to realize the source S being grounded.
  • the electrode pads of some electrodes of the transistor (such as the drain D and the gate G) are connected to the pins through bonding wires (bonding), specifically, the electrode pads of the drain D are connected to the pins through the bonding wires.
  • the bonding is connected to pin 1, and the electrode pad of the gate G is connected to pin 2 by bonding wire bonding.
  • the pins are disposed on an insulating layer (for example, insulating ceramics), and the insulating layer is bonded to the heat dissipation substrate 321 by an insulating adhesive.
  • the package structure 32 includes a package tube shell 322, the package tube shell 322 is bonded to the heat dissipation substrate 321 through an insulating adhesive, and one end of the pin is exposed from the package structure 32 to connect to other circuits, wherein the integrated circuit 31 is arranged on the package tube In the space surrounded by the shell 322 and the heat dissipation substrate 321 .
  • An example of a high-power semiconductor device such as: gallium nitride high electron mobility transistor (gallium nitride high electron mobility transistor, GaN HEMT) device, due to its high breakdown electric field, high channel electron concentration, high electron mobility and High temperature stability and other advantages, so it is widely used as a transistor in the integrated circuit 31 .
  • gallium nitride high electron mobility transistor gallium nitride high electron mobility transistor, GaN HEMT
  • GaN HEMT gallium nitride high electron mobility transistor
  • the semiconductor structure 400 mainly includes a plurality of sources 410 , a plurality of drains 420 , a plurality of gates 430 , a drain pad 421 , a gate pad 431 and a back hole 412 .
  • the source 410 and the drain 420 are arranged alternately along the second direction x
  • the gate 430 is located between the source 410 and the drain 420
  • the source 410, the drain 420 and the gate 430 are all along the first direction y extend.
  • the back hole 412 is located below the source electrode 410
  • the source electrode 410 is directly connected to the backside ground of the semiconductor structure 400 through the back hole 412 .
  • the drain pad 421 is coupled to the drain 420
  • the gate pad 431 is coupled to the gate 430
  • the drain pad 421 and the gate pad 431 are respectively located at opposite ends of the source 410 along the first direction y .
  • the size h1 of a single gate 430 is referred to as a single-finger gate width (Wgu).
  • the integrated circuit 31 is the circuit structure in the power amplifier circuit 30
  • a plurality of semiconductor groups 40 are connected in parallel to form a semiconductor structure 400 to increase the total output power or the total gate width
  • the gate 430 in the semiconductor structure 400 extends along the first direction y
  • the multiple gates 430 extend along the second direction x Arranged in parallel
  • both the drain pad 421 and the gate pad 431 are provided with bonding points 440
  • each bonding point 440 has a bonding wire 441 connected thereto.
  • the number of semiconductor structures 400 that can be arranged in parallel is limited, and therefore, the number of gates 430 in the semiconductor structure 400 is limited.
  • the total gate width of the semiconductor structure 400 has to be increased by increasing the gate width of a single finger.
  • the increase of the single-finger gate width will lead to a longer signal transmission path along the gate 430 , resulting in a decrease in the gain of the semiconductor structure 400 and affecting the performance of the semiconductor structure 400 .
  • the increase of the single-finger gate width will lead to the deterioration of the heat dissipation performance of the semiconductor structure 400 and affect the efficiency of the semiconductor structure 400 .
  • the total output power is generally increased by changing the material or parameters of the semiconductor structure 400 , thereby reducing the gate width of a single finger.
  • the embodiment of the present application provides a semiconductor structure 400.
  • the semiconductor structure 400 includes multiple sources 410, multiple drains 420, multiple gates 430, source pads 411, and drain pads 421. and the gate pad 431 .
  • the source 410 and the drain 420 are alternately arranged along the first direction y, the gate 430 is located between the source 410 and the drain 420, and the source 410, the drain 420 and the gate 430 extend along the second direction x.
  • the plurality of sources 410 , the plurality of drains 420 and the plurality of gates 430 can be divided into two groups arranged side by side along the second direction x, and there are gaps between the sources 410 in the same row.
  • the gates 430 in each group are coupled to the same gate bus 432 , the gate bus 432 is located on the side away from the gap of the drain 420 , and the gate bus 432 is coupled to the gate pad 431 .
  • Multiple drains 420 are coupled to the same drain bus line 422 , the drain bus line 422 is located at the side of the drain 420 close to the gap, and the drain bus line 422 is coupled to the drain pad 421 .
  • the source electrode 410 and the drain electrode 420 are interdigitated and interdigitated.
  • the drain pad 421 and the gate pad 431 are respectively located on opposite sides of the drain bus line 422 .
  • the sources 410 in each group are coupled to the same source pad 411 , and the source pad 411 is located on the side of the gate bus 432 away from the source 410 . That is to say, along the second direction x, the source pads 411 in the two groups are respectively located on opposite sides of a row of source electrodes 410 .
  • the source pad 411 , the drain pad 421 and the gate pad 431 all need to be bonded to the package structure 32 through the bonding wire 441 .
  • the semiconductor structure 400 increases the total gate width by increasing the number of gates 430 , avoiding the problem that the performance of the semiconductor structure 400 is affected by increasing the gate width of a single finger.
  • the total gate width of the semiconductor structure 400 can be increased without increasing the single-finger gate width of the semiconductor structure 400 .
  • bonding points 440 and bonding wires 441 connected to each bonding point 440 are provided on the source pad 411 , the drain pad 421 and the gate pad 431 .
  • the source pad 411 , the drain pad 421 and the gate pad 431 are respectively bonded and connected to the package structure 32 through the bonding wire 441 .
  • the source 410 in the plurality of semiconductor structures 400 needs to be electrically connected to the source pad 411 , the drain 420 needs to be electrically connected to the drain pad 421 , and the gate 430 needs to be electrically connected to the gate pad 431 .
  • the adjacent gate pads 431 or the adjacent drain pads 421 cannot be directly coupled.
  • a dielectric bridge (the area between the adjacent drain pads 421 is provided with a dielectric layer, and the source pads 411 on both sides
  • the drain pad 421 is electrically connected through a bridge on the dielectric layer; or, a dielectric layer is provided in the area between adjacent gate pads 431, and the gate pads 431 on both sides of the source pad 411 pass through the dielectric layer
  • the bridge on the bridge is electrically connected) or the air bridge (the area between the adjacent drain pads 421, the drain pad 421 jumps up, leaving a gap between the source pad 411 and the drain pad 421; Or, in the region between the adjacent gate pads 431, the gate pads 431 jump up, leaving a gap between the source pads 411 and the gate pads 431) so that the drain pads 421 or gate
  • the electrode pad 431 is electrically connected across the region between them.
  • the length of the drain pad 421 and the gate pad 431 along the second direction x is relatively small, which limits the connection between the drain pad 421 or the gate pad 431.
  • the quantity affects the matching between the multiple semiconductor groups 40 , and further affects the performance of the semiconductor structure 400 . Therefore, the semiconductor structure 400 cannot be made into multiple parallel-connected high-power devices due to process limitations.
  • an embodiment of the present application further provides a semiconductor structure 400 .
  • the semiconductor structure 400 includes a plurality of semiconductor groups 40 .
  • a plurality of bonding points 440 and bonding wires 441 connected to each bonding point 440 are also disposed on the semiconductor structure 400 .
  • the bonding points 440 are arranged on the drain pad 421 along the second direction x, and the bonding points 440 are arranged on the gate pad 431 along the second direction x.
  • semiconductor structure 400 semiconductor group 40
  • semiconductor group 40 semiconductor group 40
  • the semiconductor structure 400 mainly includes a plurality of sources 410 , a plurality of drains 420 , a plurality of gates 430 , a drain pad 421 , a gate pad 431 and a plurality of back holes 412 .
  • the source 410, the drain 420 and the gate 430 are located in the active area (AA).
  • the drain pad 421 and the gate pad 431 are located in the inactive area.
  • a plurality of sources 410 , a plurality of drains 420 and a plurality of gates 430 are located between the drain pad 421 and the gate pad 431 .
  • a plurality of sources 410 and a plurality of drains 420 are alternately arranged along a first direction y, which is a direction from the drain pad 421 to the gate pad 431 .
  • Both the drain pad 421 and the gate pad 431 extend along the second direction x, and the first direction y intersects the second direction x, for example: the first direction y is perpendicular to the second direction x.
  • a plurality of bonding points 440 are disposed on the drain pad 421 and the gate pad 431 , and each bonding point 440 is also connected to a bonding wire 441 .
  • the bonding wires 441 are used to respectively connect the drain pad 421 and the gate pad 431 to corresponding pins on the package structure 32 .
  • the bonding wire 441 is used to connect the drain pad 421 to the pin 1 on the packaging structure 32 , and the bonding wire 441 is also used to connect the gate pad 431 to the pin 2 on the packaging structure 32 .
  • Bonding refers to a process in which two homogeneous or heterogeneous materials are surface-treated and directly combined under certain conditions to achieve electrical or mechanical electrical interconnection between the two materials.
  • the bonding method of the bonding wire 441 and the drain pad 421 or the gate pad 431 may be, for example, direct contact bonding when preparing the drain pad 421 or the gate pad 43 .
  • the way of bonding point 440 and bonding wire 441 can be, for example, by micro bump bonding (micro bump bonding), embedded bump bonding (embedded bump bonding), hybrid bonding (hybrid bonding, HB) , surface activated bonding (surface activated bonding, SAB), atomic diffusion bonding (atomic diffusion bonding, ADB), wire bonding (wire bonding, WB) and other processes to achieve bonding.
  • Materials of the bonding points 440 and the bonding wires 441 may include gold (Au).
  • the material of the source electrode 410 and the drain electrode 420 may be a single substance, or an alloy or a multilayer stacked metal.
  • the material of the source electrode 410 and the drain electrode 420 includes at least one of titanium (Ti), gold (Au), and platinum (Pt) elements.
  • the material of the source electrode 410 and the drain electrode 420 includes titanium nitride (TiN).
  • both the source electrode 410 and the drain electrode 420 are strip-shaped and extend along the second direction x.
  • the gate 430 is located between the source 410 and the drain 420 , that is, the gate 430 also extends along the second direction x.
  • the size h2 of the gate 430 in the second direction x is the width of a single finger.
  • a gate 430 is disposed between two adjacent source electrodes 410 and drain electrodes 420 .
  • a gate 430 is provided between any adjacent two source electrodes 410 and drain electrodes 420 .
  • the number of gates 430 in the semiconductor structure 400 can be as large as possible.
  • the total gate width of the semiconductor structure 400 is increased, thereby improving the gain and efficiency of the semiconductor structure 400 .
  • the material of the gate 430 can be, for example, a high work function metal.
  • the material of the gate 430 may be nickel (Ni) or gold, for example.
  • the semiconductor structure 400 further includes a drain bus line 422 and a gate bus line 432 . Drain bus lines 422 and gate bus lines 432 are located in the active area.
  • both the drain bus line 422 and the gate bus line 432 extend along the first direction y.
  • the drain bus line 422 and the gate bus line 432 are located on opposite sides of the source electrode 410 . That is to say, the drain bus line 422 and the gate bus line 432 are located on opposite sides of the source electrode 410 along the second direction x.
  • the drain bus 422 is coupled to the drain 420 and the drain pad 421 respectively, and the gate bus 432 is coupled to the gate 430 and the gate pad 431 respectively.
  • the drain pad 421 and the gate pad 431 are respectively disposed at two opposite ends of the drain bus line 422 (or the gate bus line 432 ).
  • the drain pad 421 is coupled to the drain bus line 422
  • the gate pad 431 is coupled to the gate bus line 432 .
  • the size of the drain bus line 422 along the second direction x is smaller than the size of the bonding point 440 along the second direction x, and the size of the gate bus line 432 along the second direction x is smaller than the size of the bonding point 440 along the second direction x. That is to say, the bonding point 440 and the bonding wire 441 cannot be disposed on the drain bus line 422 and the gate bus line 432 .
  • the gate 430 , the gate bus 432 , and the gate pad 431 can be formed synchronously in the same process. Or it can be understood that the gate 430 , the gate bus 432 , and the gate pad 431 may be of the same layer and of the same material.
  • the drain 420 , the drain bus 422 , and the drain pad 421 can be formed synchronously in the same process. Or it can be understood that the drain 420 , the drain bus 422 , and the drain pad 421 may be of the same layer and of the same material.
  • drain bus 422 There can be one drain bus 422 , that is, all the drains 420 are coupled to the same drain bus 422 .
  • a plurality of drains 420 may be coupled to multiple drain bus lines 422 respectively, or a part of the drains 420 may be coupled to the same drain bus line 422, and another part of the drains 420 may be coupled to another drain bus line 422. coupling.
  • there can be one gate bus 432 that is, all gates 430 are coupled to the same gate bus 432 .
  • a plurality of gates 430 may be coupled to multiple gate bus lines 432 respectively, or a part of gates 430 may be coupled to the same gate bus 432, and another part of gates 430 may be coupled to another gate bus 432. coupling.
  • the sources 410 , the drains 420 and the gates 430 are divided into one group.
  • the drain bus 422 and the gate bus 432 are located on the same side of the source 410 .
  • the drain bus 422 and the gate bus 432 are arranged on the same side of the source 410, there is no overlap between the drain bus 422, the source 410, and the gate 430, and there is no overlap between the gate bus 432, the source 410, and the drain 420. There is also no overlap. Therefore, there will be no parasitic capacitance between the drain bus 422 and the source 410 and the gate 430 and between the gate bus 432 and the source 410 and the drain 420 .
  • a parasitic capacitance may or may not be generated between the drain bus line 422 and the gate bus line 432 .
  • the gate bus line 432 is located above or below the drain bus line 422. As shown in FIG. parasitic capacitance.
  • the drain bus line 422 at least overlaps the gate 430 , and a parasitic capacitance will be generated at the overlapping portion of the drain bus line 422 and the gate 430 .
  • the drain bus 422 is located on the side of the source 410
  • the gate bus 432 is located above or below the source 410 and the drain 420 , and has an intersection with the source 410 and the drain 420 . stack. There is no overlap between the drain bus 422 and the gate 430 or the gate bus 432 , therefore, no parasitic capacitance will be generated between the drain bus 422 and the gate 430 or the gate bus 432 .
  • the drain bus line 422 and the gate bus line 432 are respectively located on two opposite sides of the source 410 (the drain 420 or the gate 430 ).
  • the drain bus 422 is located on one side of the source 410 , and the gate bus 432 is located on the other side of the source 410 .
  • the drain bus line 422 has no overlap with the source 410 , the gate 430 and the gate bus line 432 .
  • the gate bus 432 has no overlap with the source 410 , the drain 420 and the drain bus 422 . Therefore, there is no parasitic capacitance between the drain bus 422 and the source 410 , the gate 430 and the gate bus 432 .
  • the drain bus line 422 and the gate bus line 432 shown in FIG. 4E can be arranged on different sides of the source electrode 410, so as to avoid overlapping between the drain bus line 422 and the source electrode 410, the drain electrode 420 and the gate electrode 430.
  • the overlap between the bus 432 and the source 410, the drain 420, and the gate 430 is also avoided, and the overlap between the drain bus 422 and the gate bus 432 is also avoided, thereby preventing the source 410, drain 420,
  • the gate 430 and the drain bus 422 and the gate bus 432 overlap each other to generate parasitic capacitance.
  • the embodiment of the present application does not limit the positions of the drain bus line 422 and the gate bus line 432 , which can be reasonably set as required.
  • the multiple sources 410 , the multiple drains 420 and the multiple gates 430 may be divided into multiple groups arranged side by side along the second direction x.
  • the plurality of sources 410 , the plurality of drains 420 and the plurality of gates 430 are divided into two groups arranged side by side along the second direction x.
  • the source electrodes 410 and the drain electrodes 420 in each group are alternately arranged along the first direction y.
  • the sources 410 in each group are located in the same row. In some embodiments, the drains 420 in each group are located in the same row. In some embodiments, the gates 430 in each group are located in the same row.
  • the drain bus line 422 and the gate bus line 432 are disposed on the same side, and both are located on the side of the source electrode 410 away from the gap.
  • the drain bus 422 and the gate bus 432 are arranged on the same side of the source 410 away from the gap, so that there is no overlap between the drain bus 422, the source 410, and the gate 430, and the gate bus 432 and the source 410, the drain There is also no overlap between the 420's. Therefore, there will be no parasitic capacitance between the drain bus 422 and the source 410 and the gate 430 and between the gate bus 432 and the source 410 and the drain 420 .
  • the gate bus line 432 is located above or below the drain bus line 422. As shown in FIG. 5A, the gate bus line 432 overlaps with the drain electrode 420 at least. parasitic capacitance.
  • the drain bus line 422 at least overlaps the gate 430 , and a parasitic capacitance will be generated at the overlapping portion of the drain bus line 422 and the gate 430 .
  • the drain bus line 422 and the gate bus line 432 are disposed on the same side, and both are located on the side of the source electrode 410 close to the gap.
  • the gate bus 432 is located above or below the drain bus 422. There is overlap between the drain bus 422 and the gate 430 and the gate bus 432.
  • the gate bus 432 is at least connected to the source 410, the drain 420 or the drain bus. There is an overlap between 422. At this time, a parasitic capacitance may be generated at the overlapping portion of the gate bus line 432 and the source 410 , the drain 420 or the drain bus line 422 .
  • the drain bus line 422 and the gate bus line 432 are arranged on different sides, and the drain bus line 422 and the gate bus line 432 are respectively located on two opposite sides of the source 410 away from the gap.
  • the drain bus 422 is located on one side of the source 410 away from the gap, and the gate bus 432 is located on the other side opposite to the side of the source 410 away from the gap. At this time, the drain bus line 422 has no overlap with the source 410 , the gate 430 and the gate bus line 432 . The gate bus 432 has no overlap with the source 410 , the drain 420 and the drain bus 422 . Therefore, parasitic capacitance due to overlap among the source 410 , drain 420 , drain bus 422 and gate bus 432 is avoided.
  • the drain bus line 422 and the gate bus line 432 are arranged on different sides, the drain bus line 422 is located on the side of the source 410 away from the gap, and the gate bus line 432 is located on the side of the source 410 close to the gap. side.
  • the drain bus 422 is located on the side of the source 410 away from the gap, and has no overlap with the gate 430 and the gate bus 432 , and no parasitic capacitance will be generated between the drain bus 422 , the gate 430 , and the gate bus 432 .
  • the gate bus 432 is located above or below the drain 420 and overlaps with the drain 420 . At this time, the overlapping portion of the gate bus 432 and the drain 420 will generate parasitic capacitance.
  • the drain bus line 422 and the gate bus line 432 are arranged on different sides, the gate bus line 432 is located on the side of the source 410 away from the gap, and the drain bus line 422 is located at the source 410 close to the gap. side.
  • the gate bus 432 is located on the side of the source 410 away from the gap, and there is no overlap between the source 410 , the drain 420 and the drain bus 422 , and the gate bus 432 and the source 410 , the drain 420 and the drain bus 422 There will be no parasitic capacitance between them.
  • the drain bus line 422 is located above or below the gate 430 and overlaps with the gate 430 . At this time, a parasitic capacitance will be generated at the overlapping portion of the drain bus line 422 and the gate 430 .
  • drain electrodes 420 in the same row have gaps, and there is no gap between the source electrodes 410 and the gate electrodes 430 in the same row. That is, the sources 410 in the same row are connected, and the gates 430 in the same row are connected. At this time, all the drains 420 in each group share a drain bus 422 , and all the gates 430 in two groups share a gate bus 432 .
  • the drain bus line 422 and the gate bus line 432 may be disposed on the same side of the drain 420 , or may be disposed on different sides of the drain 420 .
  • the drain bus lines 422 in the two groups are respectively located on two opposite sides of the drain 420 away from the gap, and the gate bus line 432 is located on the side of the drain 420 away from the gap, and one of the drains
  • the pole bus 422 is disposed on the same side.
  • drain bus lines 422 on a different side from the gate bus line 432 is provided, and the drain bus line 422 has no overlap with the gate 430 and the gate bus line 432 , Therefore, there is no parasitic capacitance between the drain bus line 422 and the gate 430 and the gate bus line 432 .
  • a gate bus 432 and another drain bus 422 on the same side as the gate bus 432 are provided. At this time, there is no overlap between the drain bus 422 and the gate 430, There is also no overlap between the gate bus 432 and the source 410 and the drain 420 . Therefore, there will be no parasitic capacitance between the drain bus 422 and the gate 430 and between the gate bus 432 and the source 410 and the drain 420 .
  • parasitic capacitance may or may not be generated between the drain bus line 422 and the gate bus line 432. parasitic capacitance.
  • the gate bus line 432 is located above or below the drain bus line 422. As shown in FIG. parasitic capacitance.
  • the drain bus line 422 at least overlaps the gate 430 , and a parasitic capacitance will be generated at the overlapping portion of the drain bus line 422 and the gate 430 .
  • the drain bus line 422 and the gate bus line 432 may be arranged on different sides of the drain 420, the drain bus line 422 is located on two opposite sides of the drain 420 away from the gap, and the gate bus line The bus line 432 is located on the side of the drain 420 close to the gap, that is, the area between two sets of drains 420 .
  • FIG. 6C there are gaps between the drain electrodes 420 in the same row and between the source electrodes 410 in the same row, and there is no gap between the gate electrodes 430 in the same row. That is, the gates 430 located in the same row are connected. At this time, all the drains 420 in each group share a drain bus 422 , and all the gates 430 in two groups share a gate bus 432 .
  • the drain bus line 422 and the gate bus line 432 may also be disposed on the same side of the drain 420 , or disposed on different sides of the drain 420 .
  • the drain bus line 422 and the gate bus line 432 can be arranged on the same side of the drain electrode 420, and the drain bus line 422 and the gate bus line 432 are both located away from the drain electrode 420 (or the source electrode 410). side of the gap.
  • FIG. 6C is the same as that of FIG. 6A in which the drain bus lines 422 and the gate bus lines 432 are arranged at the same positions, except that there is a gap between the sources 410 in the same row in FIG. 6C . Therefore, the drain bus line 422 disposed on a different side from the gate bus line 432 does not generate parasitic capacitance between the gate 430 and the gate bus line 432 .
  • the drain bus line 422 disposed on the same side as the gate bus line 432 does not generate parasitic capacitance between the gate 430 .
  • a parasitic capacitance may or may not be generated between the drain bus line 422 and the gate bus line 432 on the same side.
  • the overlapping portion of the gate bus 432 and the drain 420 generates parasitic capacitance.
  • the overlapping portion of the drain bus line 422 and the gate 430 may generate parasitic capacitance.
  • the drain bus line 422 and the gate bus line 432 may be disposed on different sides of the drain electrode 420, and the drain bus line 422 is located on the side of the drain electrode 420 (or source electrode 410) away from the gap,
  • the gate bus 432 is located on the side of the drain 420 (or source 410 ) close to the gap.
  • FIG. 6D is the same as that of FIG. 6B in which the drain bus lines 422 and the gate bus lines 432 are arranged at the same positions, except that there is a gap between the sources 410 in the same row in FIG. 6D . Therefore, there will be no parasitic capacitance between the two drain bus lines 422 and the gate 430 and the gate bus line 432 .
  • the drain bus line 422 and the gate bus line 432 as shown in FIG. 6D can be arranged on different sides of the drain electrode 420, which can avoid overlapping and gate bus lines between the drain bus line 422 and the source electrode 410, the drain electrode 420, and the gate electrode 430.
  • the overlapping between the pole bus 432 and the source 410, the drain 420 and the gate 430 is also avoided.
  • the gate 430 , the drain bus 422 and the gate bus 432 overlap each other to generate parasitic capacitance.
  • the gate electrodes 430 in the same row have gaps, and there is no gap between the source electrodes 410 and the drain electrodes 420 in the same row. That is, the sources 410 located in the same row are connected, and the sources 410 located in the same row are connected. At this time, all the drains 420 in the two groups share a drain bus 422 , and all the gates 430 in each group share a gate bus 432 .
  • drain bus line 422 and the gate bus line 432 may be disposed on the same side of the gate 430 , or may be disposed on different sides of the gate 430 .
  • the gate bus lines 432 in the two groups are respectively located on two opposite sides of the gate 430 away from the gap, and the drain bus 422 is located on the side of the gate 430 away from the gap, and one of the gates
  • the pole bus 432 is disposed on the same side.
  • one of the gate bus lines 432 on the side different from the drain bus line 422 is provided, and the gate bus line 432 is connected to the source 410, the drain electrode 420, and the drain bus line 422. There is no overlap, therefore, no parasitic capacitance will be generated between the gate bus 432 and the source 410 , drain 420 and drain bus 422 .
  • a drain bus line 422 and another gate bus line 432 on the same side as the drain bus line 422 are provided on the other side of the gate 430 away from the gap. At this time, there is no overlap between the drain bus line 422 and the gate 430, There is also no overlap between the gate bus 432 and the source 410 and the drain 420 . Therefore, there will be no parasitic capacitance between the drain bus 422 and the gate 430 and between the gate bus 432 and the source 410 and the drain 420 .
  • parasitic capacitance may or may not be generated between the drain bus line 422 and the gate bus line 432. parasitic capacitance.
  • the gate bus line 432 is located above or below the drain bus line 422. As shown in FIG. parasitic capacitance.
  • the drain bus line 422 at least overlaps the gate 430 , and a parasitic capacitance will be generated at the overlapping portion of the drain bus line 422 and the gate 430 .
  • FIG. 7B there are gaps between the drains 420 in the same row and between the gates 430 in the same row, and there is no gap between the sources 410 in the same row. That is, the sources 410 located in the same row are connected. At this time, all the drains 420 in each group share the same drain bus 422 , and all the gates 430 in each group share a gate bus 432 .
  • the drain bus line 422 and the gate bus line 432 can also be arranged on the same side of the gate 430, and both the drain bus line 422 and the gate bus line 432 are located away from the gate 430 (or the drain 420). side of the gap.
  • drain bus lines 422 and gate bus lines 432 of each group are located on the side of the gate 430 away from the gap.
  • parasitic capacitance may or may not be generated between the drain bus line 422 and the gate bus line 432. parasitic capacitance.
  • the gate bus line 432 is located above or below the drain bus line 422. As shown in FIG. parasitic capacitance.
  • the drain bus line 422 at least overlaps the gate 430 , and a parasitic capacitance will be generated at the overlapping portion of the drain bus line 422 and the gate 430 .
  • FIG. 7C there are gaps between the source electrodes 410 in the same row and between the gate electrodes 430 in the same row, and there is no gap between the drain electrodes 420 in the same row. That is, the drains 420 located in the same row are connected. At this time, all the drains 420 in two groups share a drain bus 422 , and all gates 430 in each group share a gate bus 432 .
  • FIG. 7C is the same as that of FIG. 7A in which the drain bus lines 422 and the gate bus lines 432 are arranged at the same positions, except that there is a gap between the sources 410 in the same row in FIG. 7C .
  • the gate bus 432 disposed on the same side as the drain bus 422 does not generate parasitic capacitance between the source 410 and the drain 420 .
  • a parasitic capacitance may or may not be generated between the drain bus line 422 and the gate bus line 432 on the same side.
  • the overlapping portion of the gate bus 432 and the drain 420 generates parasitic capacitance.
  • the overlapping portion of the drain bus line 422 and the gate 430 may generate parasitic capacitance.
  • FIG. 7D there are gaps between the source electrodes 410 in the same row, the drain electrodes 420 in the same row, and the gate electrodes 430 in the same row. At this time, all the drains 420 in each group share one drain bus 422 , and all the gates 430 in each group share one gate bus 432 .
  • drain bus line 422 and the gate bus line 432 may be disposed on the same side of the gate 430 , or may be disposed on different sides of the gate 430 .
  • the drain bus line 422 and the gate bus line 432 can be arranged on the same side of the gate 430, and both the drain bus line 422 and the gate bus line 432 are located at the gate 430 (the source 410 or the drain 420) away from the side of the gap.
  • FIG. 7D is the same as that of FIG. 7B in which the drain bus lines 422 and the gate bus lines 432 are arranged at the same positions, except that there is a gap between the sources 410 in the same row in FIG. 7D .
  • a parasitic capacitance may or may not be generated between the drain bus line 422 and the gate bus line 432 on the same side.
  • the overlapping portion of the gate bus 432 and the drain 420 generates parasitic capacitance.
  • the overlapping portion of the drain bus line 422 and the gate 430 may generate parasitic capacitance.
  • the drain bus line 422 and the gate bus line 432 can be arranged on different sides of the gate 430, and the drain bus line 422 is located at the gate 430 (source 410 or drain 420) close to the gap
  • the gate bus 432 is located on two opposite sides of the gate 430 (source 410 or drain 420 ) away from the gap.
  • the drain bus line 422 and the gate bus line 432 shown in FIG. The overlap between the bus 432 and the source 410, the drain 420, and the gate 430 is also avoided, and the overlap between the drain bus 422 and the gate bus 432 is also avoided, thereby preventing the source 410, drain 420, The gate 430 and the drain bus 422 and the gate bus 432 overlap each other to generate parasitic capacitance.
  • At least one back hole 412 is disposed under the source electrode 410 .
  • the source 410 is grounded through the back hole 412 .
  • a back hole 412 is disposed under the source electrode 410 .
  • At least two back holes 412 are disposed under the source electrode 410 .
  • the back hole 412 can be circular or square
  • the back hole 412 only needs to be disposed under the source electrode 410 .
  • the size of the back hole 412 in the first direction y does not exceed the size of the source 410 in the first direction y
  • the size of the back hole 412 in the second direction x does not exceed the size of the source 410 in the second direction x.
  • the embodiment of the present application does not limit the number and shape of the back holes 412 , which can be reasonably designed as required.
  • the number, shape and size of the back holes 412 disposed under the plurality of source electrodes 410 may be the same or different.
  • the back hole 412 penetrates from the substrate 401 to the barrier layer 403 , and the bottom of the source 410 close to the substrate 401 serves as the bottom of the back hole 412 .
  • the active area is located under the source electrode 410, that is, the back hole 412 is disposed in the active area. If the bottom of the source 410 is an inactive area, that is, the back hole 412 is disposed in the inactive area.
  • the embodiment of the present application does not limit this, it only needs to ensure that the back hole is disposed under the source electrode 410 .
  • the semiconductor structure 400 provided in the embodiment of the present application further includes a back conductive layer 405 .
  • the backside conductive layer 405 covers the backside of the substrate 401 and the back hole 412 .
  • the source electrode 410 is in contact with the back conductive layer 405 .
  • the source 410 is grounded through the back conductive layer 405 .
  • the back conductive layer 405 can be a single-layer structure or a multi-layer structure. This embodiment of the present application does not limit it.
  • the back conductive layer 405 includes a first conductive layer 405a and a second conductive layer 405b that are sequentially stacked.
  • the first conductive layer 405a is in direct contact with the source 410
  • the second conductive layer 405b is disposed on the side of the first conductive layer 405a away from the substrate 401, and the adhesiveness of the first conductive layer 405a is greater than that of the second conductive layer 405b.
  • the back hole 412 is located under the source 410 , and the source 410 of the semiconductor structure 400 is grounded through the back conductive layer 405 , so as to avoid additional parasitic capacitance and inductance caused by the existence of the source pad 411 .
  • the source 410 can be directly grounded without setting the source pad 411, which avoids the need to connect the adjacent drain pad 421. Air bridges or dielectric bridges are provided between or between adjacent gate pads 431 to cause problems in the process. At the same time, the source electrode 410 directly contacts the back conductive layer 405 , so that the signal transmission path to the source electrode 410 is shortened, thereby reducing the parasitic inductance of the semiconductor structure 400 and improving the frequency characteristic of the semiconductor structure 400 .
  • the back hole 412 does not need to be disposed under the source pad 411 , which reduces the signal transmission path from the source pad 411 to the source 410 , thereby reducing the parasitic inductance of the semiconductor structure 400 .
  • the semiconductor structure 400 includes a substrate 401 and stacked semiconductor layers on the substrate 401 .
  • the stacked semiconductor layers include a channel layer 402 and a barrier layer 403 .
  • the substrate 401 may be, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a sapphire substrate, or a diamond substrate, etc., and the embodiment of the present application does not limit the material of the substrate 401 .
  • the stacked semiconductor layers on the substrate 401 include a nucleation layer, a graded buffer layer, a channel layer 402 , an insertion layer, a barrier layer 403 and a cap layer which are stacked in sequence.
  • the channel layer 402 and the barrier layer 403 form a heterojunction, and a two-dimensional electron gas (two-dimensional electron gas, 2DEG) 404 is generated above the channel layer 402 .
  • 2DEG two-dimensional electron gas
  • the nucleation layer is disposed on the surface of the substrate 401 .
  • the material of the nucleation layer may include one or more of GaN (gallium nitride), AlGaN (aluminum gallium nitride), and AlN (aluminum nitride).
  • the role of the nucleation layer is to improve the quality of the epitaxy, which is beneficial to the growth of the upper epitaxy.
  • the method for forming the nucleation layer may be, for example, metal-organic chemical vapor deposition (MOCVD) growth method or molecular beam epitaxy (molecular beam epitaxy, MBE) growth method.
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the graded buffer layer is disposed on the side of the nucleation layer away from the substrate 401 .
  • the function of the graded buffer layer is that the band gap between the graded buffer layer and the channel layer 402 is different, which can make the potential well depth of the heterojunction formed by the barrier layer 403 and the channel layer 402 deeper, thereby improving the two-dimensional electron gas 404 limits.
  • the buffer layer is generally thicker, and is the main structure for the semiconductor structure 400 to withstand voltage.
  • the MOCVD process can be used to epitaxially grow the AlGaN graded layer whose Al (aluminum) composition gradually decreases.
  • an Al 0.8 Ga 0.2 N layer, an Al 0.5 Ga 0.5 N layer, and an Al 0.2 Ga 0.8 N layer are sequentially formed on the side of the nucleation layer away from the substrate 401 by MOCVD process to form a graded buffer layer.
  • the graded buffer layer in order to reduce the decrease in mobility caused by electron scattering, the graded buffer layer generally adopts an undoped structure.
  • the channel layer 402 is disposed on a side of the graded buffer layer away from the substrate 401 .
  • the material of the channel layer 402 may include one or more of GaN, AlGaN, InAlN (indium aluminum nitride), AlN, ScAlN (scandium aluminum nitride).
  • the method of forming the channel layer 402 may be, for example, MOCVD growth method or MBE growth method.
  • the insertion layer is disposed on the side of the channel layer 402 away from the substrate 401 for improving the mobility of the two-dimensional electron gas 404 .
  • a method for forming the intercalation layer for example, MOCVD growth method or MBE growth method can be used.
  • the barrier layer 403 is disposed on a side of the insertion layer away from the substrate 401 .
  • the material of the barrier layer 403 may include, for example, one or more of GaN, AlGaN, InAlN, AlN, and ScAlN.
  • the method of forming the barrier layer 403 may be, for example, MOCVD growth method or MBE growth method.
  • the materials of the channel layer 402 and the barrier layer 403 are different, and the channel layer 402 and the barrier layer 403 form a heterostructure.
  • the material of the channel layer 402 includes GaN
  • the material of the barrier layer 403 includes AlGaN.
  • the barrier layer 403 is usually not doped, and the barrier layer 403 with unidirectional flow capability is formed under the gate 430 by utilizing the work function difference between it and the subsequently formed gate 430 (usually a metal material). , while ensuring the ability of the gate 430 to control the channel layer 402 , it can also effectively reduce the leakage problem of the gate 430 .
  • the cap layer is disposed on the side of the barrier layer 403 away from the substrate 401 .
  • the material of the cap layer may be GaN or Si 3 N 4 (silicon nitride).
  • MOCVD growth method or MBE growth method can be used to form the cap layer. It can be understood that the setting of the cap layer should not affect the ohmic contact between the source electrode 410 and the drain electrode 420 and the barrier layer 403, which can be achieved by doping or patterning the cap layer (exposing the barrier layer 403). Effect.
  • the thickness of the cap layer is too small to protect the barrier layer 403 . If the thickness of the cap layer is too large, the thickness of the semiconductor structure 400 will be increased.
  • the embodiment of the present application does not limit the stacking of semiconductor layers, as long as at least a heterostructure including a channel layer 402 and a barrier layer 403 is formed on the substrate 401 .
  • the source electrode 410 and the drain electrode 420 are disposed on the barrier layer 403 .
  • the uppermost layer is a cap layer, and the source electrode 410 and the drain electrode 420 are formed on the cap layer.
  • the uppermost layer is the barrier layer 403 , and the source 410 and the drain 420 are formed on the barrier layer 403 . Regardless of the structure, it is sufficient to ensure that the source electrode 410 and the drain electrode 420 form an ohmic contact with the barrier layer 403 .
  • the source electrode 410 and the drain electrode 420 are arranged on the surface of the stacked semiconductor layer (such as the barrier layer 403), and the source electrode 410 and the drain electrode 420 are the closest to the stacked semiconductor layer (such as the barrier layer 403).
  • conductive structure As shown in Figure 8, the source electrode 410 and the drain electrode 420 are arranged on the surface of the stacked semiconductor layer (such as the barrier layer 403), and the source electrode 410 and the drain electrode 420 are the closest to the stacked semiconductor layer (such as the barrier layer 403).
  • the source 410 and the drain 420 are the first-layer conductive structures disposed on the stacked semiconductor layers (eg, the barrier layer 403 ), and no other conductive structures are disposed between them.
  • the gate 430 is located between the source 410 and the drain 420 .
  • the gate 430 is disposed on the barrier layer 403 and forms a Schottky contact with the barrier layer 403 .
  • drain bus line 422 and the gate bus line 432 are disposed on the barrier layer 403 .
  • the drain bus 422 may be formed simultaneously with the drain 420
  • the gate bus 432 may be formed simultaneously with the gate 430 .
  • the semiconductor structure 400 further includes a thickened source 510 and a thickened drain 520 .
  • the thickened source electrode 510 is disposed on the source electrode 410 and is in contact with the source electrode 410 .
  • the thickened drain 520 is disposed on the drain 420 and is in contact with the drain 420 .
  • the embodiment of the present application does not limit the materials of the thickened source electrode 510 and the thickened drain electrode 520 , which may be the same as or different from those of the source electrode 410 and the drain electrode 420 .
  • Thickening the source electrode 510 and thickening the drain electrode 520 is equivalent to increasing the thickness of the source electrode 410 and the drain electrode 420 , reducing the resistance of the source electrode 410 and the drain electrode 420 , thereby improving the current conduction capability of the semiconductor structure 400 .
  • the size of the thickened source 510 and the thickened drain 520 does not need to be the same as the size of the source 410 and the drain 420, they can be larger or smaller than the size of the source 410 and the drain 420, both can play a role. To improve the role of current conduction ability.
  • the semiconductor structure 400 further includes a field plate (field plate, FP) 406 .
  • FP field plate
  • the material of the field plate 406 may be any conductive material.
  • the field plate 406 is arranged on the side of the gate 430 away from the substrate 401, above the region between the gate 430 and the drain 420, and the orthographic projection of the field plate 406 on the substrate 401 is the same as that of the gate 430 on the substrate 401. Orthographic projection overlay.
  • the field plate 406 may be in a floating state without loading any signal.
  • the field plate 406 can also be in contact with the source 410 , and the field plate 406 can also be in contact with the gate 430 .
  • the electric field distribution in the semiconductor structure 400 can be modulated to make the electric field distribution uniform and avoid electric field peaks.
  • the semiconductor structure 400 further includes a first dielectric layer 407 , a second dielectric layer 408 and a third dielectric layer (not shown in FIG. 8 ).
  • the first dielectric layer 407 is located between the gate 430 and the stacked semiconductor layer (eg barrier layer 403 ).
  • the second dielectric layer 408 is located between the gate 430 and the field plate 406 .
  • the third dielectric layer covers the surface of the semiconductor structure 400 , and the third dielectric layer may include a passivation layer (including a dielectric material) or a waterproof layer (including a waterproof material) for protecting the semiconductor structure 400 .
  • the semiconductor structure 400 includes a plurality of semiconductor groups 40 arranged along the second direction x.
  • a plurality of sources 410 , a plurality of drains 420 and a plurality of gates 430 serve as a semiconductor group 40 .
  • each semiconductor group 40 may include one set of source 410 , drain 420 and gate 430 , or may include multiple sets of source 410 , drain 420 and gate 430 .
  • the structures of the plurality of semiconductor groups 40 included in the semiconductor structure 400 may be the same or different.
  • the gate pads 431 in the plurality of semiconductor groups 40 are coupled, the drain pads 421 in the plurality of semiconductor groups 40 are coupled, and the back conductive layers 405 in the plurality of semiconductor groups 40 are coupled.
  • the drain pads 421 in the plurality of semiconductor groups 40 are coupled through a first resistor 423
  • the gate pads 431 in the plurality of semiconductor groups 40 are coupled through a second resistor 433 .
  • the coupling of multiple drain pads 421 through the first resistor 423 or the coupling of multiple gate pads 431 through the second resistor 433 can improve the stability of the semiconductor structure 400 .
  • the gate pads 431 in the plurality of semiconductor groups 40 are integrated, and the drain pads 421 in the plurality of semiconductor groups 40 are integrated.
  • the embodiment of the present application also provides a working method of a semiconductor structure 400, including:
  • the turn-on signal is input to the drain 420 through the drain pad 421 .
  • the turn-on signal is input from pin 1 of the package structure 32 , input to the drain pad 421 through the bonding wire 441 connected to the pin 1 , and then input to the drain 420 through the drain pad 421 .
  • the input of the turn-on signal makes the gate voltage greater than the threshold voltage, and turns on the gate channel.
  • the working signal is input to the drain 420 through the drain pad 421 .
  • start signal in step S1 and the working signal in step S2 may be input by the same signal, or may be input by two different signals in time division, which is not limited in the embodiment of the present application.
  • the working signal is input from the pin 1 of the package structure 32 , input to the drain pad 421 through the bonding wire 441 connected to the pin 1 , and then input to the drain 420 through the drain pad 421 .
  • the initial signal is input to the gate 430 through the gate pad 431 , and under the control of the working signal, the initial signal is amplified and then output from the drain 420 to the drain pad 421 .
  • the gate channel is opened, and the initial signal is input from the pin 2 of the package structure 32, and input to the gate pad 431 through the bonding wire 441 connected to the pin 2, and then the gate The pole pad 431 is input to the gate 430 .
  • the initial signal is amplified, and the amplified initial signal is output from the drain 420 to the drain pad 421, and then output to the package structure through the bonding wire 441 connected to the drain pad 421 32 pin 1.
  • the semiconductor structure 400 provided in the embodiment of the present application includes a substrate 401 , a channel layer 402 and a barrier layer 403 arranged in layers.
  • the semiconductor structure 400 further includes a plurality of sources 410, a plurality of drains 420, a plurality of gates 430, a drain bus 422 and a gate bus 432 arranged on the barrier layer 403, penetrating from the substrate 401 to the barrier layer A plurality of back holes 412 of 403 and a back conductive layer 405 covering the back of the substrate 401 and the back holes 412 .
  • the drain bus 422 is coupled to the drain 420
  • the gate bus 432 is coupled to the gate 430 .
  • At least one back hole 412 is disposed under the source electrode 410 , and the source electrode 410 is in contact with the back conductive layer 405 .
  • the source 410 and the drain 420 are alternately arranged along the first direction y
  • the gate 430 is located between the source 410 and the drain 420
  • the drain bus 422 coupled to the drain 420
  • the gate bus lines 432 coupled to the poles 430 all extend along the first direction y.
  • the number of gates 430 is increased, and the premise of not increasing the size of a single gate 430, that is, the single-finger grid width Therefore, the total gate width of the semiconductor structure 400 is increased, thereby increasing the output power of the semiconductor structure 400 and improving the gain and efficiency of the semiconductor structure 400 .
  • the back hole 412 is disposed under the source electrode 410 , and the back conductive layer 405 directly contacts the source electrode 410 through the back hole 412 to realize the grounding of the source electrode 410 and reduce the complexity of the process. Furthermore, since the source electrode 410 directly contacts the back conductive layer 405 , the signal transmission path to the source electrode 410 is shorter, reducing the parasitic inductance of the semiconductor structure 400 . In addition, the back hole 412 and the back conductive layer 405 are provided under the source 410, so that the source pad 411 and the source bus connecting the source 410 and the source pad 411 are no longer required, and the source bus and the source bus 411 can be avoided.
  • the parasitic capacitance generated by the overlap between the drain bus lines 422 or the gate bus lines 432 further improves the reliability of the semiconductor structure 400 .
  • There is no need to provide the source pad 411 therefore, there is no problem of affecting the matching between the plurality of semiconductor groups 40 due to the limitation of the number of connecting wires between the drain pad 421 or the gate pad 431 .

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Abstract

本申请实施例提供一种半导体结构及其工作方法、功率放大电路、电子设备，涉及半导体技术领域，用于提高高功率半导体器件的总输出功率。半导体结构包括多个半导体组，每个半导体组包括多个源极、多个漏极和多个栅极、漏极焊盘、栅极焊盘以及设置在每个源极下方的至少一个背孔。其中，漏极焊盘和栅极焊盘上均设置有多个键合点。多个源极、多个漏极和多个栅极均位于漏极焊盘和栅极焊盘之间，多个漏极与漏极焊盘耦接，多个栅极与栅极焊盘耦接。在第一方向上，源极、漏极和栅极交替排布，栅极位于源极和漏极之间。漏极焊盘和栅极焊盘均沿第二方向延伸，第一方向为从漏极焊盘到栅极焊盘的方向，第一方向与第二方向相交。

Description

半导体结构及其工作方法、功率放大电路、电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其工作方法、功率放大电路、电子设备。
背景技术
随着半导体科技的发展，具有热导率高、电子漂移速率高、耐高温、化学性质稳定的半导体器件，被广泛应用于高频、高温、微波领域。
高功率半导体器件，例如氮化镓高电子迁移率晶体管(gallium nitride high electron mobility transistor，GaN HEMT)器件，由于其特有的高电子迁移率、高二维电子气面密度、高击穿电场、高沟道电子浓度和高温度稳定性等优点，使得其具备更高的输出功率密度，因而被广泛应用于射频/微波功率放大电路等集成电路中。
为了提高高功率半导体器件的总输出功率，就需要增大器件的总栅宽。通常利用增加栅条的数量来增大总栅宽。然而，由于功率放大电路封装尺寸的限制，能够排布的栅条数量有限。或者，可以通过增大单指栅宽来增大总栅宽。然而，单指栅宽的增大会导致器件的增益降低，影响器件性能。
发明内容
本申请实施例提供一种半导体结构及其工作方法、功率放大电路、电子设备，用于提高高功率半导体器件的总输出功率。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种半导体结构，半导体结构包括多个半导体组。每个半导体组包括多个源极、多个漏极和多个栅极、漏极焊盘和栅极焊盘以及设置在每个源极下方的至少一个背孔。其中，漏极焊盘和栅极焊盘上均设置有多个键合点，每个键合点还连接有键合线。多个源极、多个漏极和多个栅极均位于漏极焊盘和栅极焊盘之间，多个漏极与漏极焊盘耦接，多个栅极与栅极焊盘耦接。在第一方向上，源极、漏极和栅极交替排布，栅极位于源极和漏极之间。漏极焊盘和栅极焊盘均沿第二方向延伸，第一方向为从漏极焊盘到栅极焊盘的方向，第一方向与第二方向相交。
本申请实施例中，漏极焊盘和栅极焊盘位于源极、漏极交替排布方向的相对两侧，源极和漏极的交替排布的方向与漏极焊盘和栅极焊盘延伸的方向相交，栅极位于源极和漏极之间，可以尽可能多的增加栅极的数量，实现在不增加单个栅极的尺寸，即在不增加单指栅宽的前提下，增加了半导体结构的总栅宽，进而提高了半导体结构的输出功率，提高了半导体结构的增益和效率。
同时，背孔设置在源极的下方，实现源极接地，降低了工艺的复杂度。同时，使信号传输至源极的路径更短，减小了半导体结构的寄生电感。另外，源极通过背孔实现接地，也就无需再设置源极焊盘以及连接源极与源极焊盘的源极总线，能够避免源极总线与漏极或者栅极之间交叠而产生的寄生电容，进而提高了半导体结构的可靠性。
在一些实施例中，半导体结构还包括漏极总线和栅极总线；漏极总线与多个漏极和漏极焊盘分别耦接；栅极焊盘与多个栅极和栅极焊盘分别耦接；漏极总线和栅极总线均沿第一方向延伸；漏极总线和栅极总线位于漏极沿第二方向相对的两侧。利用漏极总线实现漏极与漏极焊盘耦接，利用栅极总线实现栅极与栅极焊盘耦接，且漏极总线和栅极总线位于漏极沿第二方向相对的两侧，避免漏极总线和栅极总线与源极、漏极或者栅极产生交叠，进而避免漏极总线和栅极总线与源极、漏极或者栅极之间相互交叠产生的寄生电容。
在一些实施例中，漏极总线沿第二方向的尺寸小于键合点沿第二方向的尺寸，栅极总线沿第二方向的尺寸小于键合点沿第二方向的尺寸。漏极总线和栅极总线上均无法设置键合点以及与键合点连接的键合线。
在一些实施例中，多个源极、多个漏极和多个栅极划分为沿第二方向并排设置的多组，每组中的源极和漏极沿第一方向交替排布。节省了沿第二方向漏极总线或者栅极总线占用的面积。
在一些实施例中，位于同一排的源极之间具有间隙。能够根据实际情况合理设置漏极总线和栅极总线的位置。
在一些实施例中，位于同一排的栅极之间具有间隙。能够根据实际情况合理设置漏极总线和栅极总线的位置。
在一些实施例中，位于同一排的漏极之间具有间隙。能够根据实际情况合理设置漏极总线和栅极总线的位置。
在一些实施例中，漏极总线和栅极总线一者位于漏极远离间隙的侧面，另一者位于漏极靠近间隙的侧面。漏极总线和栅极总线之间不存在交叠，不产生寄生电容。
在一些实施例中，多个源极、多个漏极和多个栅极划分为沿第二方向并排设置的两组；每组中的漏极与同一条漏极总线耦接，每条漏极总线位于漏极远离间隙一侧；多个栅极与同一条栅极总线耦接，栅极总线位于漏极靠近间隙一侧。漏极总线和栅极总线设置于漏极的不同侧，避免漏极总线与源极、漏极以及栅极之间产生交叠，避免栅极总线与源极、漏极以及栅极之间产生交叠，同时，也避免了漏极总线和栅极总线之间产生交叠，进而避免源极、漏极、栅极漏极总线以及栅极总线之间相互交叠产生的寄生电容。
在一些实施例中，多个源极、多个漏极和多个栅极划分为沿第二方向并排设置的两组；每组中的栅极与同一条栅极总线耦接，每条栅极总线位于漏极远离间隙一侧；多个漏极与同一条漏极总线耦接，漏极总线位于漏极靠近间隙一侧。漏极总线和栅极总线设置于漏极的不同侧，避免漏极总线与源极、漏极以及栅极之间产生交叠，避免栅极总线与源极、漏极以及栅极之间产生交叠，同时，也避免了漏极总线和栅极总线之间产生交叠，进而避免源极、漏极、栅极漏极总线以及栅极总线之间相互交叠产生的寄生电容。
在一些实施例中，源极下方设置有至少两个背孔。源极下方设置背孔能够减小半导体结构的寄生电感，提升半导体结构的频率特性。
在一些实施例中，多个半导体组沿第二方向排布，键合点沿第二方向在漏极焊盘上排布；键合点沿第二方向在栅极焊盘上排布。多个半导体组并联排布形成的半导体 结构为大功率器件。
在一些实施例中，多个半导体组中的栅极焊盘耦接，多个半导体组中的漏极焊盘耦接。实现了信号的同步传输。
在一些实施例中，半导体结构还包括：依次层叠设置的衬底、沟道层以及势垒层；源极、漏极以及栅极均设置于势垒层上。源极和漏极分别与势垒层形成欧姆接触
在一些实施例中，背孔从衬底贯穿至势垒层；半导体结构还包括背面导电层；背面导电层覆盖衬底的背面和背孔；源极与背面导电层接触。背面导电层通过背孔与源极直接接触，实现源极接地，降低了工艺的复杂度。源极直接接触背面导电层，使信号传输至源极的路径更短，减小了半导体结构的寄生电感。
本申请实施例的第二方面，提供一种半导体结构的工作方法，半导体结构包括多个半导体组，每个半导体组包括：多个源极、多个漏极和多个栅极；漏极焊盘和栅极焊盘；多个漏极与漏极焊盘耦接，多个栅极与栅极焊盘耦接；漏极焊盘和栅极焊盘上均设置有多个键合点；其中，多个源极、多个漏极和多个栅极均位于漏极焊盘和栅极焊盘之间，在第一方向上，源极、漏极以及栅极交替排布；栅极位于源极和漏极之间；漏极焊盘和栅极焊盘均沿第二方向延伸，第一方向为从漏极焊盘到栅极焊盘的方向第一方向与第二方向相交；多个背孔，多个源极中的每个源极的下方设置有至少一个背孔；源极通过背孔接地；半导体结构的工作方法包括：工作信号通过漏极焊盘输入至漏极；初始信号通过栅极焊盘输入至栅极，在工作信号的控制下，对初始信号进行放大后从漏极输出至漏极焊盘。
本申请实施例提供的半导体结构的工作方法，半导体结构包括第一方面的半导体结构，其有益效果与半导体结构的有益效果相同，此处不再赘述。
本申请实施例的第三方面，提供一种功率放大电路，包括封装结构以及如第一方面任一项的半导体结构，半导体结构封装于封装结构内部。
本申请实施例提供的功率放大电路包括第一方面的半导体结构，其有益效果与半导体结构的有益效果相同，此处不再赘述。
本申请实施例的第四方面，提供一种电子设备，包括功率放大器及天线，功率放大器用于将射频信号放大后输出至天线向外辐射，功率放大器包括如第三方面的功率放大电路。
本申请实施例提供的电子设备包括第一方面的半导体结构，其有益效果与半导体结构的有益效果相同，此处不再赘述。
附图说明
图1A为本申请实施例提供的一种电子设备的框架示意图；
图1B为本申请实施例提供的一种基站的框架示意图；
图1C为本申请实施例提供的一种功率放大电路的框架示意图；
图2A为本申请实施例提供的一种半导体结构的结构示意图；
图2B为本申请实施例提供的一种半导体结构的结构示意图；
图3A为本申请实施例提供的另一种半导体结构的结构示意图；
图3B为本申请实施例提供的另一种半导体结构的结构示意图；
图4A为本申请实施例提供的又一种半导体结构的结构示意图；
图4B为本申请实施例提供的又一种半导体结构的结构示意图；
图4C为本申请实施例提供的又一种半导体结构的结构示意图；
图4D为本申请实施例提供的又一种半导体结构的结构示意图；
图4E为本申请实施例提供的又一种半导体结构的结构示意图；
图5A为本申请实施例提供的又一种半导体结构的结构示意图；
图5B为本申请实施例提供的又一种半导体结构的结构示意图；
图5C为本申请实施例提供的又一种半导体结构的结构示意图；
图5D为本申请实施例提供的又一种半导体结构的结构示意图；
图5E为本申请实施例提供的又一种半导体结构的结构示意图；
图6A为本申请实施例提供的又一种半导体结构的结构示意图；
图6B为本申请实施例提供的又一种半导体结构的结构示意图；
图6C为本申请实施例提供的又一种半导体结构的结构示意图；
图6D为本申请实施例提供的又一种半导体结构的结构示意图；
图7A为本申请实施例提供的又一种半导体结构的结构示意图；
图7B为本申请实施例提供的又一种半导体结构的结构示意图；
图7C为本申请实施例提供的又一种半导体结构的结构示意图；
图7D为本申请实施例提供的又一种半导体结构的结构示意图；
图7E为本申请实施例提供的又一种半导体结构的结构示意图；
图8为沿图7E中A1-A2向的剖视图；
图9为本申请实施例提供的又一种半导体结构的结构示意图；
图10为本申请实施例提供的半导体结构的工作方法的流程图。
附图标记：
100-电子设备；110-处理器；120-外部存储器接口；121-内部存储器；130-通用串行总线接口；140-充电管理模块；141-电源管理模块；142-电池；1-天线；2-天线；150-移动通信模块；160-无线通信模块；170-音频模块；170A-扬声器；170B-受话器；170C-麦克风；170D-耳机接口；180-传感器模块；190-摄像头；191-显示屏；200-基站；21-BBU；22-RRU；23-天线；221-数字中频模块；222-收发信机模块；223-功率放大器；224-滤波器；30-功率放大电路；31-集成电路；32-封装结构；321-散热基板；322-封装管壳；400-半导体结构；40-半导体组；410-源极；420-漏极；430-栅极；440-键合点；441-键合线；411-源极焊盘；421-漏极焊盘；431-栅极焊盘；412-背孔；422-漏极总线；432-栅极总线；423-第一电阻；433-第二电阻；401-衬底；402-沟道层；403-势垒层；404-二维电子气；405-背面导电层；405a-第一导电层；405b-第二导电层；406-场板；407-第一介质层；408-第二介质层；510-加厚源极；520-加厚漏极。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下对本申请的实施例中的技术术语说明如下：
半导体：半导体是一种常温下导电性能介于导体与绝缘体之间的材料；其中，半导体包括本征半导体和杂质半导体。不含杂质和缺陷的纯净半导体，其内部电子和空 穴浓度相等，称为本征半导体。掺入一定量杂质的半导体称为杂质半导体或非本征半导体。其中，杂质半导体中掺入的杂质能够提供一定浓度的载流子(如空穴或电子)，其中掺杂提供电子杂质(如5价的磷元素)的杂质半导体也称作电子型半导体或N(negative，负)型半导体，掺杂提供空穴杂质(如3价的硼元素)的杂质半导体也称作空穴型半导体或P(positive，正)型半导体，掺杂能够改善本征半导体的导电性，通常载流子浓度越大，半导体的电阻率越低，导电性也越好。在本申请的实施例中，采用半导体(或者说采用半导体材料)制作的器件中的层结构称为半导体层。
以下，本申请实施例中，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本申请实施例中，“上”、“下”、“左”以及“右不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
在本申请实施例中，“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。在本申请中，“至少一个(层)”是指一个(层)或者多个(层)，“多个(层)”是指两个(层)或两个(层)以上。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。
本申请实施例中参照作为理想化示例性附图的剖视图和/或平面图和/或等效电路图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可 设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本申请实施例提供一种电子设备，该电子设备例如可以为激光雷达驱动器、激光器、探测器、雷达、5G(the 5th generation mobile network，第五代移动通信技术)通信设备等不同类型的用户设备或终端设备；该电子设备也可以为基站等网络设备。电子设备也可以是用于上述电子设备中的功率放大器等装置。本申请实施例对上述电子设备的具体形式不做特殊限制。
示例性的，本申请实施例提供的电子设备为手机，图1A示出了一种电子设备100的结构示意图。电子设备100可以包括处理器110，外部存储器接口120，内部存储器121，通用串行总线(universal serial bus，USB)接口130，充电管理模块140，电源管理模块141，电池142，天线1，天线2，移动通信模块150，无线通信模块160，音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，传感器模块180，摄像头190以及显示屏191等。
可以理解的是，本申请的实施例示意的结构并不构成对电子设备100的具体限定。在本申请另一些实施例中，电子设备100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
处理器110可以包括一个或多个处理单元，例如：处理器110可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
处理器110中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器110中的存储器为高速缓冲存储器。该存储器可以保存处理器110刚用过或循环使用的指令或数据。如果处理器110需要再次使用该指令或数据，可从该存储器中直接调用。避免了重复存取，减少了处理器110的等待时间，因而提高了系统的效率。
在一些实施例中，处理器110可以包括一个或多个接口。接口可以包括集成电路(inter-integrated circuit，I2C)接口，集成电路内置音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口，用户标识模块(subscriber identity module，SIM)接口，和/或通用串行总线(universal serial bus，USB)接口等。
充电管理模块140用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器。在一些有线充电的实施例中，充电管理模块140可以通过USB 接口130接收有线充电器的充电输入。在一些无线充电的实施例中，充电管理模块140可以通过电子设备100的无线充电线圈接收无线充电输入。充电管理模块140为电池142充电的同时，还可以通过电源管理模块141为电子设备100供电。
电源管理模块141用于连接电池142，充电管理模块140与处理器110。电源管理模块141接收电池142和/或充电管理模块140的输入，为处理器110，内部存储器121，显示屏191，摄像头190，和无线通信模块160等供电。电源管理模块141还可以用于监测电池容量，电池循环次数，电池健康状态(漏电，阻抗)等参数。在其他一些实施例中，电源管理模块141也可以设置于处理器110中。在另一些实施例中，电源管理模块141和充电管理模块140也可以设置于同一个器件中。
电子设备100的无线通信功能可以通过天线1，天线2，移动通信模块150，无线通信模块160，调制解调处理器以及基带处理器等实现。
天线1和天线2用于发射和接收电磁波信号。电子设备100中的每个天线可用于覆盖单个或多个通信频带。不同的天线还可以复用，以提高天线的利用率。例如：可以将天线1复用为无线局域网的分集天线。在另外一些实施例中，天线可以和调谐开关结合使用。
移动通信模块150可以提供应用在电子设备100上的包括2G/3G/4G/5G等无线通信的解决方案。移动通信模块150可以包括一个或多个滤波器，开关，功率放大器，低噪声放大器(low noise amplifier，LNA)等。移动通信模块150可以由天线1接收电磁波，并对接收的电磁波进行滤波，放大等处理，传送至调制解调处理器进行解调。移动通信模块150还可以对经调制解调处理器调制后的信号放大，经天线1转为电磁波辐射出去。在一些实施例中，移动通信模块150的至少部分功能模块可以被设置于处理器110中。在一些实施例中，移动通信模块150的至少部分功能模块可以与处理器110的至少部分模块被设置在同一个器件中。
调制解调处理器可以包括调制器和解调器。其中，调制器用于将待发送的低频基带信号调制成中高频信号。解调器用于将接收的电磁波信号解调为低频基带信号。随后解调器将解调得到的低频基带信号传送至基带处理器处理。低频基带信号经基带处理器处理后，被传递给应用处理器。应用处理器通过音频设备(不限于扬声器170A，受话器170B等)输出声音信号，或通过显示屏191显示图像或视频。在一些实施例中，调制解调处理器可以是独立的器件。在另一些实施例中，调制解调处理器可以独立于处理器110，与移动通信模块150或其他功能模块设置在同一个器件中。
无线通信模块160可以提供应用在电子设备100上的包括无线局域网(wireless local area networks，WLAN)(如无线保真(wireless fidelity，Wi-Fi)网络)，蓝牙(bluetooth，BT)，全球导航卫星系统(global navigation satellite system，GNSS)，调频(frequency modulation，FM)，近距离无线通信技术(near field communication，NFC)，红外技术(infrared，IR)等无线通信的解决方案。无线通信模块160可以是集成一个或多个通信处理模块的一个或多个器件。无线通信模块160经由天线2接收电磁波，将电磁波信号调频以及滤波处理，将处理后的信号发送到处理器110。无线通信模块160还可以从处理器110接收待发送的信号，对其进行调频，放大，经天线2转为电磁波辐射出去。
在一些实施例中，电子设备100的天线1和移动通信模块150耦合，天线2和无线通信模块160耦合，使得电子设备100可以通过无线通信技术与网络以及其他设备通信。该无线通信技术可以包括全球移动通讯系统(global system for mobile communications，GSM)，通用分组无线服务(general packet radio service，GPRS)，码分多址接入(code division multiple access，CDMA)，宽带码分多址(wideband code division multiple access，WCDMA)，时分码分多址(time-division code division multiple access，TD-SCDMA)，长期演进(long term evolution，LTE)，BT，GNSS，WLAN，NFC，FM，和/或IR技术等。该GNSS可以包括全球卫星定位系统(global positioning system，GPS)，全球导航卫星系统(global navigation satellite system，GLONASS)，北斗卫星导航系统(beidou navigation satellite system，BDS)，准天顶卫星系统(quasi-zenith satellite system，QZSS)和/或星基增强系统(satellite based augmentation systems，SBAS)。
电子设备100通过GPU，显示屏191，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏191和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。处理器110可包括一个或多个GPU，其执行程序指令以生成或改变显示信息。
显示屏191用于显示图像，视频等。显示屏191包括显示面板。显示面板可以采用液晶显示屏(liquid crystal display，LCD)，有机发光二极管(organic light-emitting diode，OLED)，有源矩阵有机发光二极体或主动矩阵有机发光二极体(active-matrix organic light emitting diode，AMOLED)，柔性发光二极管(flex light-emitting diode，FLED)，Miniled，MicroLed，Micro-oLed，量子点发光二极管(quantum dot light emitting diodes，QLED)等。在一些实施例中，电子设备100可以包括1个或N个显示屏191，N为大于1的正整数。电子设备100可以通过ISP，摄像头190，视频编解码器，GPU，显示屏191以及应用处理器等实现拍摄功能。
ISP用于处理摄像头190反馈的数据。例如，拍照时，打开快门，光线通过镜头被传递到摄像头感光元件上，光信号转换为电信号，摄像头感光元件将电信号传递给ISP处理，转化为肉眼可见的图像。ISP还可以对图像的噪点，亮度，肤色进行算法优化。ISP还可以对拍摄场景的曝光，色温等参数优化。在一些实施例中，ISP可以设置在摄像头190中。
摄像头190用于捕获静态图像或视频。物体通过镜头生成光学图像投射到感光元件。感光元件可以是电荷耦合器件(charge coupled device，CCD)或互补金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)光电晶体管。感光元件把光信号转换成电信号，之后将电信号传递给ISP转换成数字图像信号。ISP将数字图像信号输出到DSP加工处理。DSP将数字图像信号转换成标准的RGB，YUV等格式的图像信号。在一些实施例中，电子设备100可以包括1个或N个摄像头190，N为大于1的正整数。
外部存储器接口120可以用于连接外部存储卡，例如Micro SD卡，实现扩展电子设备100的存储能力。外部存储卡通过外部存储器接口120与处理器110通信，实现数据存储功能。例如将音乐，视频等文件保存在外部存储卡中。
内部存储器121可以用于存储一个或多个计算机程序，该一个或多个计算机程序 包括指令。处理器110可以通过运行存储在内部存储器121的上述指令，从而使得电子设备100执行各种功能应用和数据处理等。内部存储器121可以包括存储程序区和存储数据区。其中，存储程序区可存储操作系统；该存储程序区还可以存储一个或多个应用程序(比如图库、联系人等)等。存储数据区可存储电子设备100使用过程中所创建的数据(比如照片，联系人等)等。此外，内部存储器121可以包括高速随机存取存储器，还可以包括非易失性存储器，例如一个或多个磁盘存储器件，闪存器件，通用闪存存储器(universal flash storage，UFS)等。在另一些实施例中，处理器110通过运行存储在内部存储器121的指令，和/或存储在设置于处理器中的存储器的指令，来使得电子设备100执行各种功能应用和数据处理。
电子设备100可以通过音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，以及应用处理器等实现音频功能。例如音乐播放，录音等。
音频模块170用于将数字音频信息转换成模拟音频信号输出，也用于将模拟音频输入转换为数字音频信号。音频模块170还可以用于对音频信号编码和解码。在一些实施例中，音频模块170可以设置于处理器110中，或将音频模块170的部分功能模块设置于处理器110中。
扬声器170A，也称“喇叭”，用于将音频电信号转换为声音信号。电子设备100可以通过扬声器170A收听音乐，或收听免提通话。
受话器170B，也称“听筒”，用于将音频电信号转换成声音信号。当电子设备100接听电话或语音信息时，可以通过将受话器170B靠近人耳接听语音。
麦克风170C，也称“话筒”，“传声器”，用于将声音信号转换为电信号。当拨打电话或发送语音信息时，用户可以通过人嘴靠近麦克风170C发声，将声音信号输入到麦克风170C。电子设备100可以设置一个或多个麦克风170C。在另一些实施例中，电子设备100可以设置两个麦克风170C，除了采集声音信号，还可以实现降噪功能。在另一些实施例中，电子设备100还可以设置三个，四个或更多麦克风170C，实现采集声音信号，降噪，还可以识别声音来源，实现定向录音功能等。
耳机接口170D用于连接有线耳机。耳机接口170D可以是USB接口130，也可以是3.5mm的开放移动电子设备平台(open mobile terminal platform，OMTP)标准接口，美国蜂窝电信工业协会(cellular telecommunications industry association of the USA，CTIA)标准接口。
传感器模块180可以包括压力传感器，陀螺仪传感器，气压传感器，磁传感器，加速度传感器，距离传感器，接近光传感器，指纹传感器，温度传感器，触摸传感器，环境光传感器，骨传导传感器等。
在本申请的实施例中，触摸传感器，也称“触控器件”。触摸传感器可以设置于显示屏191，由触摸传感器与显示屏191组成触摸屏，也称“触控屏”。触摸传感器用于检测作用于其上或附近的触摸操作。触摸传感器可以将检测到的触摸操作传递给应用处理器，以确定触摸事件类型。可以通过显示屏提供与触摸操作相关的视觉输出。在另一些实施例中，也可以设置有多个触摸传感器形成的触控传感器阵列的触控面板以外挂形式设置于显示面板的表面。在另一些实施例中，触摸传感器也可以与显示屏191所处的位置不同。本申请的实施例中对触控传感器的形式不做限定，例如可以是电容、 或压敏电阻等器件。
另外，上述电子设备100中还可以包括按键、马达、指示器以及用户标识模块(subscriber identification module，SIM)卡接口等一种或多种部件，本申请的实施例对此不做任何限制。
示例性的，本申请的实施例提供的电子设备为5G基站，5G基站可分为基带处理单元(base band unit，BBU)-有源天线单元(active antenna unit，AAU)、集中单元-分布单元(central unit-distribute unit，CU-DU)-AAU、BBU-射频拉远单元(remote radio unit，RRU)-天线(antenna)、CU-DU-RRU-Antenna、一体化5G基站(5G node base station，gNB)-等不同的架构。
图1B示例一种BBU-RRU架构的基站200。基站200可以包括BBU21、RRU22和天线23；其中BBU21与RRU22通过光纤连接，两者之间的接口是基于开放式通用公共射频接口(common public radio interface，CPRI)及开放式基站架构(open base station architecture initiative，OBSAI)。其中，BBU21将生成的基带信号通过RRU22处理后发送至天线23进行发射。RRU22包括数字中频模块221、收发信机模块222、功率放大器223(power amplifier，PA)以及滤波器224。其中，数字中频模块221用于光纤传输的基带信号的调制解调、数字上下变频、数字模拟转换(digital to analog converter，D/A)等形成中频信号；收发信机模块222完成中频信号到射频信号的变换；功率放大器223用于将小功率的射频信号进行功率放大；滤波器224用于对射频信号进行滤波，然后将射频信号通过天线23发射出去。
本申请实施例还提供一种功率放大电路，可以应用于图1A所示的电子设备100中移动通信模块150或无线通信模块160的功率放大器中，也可以应用于上述图1B所示的基站200中RRU22的功率放大器中。当然具体应用场景不限于上述图1A示出的电子设备100、图1B示出的基站200。可以理解的是，任意需要使用功率放大器中的功率放大电路对信号进行放大的上述电子设备均属于本申请的实施例的应用场景。
示例的，如图1C示意一种功率放大电路30。功率放大电路30包括集成电路31以及封装结构32，其中集成电路31封装于封装结构32内部。如图1C所示，提供了一种功率放大电路30的具体封装结构，集成电路31封装于功率放大电路30的封装结构32中。
如图1C所示，封装结构32具体包括：散热基板321，其中为了提高散热基板321的导电性以及散热性，散热基板321可以采用复合材料，例如铜Cu/钼Mo/铜Cu形成的叠层结构。集成电路31通过烧结银粘接或者直接焊接在散热基板321上。
其中，该集成电路31包括至少一个晶体管，晶体管的部分电极(例如可以是源极S)与散热基板321导通，以实现源极S接地。晶体管的部分电极(例如漏极D和栅极G)的电极焊盘通过键合线(bond wire)键合(bonding)连接到管脚，具体的，漏极D的电极焊盘通过键合线键合连接到管脚1，栅极G的电极焊盘通过键合线键合连接到管脚2。管脚设置在绝缘层(例如可以是绝缘陶瓷)上，绝缘层通过绝缘粘接剂粘接于散热基板321上。
此外，封装结构32包括封装管壳322，封装管壳322通过绝缘粘接剂与散热基板321粘接，并且管脚的一端从封装结构32露出以连接其他电路，其中集成电路31设 置于封装管壳322与散热基板321包围的空间中。
示例一种高功率半导体器件，例如：氮化镓高电子迁移率晶体管(gallium nitride high electron mobility transistor，GaN HEMT)器件，由于其具有高击穿电场、高沟道电子浓度、高电子迁移率和高温度稳定性等优点，因而被广泛用于作为集成电路31中的晶体管。下面以本申请实施例提供的半导体结构为HEMT器件为例进行示意说明。
如图2A所示，半导体结构400主要包括多个源极410、多个漏极420、多个栅极430、漏极焊盘421、栅极焊盘431以及背孔412。其中，源极410和漏极420沿第二方向x交替排布，栅极430位于源极410和漏极420之间，且源极410、漏极420和栅极430均沿第一方向y延伸。背孔412位于源极410下方，通过背孔412将源极410直接连接到半导体结构400的背面接地。漏极焊盘421与漏极420耦接，栅极焊盘431与栅极430耦接，且漏极焊盘421和栅极焊盘431分别位于源极410沿第一方向y相对的两端。其中，沿第一方向y，单个栅极430的尺寸h1称之为单指栅宽(Wgu)。
在一些应用中(例如集成电路31为功率放大电路30中的电路结构)，为了增大功率放大电路30的总输出功率或者总栅宽(所有单指栅宽的总和)，如图2B所示，则将多个半导体组40进行并联形成半导体结构400以增大总输出功率或者总栅宽，半导体结构400中栅极430沿第一方向y延伸，且多个栅极430沿第二方向x并联设置，漏极焊盘421和栅极焊盘431上均设置有键合点440，与每一键合点440还有与其连接的键合线441。由于功率放大电路30的封装结构32长度有限，能够并联设置的半导体结构400的数量有限，因此，限制了半导体结构400中栅极430的数量。受到封装结构32长度的约束，则不得不通过增大单指栅宽来增大半导体结构400的总栅宽。然而，单指栅宽的增大会导致信号沿栅极430传输的路径变长，导致半导体结构400的增益降低，影响半导体结构400性能。同时，单指栅宽的增大会导致半导体结构400的散热性能变差，影响半导体结构400的效率。
基于此，为了增大半导体结构400的总栅宽同时不影响其性能，通常通过改变半导体结构400的材料或者参数来提高总输出功率，进而减小单指栅宽。本申请实施例提供一种半导体结构400，如图3A所示，半导体结构400包括多个源极410、多个漏极420、多个栅极430、源极焊盘411、漏极焊盘421以及栅极焊盘431。
源极410和漏极420沿第一方向y交替排布，栅极430位于源极410和漏极420之间，源极410、漏极420和栅极430沿第二方向x延伸。
其中，多个源极410、多个漏极420和多个栅极430可以划分为沿第二方向x并排设置的两组，位于同一排的源极410之间具有间隙。每组中的栅极430与同一条栅极总线432耦接，栅极总线432位于漏极420远离间隙一侧，栅极总线432与栅极焊盘431耦接。多个漏极420与同一条漏极总线422耦接，漏极总线422位于漏极420靠近间隙一侧，漏极总线422与漏极焊盘421耦接。也就是说，源极410和漏极420呈插指状交叉设置。漏极焊盘421和栅极焊盘431分别位于漏极总线422相对的两侧。每组中的源极410与同一源极焊盘411耦接，源极焊盘411位于栅极总线432远离源极410一侧。也就是说，沿第二方向x，两组中的源极焊盘411分别位于一排源极410相对的两侧。源极焊盘411、漏极焊盘421以及栅极焊盘431均需要通过键合线441键合连接到封装结构32。
这样一来，该半导体结构400通过增加栅极430的数量增大总栅宽，避免了因为增加单指栅宽而影响半导体结构400性能的问题。
如图3B所示，多个半导体组40并联形成大功率的半导体结构400时，能够实现在不增大半导体结构400单指栅宽的前提下，增大半导体结构400的总栅宽。这时，源极焊盘411、漏极焊盘421和栅极焊盘431上均设置有键合点440，以及与每个键合点440连接的键合线441。源极焊盘411、漏极焊盘421以及栅极焊盘431分别通过键合线441键合连接到封装结构32。
多个半导体结构400中的源极410需要电性连接至源极焊盘411，漏极420需要电性连接至漏极焊盘421，栅极430需要电性连接至栅极焊盘431。然而，由于源极焊盘411的存在，使得相邻的栅极焊盘431或者相邻漏极焊盘421之间无法直接进行耦接。因此，在相邻漏极焊盘421或者相邻栅极焊盘431之间的区域，需要通过介质桥(相邻漏极焊盘421之间的区域设置介质层，源极焊盘411两侧的漏极焊盘421通过介质层上的跨桥电性连接；或者，相邻栅极焊盘431之间的区域设置介质层，源极焊盘411两侧的栅极焊盘431通过介质层上的跨桥电性连接)或空气桥(相邻漏极焊盘421之间的区域，漏极焊盘421跳起，在源极焊盘411与漏极焊盘421之间留有间隙；或者，相邻栅极焊盘431之间的区域，栅极焊盘431跳起，在源极焊盘411与栅极焊盘431之间留有间隙)的方式使漏极焊盘421或者栅极焊盘431跨过之间的区域实现电性连接。
这就导致：一方面，半导体结构400中需要制作空气桥或者介质桥，工艺复杂，增加了工艺难度。而且，空气桥结构不稳定，在后续工艺中容易造成空气桥的桥体塌裂，增加半导体结构400的可靠性风险。另一方面，由于漏极焊盘421或者栅极焊盘431之间还需要通过键合线441连接至封装结构32，从漏极焊盘421或者栅极焊盘431至封装结构32的键合线441较长，会增加半导体结构400的寄生电感，影响半导体结构400的频率特性，影响半导体结构400性能。再一方面，源极410引出的接地线会和半导体结构400中其他引线交叠而产生寄生电容。
另外，由于源极焊盘411的存在，导致漏极焊盘421和栅极焊盘431沿第二方向x的长度较小，限制了漏极焊盘421或者栅极焊盘431之间连接引线的数量，影响多个半导体组40之间的匹配性，进而影响半导体结构400的性能。因此，该半导体结构400受工艺限制无法做成多个并联的大功率器件。
基于此，为了降低半导体结构400的寄生电感和寄生电容，如图4A所示，本申请实施例还提供一种半导体结构400。半导体结构400包括多个半导体组40。
半导体结构400上还设置有多个键合点440以及与每个键合点440连接的键合线441。
其中，键合点440沿第二方向x在漏极焊盘421上排布，键合点440沿第二方向x在栅极焊盘431上排布。
为了图示清楚，以下均以部分半导体结构400(半导体组40)为例进行介绍。
如图4B所示，半导体结构400主要包括多个源极410、多个漏极420、多个栅极430、漏极焊盘421、栅极焊盘431以及多个背孔412。
其中，源极410、漏极420以及栅极430位于有源区(active area，AA)。漏极焊 盘421和栅极焊盘431位于无源区。
多个源极410、多个漏极420和多个栅极430均位于漏极焊盘421和栅极焊盘431之间。
多个源极410和多个漏极420沿第一方向y交替排布，第一方向y为从漏极焊盘421到栅极焊盘431的方向。
漏极焊盘421和栅极焊盘431均沿第二方向x延伸，第一方向y与第二方向x相交，例如：第一方向y与第二方向x垂直。
其中，漏极焊盘421和栅极焊盘431上均设置有多个键合点440，每个键合点440还与键合线441连接。键合线441用于将漏极焊盘421和栅极焊盘431分别连接至封装结构32上的对应管脚。
具体的，键合线441用于将漏极焊盘421连接至封装结构32上的管脚1，键合线还441用于栅极焊盘431连接至封装结构32上的管脚2。
键合是指将两种同质或者异质材料结果表面处理，在一定条件下直接结合，使两者材料实现电学或机械实现电气互连的一种工艺。
键合线441与漏极焊盘421或栅极焊盘431的键合方式，例如可以是在制备漏极焊盘421或栅极焊盘43时，直接接触键合。键合点440与键合线441键合的方式，例如可以是通过微凸点键合(micro bump bonding)，埋入式微凸点键合(embedded bump bonding)，混合键合(hybrid bonding，HB)，表面激活键合(surface activated bonding，SAB)，原子扩散键合(atomic diffusion bonding，ADB)，引线键合(wire bonding，WB)等工艺实现键合。
键合点440和键合线441的材料可以包括金(Au)。
源极410和漏极420的材料可以是单质，也可以是合金或多层叠层金属。
例如，源极410和漏极420的材料包括钛(Ti)、金(Au)、铂(Pt)元素中的至少一种。示例的，源极410和漏极420的材料包括氮化钛(TiN)。
在一些实施例中，源极410和漏极420均为条状，且沿第二方向x延伸。
栅极430位于源极410和漏极420之间，也就是说，栅极430也沿第二方向x延伸。栅极430在第二方向x上的尺寸h2为单指栅宽。
示例性的，如图4B所示，部分相邻的两个源极410和漏极420之间设置有栅极430。
或者，示例性的，如图4C所示，任意相邻的两个源极410和漏极420之间均设置有栅极430。
这样一来，能够使半导体结构400中栅极430的数量尽可能的多。在不增大单指栅宽的前提下，提高半导体结构400的总栅宽，进而提高半导体结构400的增益和效率。
栅极430的材料例如可以是高功函数金属。示例的，栅极430材料例如可以是镍(Ni)或者金等。
在一些实施例中，如图4C所示，半导体结构400还包括漏极总线422和栅极总线432。漏极总线422和栅极总线432位于有源区。
其中，漏极总线422和栅极总线432均沿第一方向y延伸。在第一方向y相交的 方向上，漏极总线422与栅极总线432位于源极410相对的两侧。也就是说，漏极总线422与栅极总线432位于源极410沿第二方向x相对的两侧。
漏极总线422与漏极420和漏极焊盘421分别耦接，栅极总线432与栅极430和栅极焊盘431分别耦接。
沿第一方向y，漏极焊盘421和栅极焊盘431分别设置于漏极总线422(或者栅极总线432)相对的两端。漏极焊盘421与漏极总线422耦接，栅极焊盘431与栅极总线432耦接。
漏极总线422沿第二方向x的尺寸小于键合点440沿第二方向x的尺寸，栅极总线432沿第二方向x的尺寸小于键合点440沿第二方向x的尺寸。也就是说，漏极总线422和栅极总线432上均无法设置键合点440以及键合线441。
其中，栅极430、栅极总线432、栅极焊盘431可以在同一次工艺中同步形成。或者理解为，栅极430、栅极总线432、栅极焊盘431可以同层同材料。同理，漏极420、漏极总线422、漏极焊盘421可以在同一次工艺中同步形成。或者理解为，漏极420、漏极总线422、漏极焊盘421可以同层同材料。
漏极总线422可以是一根，即，所有漏极420均与同一根漏极总线422耦接。或者，漏极总线422还可以是多根。其中，可以是多个漏极420分别与多根漏极总线422耦接，还可以是部分漏极420与同一根漏极总线422耦接，另一部分漏极420与另一根漏极总线422耦接。
同样的，栅极总线432可以是一根，即，所有栅极430均与同一根栅极总线432耦接。或者，栅极总线432也可以是多根。其中，可以是多个栅极430分别与多根栅极总线432耦接，还可以是部分栅极430与同一根栅极总线432耦接，另一部分栅极430与另一根栅极总线432耦接。
在一些实施例中，多个源极410、多个漏极420以及多个栅极430划分为一组。
关于漏极总线422和栅极总线432的位置，示例性的，如图4C所示，漏极总线422和栅极总线432位于源极410的同一侧。
漏极总线422和栅极总线432设置于源极410的同一侧面，漏极总线422与源极410、栅极430之间没有交叠，栅极总线432与源极410、漏极420之间也没有交叠。因此，漏极总线422与源极410、栅极430之间以及栅极总线432与源极410、漏极420之间不会产生寄生电容。
漏极总线422与栅极总线432之间可能存在交叠，也可能不存在交叠，因此，漏极总线422与栅极总线432之间可能产生寄生电容，也可能不会产生寄生电容。然而，栅极总线432位于漏极总线422的上方或者下方，如图4C所示，栅极总线432至少与漏极420有交叠，在栅极总线432与漏极420的交叠部分会产生寄生电容。
或者，漏极总线422至少与栅极430有交叠，在漏极总线422与栅极430的交叠部分会产生寄生电容。
或者，示例性的，如图4D所示，漏极总线422位于源极410的侧面，栅极总线432位于源极410和漏极420的上方或者下方，与源极410和漏极420有交叠。漏极总线422与栅极430、栅极总线432之间均没有交叠，因此，漏极总线422与栅极430、栅极总线432之间不会产生寄生电容。
栅极总线432与源极410和漏极420之间存在交叠，这时，栅极总线432与源极410和漏极420的交叠部分会产生寄生电容。
或者，示例性的，如图4E所示，漏极总线422和栅极总线432分别位于源极410(漏极420或者栅极430)相对的两个侧面。
漏极总线422位于源极410的一个侧面，栅极总线432位于源极410的另一个侧面。这时，漏极总线422与源极410、栅极430以及栅极总线432均没有交叠部分。栅极总线432与源极410、漏极420以及漏极总线422均没有交叠部分。因此，漏极总线422与源极410、栅极430以及栅极总线432之间均不存在寄生电容。栅极总线432与源极410、漏极420以及漏极总线422之间均不存在寄生电容。
避免了由于源极410、漏极420、漏极总线422以及栅极总线432之间交叠产生的寄生电容。
图4E所示的漏极总线422和栅极总线432可以设置于源极410的不同侧，可以避免漏极总线422与源极410、漏极420以及栅极430之间产生交叠和栅极总线432与源极410、漏极420以及栅极430之间产生交叠，同时，也避免了漏极总线422和栅极总线432之间产生交叠，进而避免源极410、漏极420、栅极430漏极总线422以及栅极总线432之间相互交叠产生的寄生电容。
本申请实施例对漏极总线422和栅极总线432的位置不做限定，根据需要合理设置即可。
在另一些实施例中，如图5A所示，多个源极410、多个漏极420和多个栅极430可以划分为沿第二方向x并排设置的多组。
例如，多个源极410、多个漏极420和多个栅极430划分为沿第二方向x并排设置的两组。
其中，每组中的源极410和漏极420沿第一方向y交替排布。
在一些实施例中，各组中的源极410位于同一排。在一些实施例中，各组中的漏极420位于同一排。在一些实施例中，各组中的栅极430位于同一排。
在一些实施例中，如图5A所示，位于同一排的源极410之间具有间隙。
这时，如图5A所示，位于同一排的源极410之间具有间隙，位于同一排的漏极420和栅极430之间没有间隙。也就是说，位于同一排的漏极420连接，位于同一排的栅极430连接。这时，两组中的所有漏极420共用一根漏极总线422，两组中的所有栅极430共用一根栅极总线432。
示例性的，如图5A所示，漏极总线422和栅极总线432设置于同一侧，均位于源极410远离间隙的侧面。
漏极总线422和栅极总线432设置于源极410远离间隙的同一侧，使漏极总线422与源极410、栅极430之间没有交叠，栅极总线432与源极410、漏极420之间也没有交叠。因此，漏极总线422与源极410、栅极430之间以及栅极总线432与源极410、漏极420之间不会产生寄生电容。
漏极总线422与栅极总线432之间可能存在交叠，也可能不存在交叠，因此，漏极总线422与栅极总线432之间可能产生寄生电容，也可能不会产生寄生电容。然而，栅极总线432位于漏极总线422的上方或者下方，如图5A所示，栅极总线432至少 与漏极420有交叠，在栅极总线432与漏极420的交叠部分会产生寄生电容。
或者，漏极总线422至少与栅极430有交叠，在漏极总线422与栅极430的交叠部分会产生寄生电容。
或者，示例性的，如图5B所示，漏极总线422和栅极总线432设置于同一侧，均位于源极410靠近间隙的侧面。
栅极总线432位于漏极总线422的上方或者下方，漏极总线422与栅极430、栅极总线432之间有交叠，栅极总线432至少与源极410、漏极420或者漏极总线422之间有交叠。这时，在栅极总线432与源极410、漏极420或者漏极总线422的交叠部分会产生寄生电容。
或者，示例性的，如图5C所示，漏极总线422和栅极总线432设置于不同侧，漏极总线422和栅极总线432分别位于源极410远离间隙相对的两个侧面。
漏极总线422位于源极410远离间隙的一个侧面，栅极总线432位于与源极410远离间隙的侧面相对的另一个侧面。这时，漏极总线422与源极410、栅极430以及栅极总线432均没有交叠部分。栅极总线432与源极410、漏极420以及漏极总线422均没有交叠部分。因此，避免了由于源极410、漏极420、漏极总线422以及栅极总线432之间交叠产生的寄生电容。
或者，示例性的，如图5D所示，漏极总线422和栅极总线432设置于不同侧，漏极总线422位于源极410远离间隙的侧面，栅极总线432位于源极410靠近离间隙的侧面。
漏极总线422位于源极410远离间隙的侧面，与栅极430和栅极总线432之间没有交叠，漏极总线422与栅极430、栅极总线432之间不会产生寄生电容。
栅极总线432位于漏极420的上方或者下方，与漏极420产生交叠部分。这时，栅极总线432与漏极420交叠的部分会产生寄生电容。
或者，示例性的，如图5E所示，漏极总线422和栅极总线432设置于不同侧，栅极总线432位于源极410远离间隙的侧面，漏极总线422位于源极410靠近离间隙的侧面。
栅极总线432位于源极410远离间隙的侧面，与源极410、漏极420和漏极总线422之间没有交叠，栅极总线432与源极410、漏极420和漏极总线422之间不会产生寄生电容。
漏极总线422位于栅极430的上方或者下方，与栅极430产生交叠部分。这时，漏极总线422与栅极430交叠的部分会产生寄生电容。
在又一些实施例中，如图6A所示，位于同一排的漏极420之间具有间隙。
如图6A所示，仅位于同一排的漏极420之间具有间隙，位于同一排的源极410和栅极430之间均没有间隙。也就是说，位于同一排的源极410连接，位于同一排的栅极430连接。这时，每一组中所有漏极420共用一根漏极总线422，两组中的所有栅极430共用一根栅极总线432。
这时，漏极总线422和栅极总线432可以设置于漏极420的同一侧，也可以设置于漏极420的不同侧。
示例性的，如图6A所示，两组中的漏极总线422分别位于漏极420远离间隙的 相对的两个侧面，栅极总线432位于漏极420远离间隙的侧面，与其中一根漏极总线422设置于同一侧。
在漏极420远离间隙的其中一个侧面，设置有与栅极总线432不同侧的其中一条漏极总线422，该条漏极总线422与栅极430和栅极总线432之间均没有交叠，因此，该条漏极总线422与栅极430和栅极总线432之间不会产生寄生电容。
在漏极420远离间隙的另一个侧面，设置有栅极总线432和与栅极总线432同一侧的另一条漏极总线422，这时，漏极总线422与栅极430之间没有交叠，栅极总线432与源极410、漏极420之间也没有交叠。因此，漏极总线422与栅极430之间以及栅极总线432与源极410、漏极420之间不会产生寄生电容。
位于同一侧的漏极总线422与栅极总线432之间可能存在交叠，也可能不存在交叠，因此，漏极总线422与栅极总线432之间可能产生寄生电容，也可能不会产生寄生电容。然而，栅极总线432位于漏极总线422的上方或者下方，如图6A所示，栅极总线432至少与漏极420有交叠，在栅极总线432与漏极420的交叠部分会产生寄生电容。
或者，漏极总线422至少与栅极430有交叠，在漏极总线422与栅极430的交叠部分会产生寄生电容。
或者，示例性的，如图6B所示，漏极总线422和栅极总线432可以设置于漏极420的不同侧，漏极总线422位于漏极420远离间隙的两个相对的侧面，栅极总线432位于漏极420靠近离间隙的侧面，即两组漏极420之间的区域。
两条漏极总线422与栅极430、栅极总线432之间均没有交叠，因此，两条漏极总线422与栅极430、栅极总线432之间不会产生寄生电容。
栅极总线432与源极410之间存在交叠，这时，栅极总线432与源极410的交叠部分会产生寄生电容。
或者，示例性的，如图6C所示，位于同一排的漏极420之间和位于同一排的源极410之间均具有间隙，位于同一排的栅极430之间没有间隙。也就是说，位于同一排的栅极430连接。这时，每一组中所有漏极420共用一根漏极总线422，两组中的所有栅极430共用一根栅极总线432。
这时，漏极总线422和栅极总线432也可以设置于漏极420的同一侧，或者，设置于漏极420的不同侧。
示例性的，如图6C所示，漏极总线422和栅极总线432可以设置于漏极420的同一侧，漏极总线422和栅极总线432均位于漏极420(或者源极410)远离间隙的侧面。
图6C与图6A的漏极总线422和栅极总线432设置位置相同，区别在于图6C中位于同一排的源极410之间具有间隙。因此，与栅极总线432设置于不同侧的漏极总线422，与栅极430和栅极总线432之间不会产生寄生电容。
与栅极总线432设置于同一侧的漏极总线422，与栅极430之间不会产生寄生电容。
栅极总线432与源极410、漏极420之间不会产生寄生电容。
位于同一侧的漏极总线422与栅极总线432之间可能产生寄生电容，也可能不会 产生寄生电容。
栅极总线432与漏极420的交叠部分会产生寄生电容。或者，漏极总线422与栅极430的交叠部分会产生寄生电容。
或者，示例性的，如图6D所示，漏极总线422和栅极总线432可以设置于漏极420的不同侧，漏极总线422位于漏极420(或者源极410)远离间隙的侧面，栅极总线432位于漏极420(或者源极410)靠近离间隙的侧面。
图6D与图6B的漏极总线422和栅极总线432设置位置相同，区别在于图6D中位于同一排的源极410之间具有间隙。因此，两条漏极总线422与栅极430、栅极总线432之间不会产生寄生电容。
栅极总线432与源极410之间没有交叠，栅极总线432与源极410不会产生寄生电容。
如图6D所示的漏极总线422和栅极总线432可以设置于漏极420的不同侧，可以避免漏极总线422与源极410、漏极420以及栅极430之间产生交叠和栅极总线432与源极410、漏极420以及栅极430之间产生交叠，同时，也避免了漏极总线422和栅极总线432之间产生交叠，进而避免源极410、漏极420、栅极430漏极总线422以及栅极总线432之间相互交叠产生的寄生电容。
在又一些实施例中，如图7A所示，位于同一排的栅极430之间具有间隙。
示例性的，如图7A所示，仅位于同一排的栅极430之间具有间隙，位于同一排的源极410和漏极420之间均没有间隙。也就是说，位于同一排的源极410连接，位于同一排的源极410连接。这时，两组中所有漏极420共用一根漏极总线422，每一组中的所有栅极430共用一根栅极总线432。
这时，漏极总线422和栅极总线432可以设置于栅极430的同一侧，也可以设置于栅极430的不同侧。
示例性的，如图7A所示，两组中的栅极总线432分别位于栅极430远离间隙的相对的两个侧面，漏极总线422位于栅极430远离间隙的侧面，与其中一根栅极总线432设置于同一侧。
在栅极430远离间隙的其中一个侧面，设置有与漏极总线422不同侧的其中一条栅极总线432，该条栅极总线432与源极410、漏极420以及漏极总线422之间均没有交叠，因此，该条栅极总线432与源极410、漏极420以及漏极总线422之间不会产生寄生电容。
在栅极430远离间隙的另一个侧面，设置有漏极总线422和与漏极总线422同一侧的另一条栅极总线432，这时，漏极总线422与栅极430之间没有交叠，栅极总线432与源极410、漏极420之间也没有交叠。因此，漏极总线422与栅极430之间以及栅极总线432与源极410、漏极420之间不会产生寄生电容。
位于同一侧的漏极总线422与栅极总线432之间可能存在交叠，也可能不存在交叠，因此，漏极总线422与栅极总线432之间可能产生寄生电容，也可能不会产生寄生电容。然而，栅极总线432位于漏极总线422的上方或者下方，如图7A所示，栅极总线432至少与漏极420有交叠，在栅极总线432与漏极420的交叠部分会产生寄生电容。
或者，漏极总线422至少与栅极430有交叠，在漏极总线422与栅极430的交叠部分会产生寄生电容。
或者，示例性的，如图7B所示，位于同一排的漏极420之间和位于同一排的栅极430之间均具有间隙，位于同一排的源极410之间没有间隙。也就是说，位于同一排的源极410连接。这时，每一组中的所有漏极420共用同一根漏极总线422，每一组中的所有栅极430共用一根栅极总线432。
这时，如图7B所示，漏极总线422和栅极总线432也可以设置于栅极430的同一侧，漏极总线422和栅极总线432均位于栅极430(或者漏极420)远离间隙的侧面。
每组的漏极总线422与栅极总线432均位于栅极430远离间隙的侧面。
栅极总线432与源极410之间不存在交叠，栅极总线432与源极410之间不会产生寄生电容。
位于同一侧的漏极总线422与栅极总线432之间可能存在交叠，也可能不存在交叠，因此，漏极总线422与栅极总线432之间可能产生寄生电容，也可能不会产生寄生电容。然而，栅极总线432位于漏极总线422的上方或者下方，如图7B所示，栅极总线432至少与漏极420有交叠，在栅极总线432与漏极420的交叠部分会产生寄生电容。
或者，漏极总线422至少与栅极430有交叠，在漏极总线422与栅极430的交叠部分会产生寄生电容。
或者，示例性的，如图7C所示，位于同一排源极410的之间和位于同一排的栅极430之间均具有间隙，位于同一排的漏极420之间没有间隙。也就是说，位于同一排的漏极420连接。这时，两组中所有的漏极420共用一根漏极总线422，每一组中的所有栅极430共用一根栅极总线432。
图7C与图7A的漏极总线422和栅极总线432设置位置相同，区别在于图7C中位于同一排的源极410之间具有间隙。
因此，与漏极总线422设置于不同侧的栅极总线432，与源极410、漏极420以及漏极总线422之间不会产生寄生电容。
与漏极总线422设置于同一侧的栅极总线432，与源极410、漏极420之间不会产生寄生电容。
漏极总线422与栅极430之间不会产生寄生电容。
位于同一侧的漏极总线422与栅极总线432之间可能产生寄生电容，也可能不会产生寄生电容。
栅极总线432与漏极420的交叠部分会产生寄生电容。或者，漏极总线422与栅极430的交叠部分会产生寄生电容。
或者，示例性的，如图7D所示，位于同一排的源极410、位于同一排的漏极420之间和位于同一排的栅极430之间均具有间隙。这时，每一组中的所有漏极420共用一根漏极总线422，每一组中的所有栅极430共用一根栅极总线432。
这时，漏极总线422和栅极总线432可以设置于栅极430的同一侧，也可以设置于栅极430的不同侧。
示例性的，如图7D所示，漏极总线422和栅极总线432可以设置于栅极430的同一侧，漏极总线422和栅极总线432均位于栅极430(源极410或者漏极420)远离间隙的侧面。
图7D与图7B的漏极总线422和栅极总线432设置位置相同，区别在于图7D中位于同一排的源极410之间具有间隙。
因此，栅极总线432与源极410之间不会产生寄生电容。
位于同一侧的漏极总线422与栅极总线432之间能产生寄生电容，也可能不会产生寄生电容。
栅极总线432与漏极420的交叠部分会产生寄生电容。或者，漏极总线422与栅极430的交叠部分会产生寄生电容。
或者，示例性的，如图7E所示，漏极总线422和栅极总线432可以设置于栅极430的不同侧，漏极总线422位于栅极430(源极410或者漏极420)靠近间隙的侧面，栅极总线432位于栅极430(源极410或者漏极420)远离间隙的两个相对的侧面。
漏极总线422与栅极430、栅极总线432之间均没有交叠，因此，漏极总线422与栅极430、栅极总线432之间不会产生寄生电容。
两条栅极总线432与源极410、漏极420以及漏极总线422之间均不存在交叠，因此，两条栅极总线432与源极410、漏极420以及漏极总线422之间不会产生寄生电容。
如图7E所示的漏极总线422和栅极总线432设置于栅极430的不同侧，可以避免漏极总线422与源极410、漏极420以及栅极430之间产生交叠和栅极总线432与源极410、漏极420以及栅极430之间产生交叠，同时，也避免了漏极总线422和栅极总线432之间产生交叠，进而避免源极410、漏极420、栅极430漏极总线422以及栅极总线432之间相互交叠产生的寄生电容。
关于背孔412的结构，如图7E所示，源极410的下方设置有至少一个背孔412。源极410通过背孔412接地。
示例性的，源极410下方设置有一个背孔412。
当源极410在第二方向x的尺寸与背孔412在第二方向x上的尺寸接近时，源极410下方仅设置一个背孔412。
或者，示例性的，源极410下方设置有至少两个背孔412。
其中，背孔412可以是圆形，也可以是方形，
背孔412只需设置在源极410的下方即可。背孔412在第一方向y上的尺寸不超过源极410在第一方向y上的尺寸，背孔412在第二方向x上的尺寸不超过源极410在第二方向x上的尺寸。
本申请实施例对背孔412的数量和形状不做限定，根据需要合理设计即可。
此处释明的是，多个源极410的下方设置背孔412的数量、形状以及大小可以相同，也可以不同。
如图8(沿图7E中A1-A2向的剖视图)所示，背孔412从衬底401贯穿至势垒层403，源极410靠近衬底401的底面作为背孔412的孔底。
其中，若源极410下方为有源区，即背孔412设置在有源区。若源极410下方为 无源区，即背孔412设置在无源区。
本申请实施例对此不做限定，只需保证背孔设置于源极410下方即可。
本申请实施例提供的半导体结构400还包括背面导电层405。如图8所示，背面导电层405覆盖衬底401的背面和背孔412。
其中，源极410与背面导电层405接触。通过背面导电层405实现源极410接地。
背面导电层405可以为单层结构，也可以为多层结构。本申请实施例对此不做限定。
示例性的，背面导电层405包括依次层叠设置的第一导电层405a和第二导电层405b。第一导电层405a与源极410直接接触，第二导电层405b设置于第一导电层405a远离衬底401一侧，第一导电层405a的黏附性大于第二导电层405b的黏附性。
背孔412位于源极410下方，通过背面导电层405实现将半导体结构400的源极410接地，避免源极焊盘411的存在带来额外的寄生电容和寄生电感。
本申请实施例中，通过设置背孔412和覆盖背孔412的背面导电层405，可以直接实现源极410接地，无需设置源极焊盘411，避免了在相邻的漏极焊盘421之间或者相邻的栅极焊盘431之间设置空气桥或者介质桥带来工艺上的问题。同时，源极410直接接触背面导电层405，使信号传输至源极410的路径更短，进而减小了半导体结构400的寄生电感，提升了半导体结构400的频率特性。
另外，也无需设置连接源极410与源极焊盘411的源极总线，避免源极总线与漏极总线422或者栅极总线432交叠而产生的寄生电容。
这样一来，背孔412无需设置在源极焊盘411的下方，减小了信号从源极焊盘411传输至源极410的路径，进而减小了半导体结构400的寄生电感。
如图8所示，半导体结构400包括衬底401以及衬底401上的堆叠半导体层。堆叠半导体层包括沟道层402和势垒层403。
衬底401例如可以是碳化硅(SiC)衬底、硅(Si)衬底、蓝宝石衬底或者金刚石衬底等，本申请实施例对衬底401的材料不做限定。
在一些实施例中，衬底401上的堆叠半导体层包括依次层叠设置的成核层、渐变缓冲层、沟道层402、插入层、势垒层403以及帽层。沟道层402和势垒层403形成异质结，沟道层402的上方产生二维电子气(two-dimensional electron gas，2DEG)404。
具体的，成核层设置在衬底401的表面上。成核层的材料可以包括GaN(氮化镓)、AlGaN(铝镓氮)、AlN(氮化铝)中一种或多种。成核层的作用是提高外延质量，利于上层外延的生长。形成成核层的方法，例如可以通过金属有机化合物化学气相沉淀(metal-organic chemical vapor deposition，MOCVD)生长法或分子束外延(molecular beam epitaxy，MBE)生长法等。
渐变缓冲层设置于成核层远离衬底401一侧。渐变缓冲层的作用是，渐变缓冲层和沟道层402的禁带宽度不同，可以使得势垒层403与沟道层402形成的异质结的势阱深度更深，从而提高二维电子气404的限制。另外，缓冲层一般厚度较厚，是半导体结构400承受电压的主要结构。
形成渐变缓冲层的方法，例如可以采用MOCVD工艺外延生长Al(铝)组分逐渐降低的AlGaN渐变层。
示例的，通过MOCVD工艺，在成核层远离衬底401一侧依次形成Al 0.8Ga 0.2N层、Al 0.5Ga 0.5N层、Al 0.2Ga 0.8N层，以形成渐变缓冲层。
其中，为了减少电子的散射带来的迁移率降低，渐变缓冲层一般采用不掺杂的结构。
沟道层402设置于渐变缓冲层远离衬底401一侧。沟道层402的材料可以包括GaN、AlGaN、InAlN(铟氮化铝)、AlN、ScAlN(钪氮化铝)中一种或多种。形成沟道层402的方法，例如可以通过MOCVD生长法或MBE生长法等。
插入层设置设置于沟道层402远离衬底401一侧，用于提高二维电子气404的迁移率。形成插入层的方法，例如可以采用MOCVD生长法或MBE生长法等。
势垒层403设置于插入层远离衬底401一侧。势垒层403的材料例如可以包括GaN、AlGaN、InAlN、AlN、ScAlN中一种或多种。形成势垒层403的方法，例如可以通过MOCVD生长法或MBE生长法等。
其中，沟道层402和势垒层403的材料不相同，沟道层402和势垒层403构成异质结构。示例的，沟道层402的材料包括GaN，势垒层403的材料包括AlGaN。
其中，势垒层403往往是不掺杂的，利用其与后续形成的栅极430(通常为金属材料)的功函数差，在栅极430下方形成具有单向通流能力的势垒层403，在保障了栅极430控制沟道层402的能力的同时还能有效降低栅极430的漏电问题。
帽层设置于势垒层403远离衬底401一侧。帽层的材料，例如，可以为GaN或者Si 3N 4(氮化硅)。形成帽层的方法，例如可以采用MOCVD生长法或MBE生长法形成帽层。可以理解的是，帽层的设置应不影响源极410和漏极420与势垒层403的欧姆接触，可以通过掺杂或对帽层进行图案化(露出势垒层403)，来达到上述效果。
帽层的厚度太小，对势垒层403起不到保护作用。帽层厚度太大会增大半导体结构400的厚度。
本申请实施例并不限定堆叠半导体层，只要在衬底401上至少形成包括沟道层402和势垒层403的异质结构即可。
以下为了便于说明，如图8所示，在后续过程中，仅以衬底401上形成的堆叠半导体层包括沟道层402和势垒层403为例进行示意。
关于源极410和漏极420的结构，如图8所示，源极410和漏极420设置于势垒层403上。
例如，堆叠半导体层中，位于最上层的为帽层，则在帽层上形成源极410和漏极420。或者，例如，堆叠半导体层中，位于最上层的为势垒层403，则在势垒层403上形成源极410和漏极420。无论哪种结构，保证源极410和漏极420与势垒层403形成欧姆接触即可。
如图8所示，源极410和漏极420设置在堆叠半导体层(例如势垒层403)的表面上，源极410和漏极420为最靠近堆叠半导体层(例如势垒层403)的导电结构。
或者理解为，源极410和漏极420为设置在堆叠半导体层(例如势垒层403)上的第一层导电结构，二者之间未设置其他导电结构。
如图8所示，栅极430位于源极410和漏极420之间。
栅极430设置于势垒层403上，与势垒层403形成肖特基接触。
此处释明的是，漏极总线422和栅极总线432设置于势垒层403上。漏极总线422可以与漏极420同时形成，栅极总线432可以与栅极430同时形成。
在一些实施例中，如图8所示，半导体结构400还包括加厚源极510和加厚漏极520。
加厚源极510设置在源极410上，与源极410接触连接。加厚漏极520设置在漏极420上，与漏极420接触连接。
本申请实施例不对加厚源极510和加厚漏极520的材料进行限定，可以与源极410和漏极420的材料相同，也可以不同。
加厚源极510和加厚漏极520相当于增加了源极410和漏极420的厚度，减小了源极410和漏极420的电阻，从而提高半导体结构400的电流导通能力。但值得注意的是，加厚源极510和加厚漏极520的大小不要求与源极410和漏极420大小相同，可以大于也可以小于源极410和漏极420的大小，都可以起到提高电流导通能力的作用。
在一些实施例中，如图8所示，半导体结构400还包括场板(field plate，FP)406。
其中，场板406的材料可以为任意导电材料。场板406设置于栅极430远离衬底401一侧，位于栅极430与漏极420之间的区域上方，场板406在衬底401上的正投影与栅极430在衬底401上的正投影交叠。
场板406可以为悬浮状态，不加载任何信号。场板406也可以与源极410接触连接，场板406还可以与栅极430接触连接。
由于栅极430位置处容易出现电场尖峰，通过在栅极430上方设置场板406，可以调制半导体结构400内的电场分布，使电场分布均匀，避免出现电场尖峰。
如图8所示，半导体结构400还包括第一介质层407、第二介质层408以及第三介质层(图8未示出)。
第一介质层407位于栅极430与堆叠半导体层(例如势垒层403)之间。
第二介质层408位于栅极430与场板406之间。
第三介质层覆盖半导体结构400的表面，第三介质层可以包括钝化层(包括介质材料)或者防水层(包括防水材料)，用于对半导体结构400进行保护。
在一些实施例中，如图9所示，半导体结构400包括沿第二方向x排布的多个半导体组40。多个源极410、多个漏极420和多个栅极430作为一个半导体组40。
根据上述实施例划分方式的不同，每个半导体组40里可以包括一组源极410、漏极420和栅极430，也可以包括多组源极410、漏极420和栅极430。半导体结构400中包括的多个半导体组40的结构可以相同，也可以不同。
其中，多个半导体组40中的栅极焊盘431耦接，多个半导体组40中的漏极焊盘421耦接，多个半导体组40中的背面导电层405耦接。
示例性的，如图9所示，多个半导体组40中的漏极焊盘421通过第一电阻423耦接，多个半导体组40中的栅极焊盘431通过第二电阻433耦接。
其中，通过第一电阻423实现多个漏极焊盘421耦接，或者通过第二电阻433实现多个栅极焊盘431耦接，可以提高半导体结构400的稳定性。
或者，示例性的，多个半导体组40中的栅极焊盘431为一体结构，多个半导体组 40中的漏极焊盘421为一体结构。
基于上述对半导体结构400的描述，以下结合图10对上述半导体结构400的工作方法进行说明。
如图10所示，本申请实施例还提供一种半导体结构400的工作方法，包括：
S1、开启信号通过漏极焊盘421输入至漏极420。
开启信号从封装结构32的管脚1输入，通过与管脚1连接的键合线441输入至漏极焊盘421，再由漏极焊盘421输入至漏极420。具体的，开启信号的输入使栅极电压大于阈值电压，开启栅极沟道。
S2、工作信号通过漏极焊盘421输入至漏极420。
其中，步骤S1中的开启信号与步骤S2中的工作信号可以为同一信号输入，也可以由两个不同的信号分时输入，本申请实施例对比不做限定。
工作信号从封装结构32的管脚1输入，通过与管脚1连接的键合线441输入至漏极焊盘421，再由漏极焊盘421输入至漏极420。
S3、初始信号通过栅极焊盘431输入至栅极430，在工作信号的控制下，对初始信号进行放大后从漏极420输出至漏极焊盘421。
具体的，在开启信号的控制下，栅极通道开启，将初始信号从封装结构32的管脚2输入，通过与管脚2连接的键合线441输入至栅极焊盘431，再由栅极焊盘431输入至栅极430。
在工作信号的控制下，对初始信号进行放大，并将放大后的初始信号从漏极420输出至漏极焊盘421，再由与漏极焊盘421连接的键合线441输出至封装结构32的管脚1。
本申请实施例提供的半导体结构400，包括层叠设置的衬底401、沟道层402和势垒层403。半导体结构400还包括设置在势垒层403上的多个源极410、多个漏极420、多个栅极430、漏极总线422和栅极总线432、从衬底401贯穿至势垒层403的多个背孔412以及覆盖衬底401的背面和背孔412的背面导电层405。其中，漏极总线422与漏极420耦接，栅极总线432与栅极430耦接。源极410的下方设置有至少一个背孔412，源极410与背面导电层405接触。本申请实施例中，源极410和漏极420沿第一方向y交替排布，栅极430位于源极410和漏极420之间，与漏极420耦接的漏极总线422和与栅极430耦接的栅极总线432均沿第一方向y延伸。与现有技术相比，在固定长度的封装结构32内，通过改变栅极430的延伸方向，增加了栅极430的数量，实现在不增加单个栅极430的尺寸即单指栅宽的前提下，增加了半导体结构400的总栅宽，进而提高了半导体结构400的输出功率，提高了半导体结构400的增益和效率。
同时，背孔412设置在源极410的下方，背面导电层405通过背孔412与源极410直接接触，实现源极410接地，降低了工艺的复杂度。又因为源极410直接接触背面导电层405，使信号传输至源极410的路径更短，减小了半导体结构400的寄生电感。另外，在源极410的下方设置背孔412与背面导电层405，也就无需再设置源极焊盘411以及连接源极410与源极焊盘411的源极总线，能够避免源极总线与漏极总线422或者栅极总线432之间交叠而产生的寄生电容，进而提高了半导体结构400的可靠性。 无需设置源极焊盘411，因此，不存在由于限制漏极焊盘421或者栅极焊盘431之间连接引线的数量而影响多个半导体组40之间匹配性的问题。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种半导体结构，其特征在于，包括多个半导体组，每个所述半导体组包括：
    多个源极、多个漏极和多个栅极；
    漏极焊盘和栅极焊盘；所述多个漏极与所述漏极焊盘耦接，所述多个栅极与所述栅极焊盘耦接；所述漏极焊盘和所述栅极焊盘上均设置有多个键合点；
    其中，所述多个源极、所述多个漏极和所述多个栅极均位于所述漏极焊盘和所述栅极焊盘之间，在所述第一方向上，所述源极、所述漏极和所述栅极交替排布；所述栅极位于所述源极和所述漏极之间；所述漏极焊盘和所述栅极焊盘均沿第二方向延伸，所述第一方向为从所述漏极焊盘到所述栅极焊盘的方向；所述第一方向与所述第二方向相交；
    多个背孔，所述多个源极中的每个源极的下方设置有至少一个所述背孔；所述源极通过所述背孔接地。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括漏极总线和栅极总线；
    所述漏极总线与所述多个漏极和所述漏极焊盘分别耦接；所述栅极焊盘与所述多个栅极和所述栅极焊盘分别耦接；所述漏极总线和所述栅极总线均沿所述第一方向延伸；所述漏极总线和所述栅极总线位于所述漏极沿所述第二方向相对的两侧。
  3. 根据权利要求2所述的半导体结构，其特征在于，所述漏极总线沿所述第二方向的尺寸小于所述键合点沿所述第二方向的尺寸；所述栅极总线的沿所述第二方向的尺寸小于所述键合点的沿所述第二方向的尺寸。
  4. 根据权利要求1-3任一项所述的半导体结构，其特征在于，所述多个源极、所述多个漏极和所述多个栅极划分为沿所述第二方向并排设置的多组，每组中的所述源极和所述漏极沿所述第一方向交替排布。
  5. 根据权利要求1-4任一项所述的半导体结构，其特征在于，位于同一排的所述源极之间具有间隙。
  6. 根据权利要求1-5任一项所述的半导体结构，其特征在于，位于同一排的所述栅极之间具有间隙。
  7. 根据权利要求1-6任一项所述的半导体结构，其特征在于，位于同一排的所述漏极之间具有间隙。
  8. 根据权利要求7所述的半导体结构，其特征在于，所述漏极总线和所述栅极总线一者位于所述漏极远离所述间隙的侧面，另一者位于所述漏极靠近所述间隙的侧面。
  9. 根据权利要求8所述的半导体结构，其特征在于，所述多个源极、所述多个漏极和所述多个栅极划分为沿所述第二方向并排设置的两组；
    每组中的所述漏极与同一条所述漏极总线耦接，每条所述漏极总线位于所述漏极远离所述间隙一侧；所述多个栅极与同一条所述栅极总线耦接，所述栅极总线位于所述漏极靠近所述间隙一侧。
  10. 根据权利要求8所述的半导体结构，其特征在于，所述多个源极、所述多个漏极和所述多个栅极划分为沿所述第二方向并排设置的两组；
    每组中的所述栅极与同一条所述栅极总线耦接，每条所述栅极总线位于所述漏极 远离所述间隙一侧；所述多个漏极与同一条所述漏极总线耦接，所述漏极总线位于所述漏极靠近所述间隙一侧。
  11. 根据权利要求1-10任一项所述的半导体结构，其特征在于，所述源极下方设置有至少两个所述背孔。
  12. 根据权利要求1-11任一项所述的半导体结构，其特征在于，多个所述半导体组沿所述第二方向排布；所述键合点沿所述第二方向在所述漏极焊盘上排布；所述键合点沿所述第二方向在所述栅极焊盘上排布。
  13. 根据权利要求12所述的半导体结构，其特征在于，多个所述半导体组中的栅极焊盘耦接，多个所述半导体组中的漏极焊盘耦接。
  14. 根据权利要求1-13任一项所述的半导体结构，其特征在于，所述半导体结构还包括：依次层叠设置的衬底、沟道层以及势垒层；
    所述源极、所述漏极以及所述栅极均设置于所述势垒层上。
  15. 根据权利要求14所述的半导体结构，其特征在于，所述背孔从所述衬底贯穿至所述势垒层；
    所述半导体结构还包括背面导电层；所述背面导电层覆盖所述衬底的背面和所述背孔；所述源极与所述背面导电层接触。
  16. 一种半导体结构的工作方法，其特征在于，所述半导体结构包括多个半导体组，每个所述半导体组包括：多个源极、多个漏极和多个栅极；漏极焊盘和栅极焊盘；所述多个漏极与所述漏极焊盘耦接，所述多个栅极与所述栅极焊盘耦接；所述漏极焊盘和所述栅极焊盘上均设置有多个键合点；其中，所述多个源极、所述多个漏极和所述多个栅极均位于所述漏极焊盘和所述栅极焊盘之间，在所述第一方向上，所述源极、所述漏极以及所述栅极交替排布；所述栅极位于所述源极和所述漏极之间；所述漏极焊盘和所述栅极焊盘均沿第二方向延伸，所述第一方向为从所述漏极焊盘到所述栅极焊盘的方向所述第一方向与所述第二方向相交；多个背孔，所述多个源极中的每个源极的下方设置有至少一个所述背孔；所述源极通过所述背孔接地；
    所述半导体结构的工作方法包括：
    工作信号通过所述漏极焊盘输入至所述漏极；
    初始信号通过所述栅极焊盘输入至所述栅极，在所述工作信号的控制下，对所述初始信号进行放大后从所述漏极输出至所述漏极焊盘。
  17. 一种功率放大电路，其特征在于，包括封装结构以及如权利要求1-15任一项所述的半导体结构，所述半导体结构封装于所述封装结构内部。
  18. 一种电子设备，其特征在于，包括功率放大器及天线，所述功率放大器用于将射频信号放大后输出至所述天线向外辐射，所述功率放大器包括如权利要求17所述的功率放大电路。
PCT/CN2022/078332 2022-02-28 2022-02-28 半导体结构及其工作方法、功率放大电路、电子设备 WO2023159578A1 (zh)

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CN108807513A (zh) * 2017-07-04 2018-11-13 苏州能讯高能半导体有限公司 半导体器件及其制造方法
CN109671774A (zh) * 2017-10-16 2019-04-23 苏州能讯高能半导体有限公司 半导体器件及其制造方法
CN110970498A (zh) * 2018-09-29 2020-04-07 苏州能讯高能半导体有限公司 一种半导体器件及其制备方法
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CN108807513A (zh) * 2017-07-04 2018-11-13 苏州能讯高能半导体有限公司 半导体器件及其制造方法
CN109671774A (zh) * 2017-10-16 2019-04-23 苏州能讯高能半导体有限公司 半导体器件及其制造方法
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