JP2014160801A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 239000011229 interlayer Substances 0.000 claims abstract description 55
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- 239000010410 layer Substances 0.000 claims abstract description 39
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims description 32
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- A—HUMAN NECESSITIES
- A42—HEADWEAR
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- A—HUMAN NECESSITIES
- A42—HEADWEAR
- A42B—HATS; HEAD COVERINGS
- A42B1/00—Hats; Caps; Hoods
- A42B1/018—Hats; Caps; Hoods with means for protecting the eyes, ears or nape, e.g. sun or rain shields; with air-inflated pads or removable linings
- A42B1/0186—Hats; Caps; Hoods with means for protecting the eyes, ears or nape, e.g. sun or rain shields; with air-inflated pads or removable linings with means for protecting the ears or nape
- A42B1/0188—Protection for the ears, e.g. removable ear muffs
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- A—HUMAN NECESSITIES
- A42—HEADWEAR
- A42B—HATS; HEAD COVERINGS
- A42B1/00—Hats; Caps; Hoods
- A42B1/02—Hats; Stiff caps
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- A—HUMAN NECESSITIES
- A42—HEADWEAR
- A42B—HATS; HEAD COVERINGS
- A42B3/00—Helmets; Helmet covers ; Other protective head coverings
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- A42B3/06—Impact-absorbing shells, e.g. of crash helmets
- A42B3/062—Impact-absorbing shells, e.g. of crash helmets with reinforcing means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
【解決手段】ヒューズ開口部からの水分侵入を防ぐため、酸化膜からなる層間絶縁膜をプラズマTEOS酸化膜層の一部を残すようにエッチングし、その後パッシベーション窒化膜を堆積、パターニングした後、部分的にパッシベーション窒化膜を除去することで、ヒューズ開口部の層間絶縁膜の側壁および側底面をパッシベーション窒化膜で覆う構造とする。これにより積層されている層間絶縁膜の界面やSOG層からの水分浸入を抑えることが可能となり、水分によるIC特性の劣化を防ぐことが可能となる。
【選択図】図2
Description
半導体基板と、
前記半導体基板の表面に設けられたフィールド絶縁膜と、
前記フィールド絶縁膜の上に配置された抵抗体及びヒューズと、
前記ヒューズの上に設けられた第一の層間絶縁膜と、
前記第一の層間絶縁膜の上に設けられた第二の層間絶縁膜と、
前記第二の層間絶縁膜の上に設けられた、SOG層を間に有する第三の層間絶縁膜と、
前記第三の層間絶縁膜上に形成されたパッシベーション酸化膜と、
前記ヒューズの上に、前記パッシベーション酸化膜から前記第二の層間絶縁膜の途中まで、その間の膜を除去することで設けられたヒューズ開口部と、
前記パッシベーション酸化膜の上と前記ヒューズ開口部の側面および側底面を覆うパッシベーション窒化膜と、を有し、
前記ヒューズ開口部の底面において前記第二の層間絶縁膜が前記パッシベーション窒化膜から露出するように、前記パッシベーション窒化膜が除去されていることを特徴とする半導体装置とした。
図2は図1の切断線A−Aにおける半導体装置の模式断面図であり、図3は図1の切断線B−Bにおける半導体装置の模式断面図である。P型シリコン半導体基板101上にPMOS領域に形成されたN型ウエル拡散層102と、特に記載はしないがNMOS領域にP型ウエル拡散層を形成し、LOCOS法により形成された酸化膜のフィールド絶縁膜103を例えば4000〜8000Å程形成している。
102 N型ウエル拡散層
103、203 フィールド絶縁膜
104 ゲート絶縁膜
105 ゲート電極
106 ヒューズ
107 高抵抗抵抗体
108 P型高濃度不純物領域
109 抵抗体の低濃度領域
110 抵抗体の高濃度領域
111、211 第一の層間絶縁膜
112 接続孔
113 第一の金属配線
114、214 第二の層間絶縁膜
115 第二の金属配線
116、216 第三の層間絶縁膜
117、217 SOG層
118 第三の金属配線
119、219 パッシベーション酸化膜
120、220 パッシベーション窒化膜
121、221 ガードリング
122、222 ヒューズ開口部
123 パッシベーション窒化膜の開口部
Claims (6)
- 半導体基板と、
前記半導体基板の表面に設けられたフィールド絶縁膜と、
前記フィールド絶縁膜の上に配置された抵抗体及びヒューズと、
前記ヒューズの上に設けられた第一の層間絶縁膜と、
前記第一の層間絶縁膜の上に設けられた第二の層間絶縁膜と、
前記第二の層間絶縁膜の上に設けられた、SOG層を間に有する第三の層間絶縁膜と、
前記第三の層間絶縁膜上に形成されたパッシベーション酸化膜と、
前記ヒューズの上に、前記パッシベーション酸化膜から前記第二の層間絶縁膜の途中まで、その間の膜を除去することで設けられたヒューズ開口部と、
前記パッシベーション酸化膜の上と前記ヒューズ開口部の側面および側底面を覆うパッシベーション窒化膜と、
を有し、
前記ヒューズ開口部の底面において前記第二の層間絶縁膜が前記パッシベーション窒化膜から露出するように、前記パッシベーション窒化膜が除去されていて、前記パッシベーション窒化膜は前記ヒューズ開口部とは異なる形状の開口部を有することを特徴とする半導体装置。 - 前記ヒューズは第一の多結晶シリコンにより形成されていることを特徴とする、請求項1記載の半導体装置。
- 前記抵抗体は前記第一の多結晶シリコンとはことなる第二の多結晶シリコンから形成されていることを特徴とする、請求項2記載の半導体装置。
- 前記ヒューズ開口部の周囲を取り囲む、金属配線材料からなるガードリングをさらに有することを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 前記ヒューズは複数配置されており、前記パッシベーション窒化膜が有する前記開口部は、それぞれの前記ヒューズにおいて独立した開口部となっていることを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置。
- 前記第一の層間絶縁膜がBPSGおよびNSG層で形成され、前記第二の層間絶縁膜がプラズマTEOSシリコン酸化膜で形成され、前記第三の層間絶縁膜がプラズマTEOSシリコン酸化膜とSOGとプラズマTEOSシリコン酸化膜で構成されていることを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置。
Priority Applications (5)
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JP2013245290A JP6215020B2 (ja) | 2013-01-25 | 2013-11-27 | 半導体装置 |
TW103101602A TWI618221B (zh) | 2013-01-25 | 2014-01-16 | 半導體裝置 |
KR1020140008320A KR102156820B1 (ko) | 2013-01-25 | 2014-01-23 | 반도체 장치 |
US14/161,894 US9570537B2 (en) | 2013-01-25 | 2014-01-23 | Semiconductor device |
CN201410033375.8A CN103972211B (zh) | 2013-01-25 | 2014-01-24 | 半导体装置 |
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JP2013012386 | 2013-01-25 | ||
JP2013012386 | 2013-01-25 | ||
JP2013245290A JP6215020B2 (ja) | 2013-01-25 | 2013-11-27 | 半導体装置 |
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JP2014160801A true JP2014160801A (ja) | 2014-09-04 |
JP6215020B2 JP6215020B2 (ja) | 2017-10-18 |
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JP (1) | JP6215020B2 (ja) |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2016122771A (ja) * | 2014-12-25 | 2016-07-07 | ローム株式会社 | チップ部品 |
JP2016213293A (ja) * | 2015-05-01 | 2016-12-15 | エスアイアイ・セミコンダクタ株式会社 | 半導体集積回路装置 |
JP7158160B2 (ja) | 2018-03-05 | 2022-10-21 | エイブリック株式会社 | 半導体装置 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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CN105789178A (zh) * | 2014-12-25 | 2016-07-20 | 中航(重庆)微电子有限公司 | 熔丝结构、包含该熔丝结构的半导体器件及制备方法 |
JP6620024B2 (ja) * | 2015-03-12 | 2019-12-11 | エイブリック株式会社 | 半導体装置 |
JP6620023B2 (ja) * | 2015-03-12 | 2019-12-11 | エイブリック株式会社 | 半導体装置およびその製造方法 |
US9917055B2 (en) * | 2015-03-12 | 2018-03-13 | Sii Semiconductor Corporation | Semiconductor device having fuse element |
JP2017045839A (ja) * | 2015-08-26 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6926806B2 (ja) * | 2017-08-09 | 2021-08-25 | 富士電機株式会社 | 半導体装置及びその製造方法 |
US10651136B2 (en) * | 2017-09-05 | 2020-05-12 | Globalfoundries Inc. | Technique for decoupling plasma antennae from actual circuitry |
JP7390841B2 (ja) * | 2019-09-30 | 2023-12-04 | エイブリック株式会社 | 半導体装置及びその製造方法 |
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JP2016122771A (ja) * | 2014-12-25 | 2016-07-07 | ローム株式会社 | チップ部品 |
US10586774B2 (en) | 2014-12-25 | 2020-03-10 | Rohm Co., Ltd. | Structure comprising an inductor and resistor |
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JP7158160B2 (ja) | 2018-03-05 | 2022-10-21 | エイブリック株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
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TWI618221B (zh) | 2018-03-11 |
TW201448162A (zh) | 2014-12-16 |
KR102156820B1 (ko) | 2020-09-16 |
CN103972211B (zh) | 2018-10-12 |
JP6215020B2 (ja) | 2017-10-18 |
US20140210042A1 (en) | 2014-07-31 |
CN103972211A (zh) | 2014-08-06 |
KR20140095990A (ko) | 2014-08-04 |
US9570537B2 (en) | 2017-02-14 |
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