JP2013092517A - スキャン・チェーン用動的クロック領域バイパス - Google Patents

スキャン・チェーン用動的クロック領域バイパス Download PDF

Info

Publication number
JP2013092517A
JP2013092517A JP2012150054A JP2012150054A JP2013092517A JP 2013092517 A JP2013092517 A JP 2013092517A JP 2012150054 A JP2012150054 A JP 2012150054A JP 2012150054 A JP2012150054 A JP 2012150054A JP 2013092517 A JP2013092517 A JP 2013092517A
Authority
JP
Japan
Prior art keywords
scan
bypass
clock domain
test
chains
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2012150054A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013092517A5 (enExample
Inventor
C Tecmara Ramesh
シー．テクマラ ラメッシュ
Kumar Priyesh
クマー プリエシュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Corp filed Critical LSI Corp
Publication of JP2013092517A publication Critical patent/JP2013092517A/ja
Publication of JP2013092517A5 publication Critical patent/JP2013092517A5/ja
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2012150054A 2011-10-25 2012-07-04 スキャン・チェーン用動的クロック領域バイパス Ceased JP2013092517A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/280,797 US8812921B2 (en) 2011-10-25 2011-10-25 Dynamic clock domain bypass for scan chains
US13/280,797 2011-10-25

Publications (2)

Publication Number Publication Date
JP2013092517A true JP2013092517A (ja) 2013-05-16
JP2013092517A5 JP2013092517A5 (enExample) 2015-08-06

Family

ID=47263057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012150054A Ceased JP2013092517A (ja) 2011-10-25 2012-07-04 スキャン・チェーン用動的クロック領域バイパス

Country Status (6)

Country Link
US (1) US8812921B2 (enExample)
EP (1) EP2587273A1 (enExample)
JP (1) JP2013092517A (enExample)
KR (1) KR20130045158A (enExample)
CN (1) CN103076558B (enExample)
TW (1) TW201317596A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020518826A (ja) * 2017-05-08 2020-06-25 ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ 集積回路での動的スキャンチェーン再構成

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8037355B2 (en) * 2007-06-07 2011-10-11 Texas Instruments Incorporated Powering up adapter and scan test logic TAP controllers
WO2009137727A1 (en) * 2008-05-07 2009-11-12 Mentor Graphics Corporation Scan cell use with reduced power consumption
JP6232215B2 (ja) * 2013-06-20 2017-11-15 ラピスセミコンダクタ株式会社 半導体装置、表示装置、及び信号取込方法
JP6130239B2 (ja) * 2013-06-20 2017-05-17 ラピスセミコンダクタ株式会社 半導体装置、表示装置、及び信号取込方法
GB2520506B (en) * 2013-11-21 2020-07-29 Advanced Risc Mach Ltd Partial Scan Cell
US20160061892A1 (en) * 2014-08-29 2016-03-03 Qualcomm Incorporated Scan programmable register controlled clock architecture for testing asynchronous domains
CN104749515B (zh) * 2015-03-31 2017-12-15 中国人民解放军国防科学技术大学 一种基于顺序等分分段式的低功耗扫描测试方法和装置
US10436837B2 (en) * 2015-10-19 2019-10-08 Globalfoundries Inc. Auto test grouping/clock sequencing for at-speed test
TWI646845B (zh) * 2016-05-19 2019-01-01 晨星半導體股份有限公司 條件式存取晶片、其內建自我測試電路及測試方法
US10048315B2 (en) * 2016-07-06 2018-08-14 Stmicroelectronics International N.V. Stuck-at fault detection on the clock tree buffers of a clock source
CN110514981B (zh) * 2018-05-22 2022-04-12 龙芯中科技术股份有限公司 集成电路的时钟控制方法、装置及集成电路
EP3903114B1 (en) * 2019-01-30 2024-04-24 Siemens Industry Software Inc. Multi-capture at-speed scan test based on a slow clock signal
CN109857024B (zh) * 2019-02-01 2021-11-12 京微齐力(北京)科技有限公司 人工智能模块的单元性能测试方法和系统芯片
TWI689738B (zh) * 2019-02-21 2020-04-01 瑞昱半導體股份有限公司 測試系統
IT202000001636A1 (it) * 2020-01-28 2021-07-28 Stmicroelectronics Shenzhen R&D Co Ltd Circuito elettronico e corrispondente procedimento per testare circuiti elettronici
JP7305583B2 (ja) * 2020-03-05 2023-07-10 株式会社東芝 半導体集積回路
US11342914B2 (en) * 2020-06-19 2022-05-24 Juniper Networks, Inc. Integrated circuit having state machine-driven flops in wrapper chains for device testing
CN112183005B (zh) * 2020-09-29 2022-11-11 飞腾信息技术有限公司 集成电路测试模式下的dft电路构建方法及应用
CN112526328B (zh) * 2020-10-28 2022-11-01 深圳市紫光同创电子有限公司 边界扫描测试方法
US11454671B1 (en) * 2021-06-30 2022-09-27 Apple Inc. Data gating using scan enable pin
US11680982B2 (en) * 2021-10-26 2023-06-20 Stmicroelectronics International N.V. Automatic test pattern generation circuitry in multi power domain system on a chip
CN114091393B (zh) * 2021-11-26 2025-09-26 芯盟科技有限公司 一种执行工程变更指令的方法、装置、设备和存储介质
KR102670130B1 (ko) * 2021-12-29 2024-05-27 연세대학교 산학협력단 스캔 체인의 다중 고장 진단장치 및 방법
JP2024063970A (ja) * 2022-10-27 2024-05-14 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置のスキャンテスト方法
US12306246B2 (en) 2023-08-21 2025-05-20 Stmicroelectronics International N.V. Partial chain reconfiguration for test time reduction
US12493076B2 (en) * 2023-09-20 2025-12-09 Apple Inc. Scan data transfer circuits for multi-die chip testing
CN118332979B (zh) * 2024-06-11 2024-08-20 奇捷科技(深圳)有限公司 一种在ECO中使用Scan DEF文件的方法
CN120104412B (zh) * 2025-05-07 2025-07-11 上海韬润半导体有限公司 一种用于集成电路调试的系统

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH095403A (ja) * 1995-06-23 1997-01-10 Nec Corp 半導体集積論理回路
JP2003058273A (ja) * 2001-08-13 2003-02-28 Oki Electric Ind Co Ltd ホールドタイム測定回路
JP2004077356A (ja) * 2002-08-21 2004-03-11 Nec Micro Systems Ltd スキャンチェーン回路、スキャンチェーン構築方法およびそのプログラム
JP2004170244A (ja) * 2002-11-20 2004-06-17 Matsushita Electric Ind Co Ltd 組み込み自己検査回路
US20050055615A1 (en) * 2003-09-08 2005-03-10 Agashe Anupama Anlruddha At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform
US20060026473A1 (en) * 2004-07-29 2006-02-02 Teck Wee Patrick Tan Inversion of scan clock for scan cells
US7373568B1 (en) * 2003-01-21 2008-05-13 Marvell Israel Ltd. Scan insertion
JP2008286553A (ja) * 2007-05-15 2008-11-27 Toshiba Corp 半導体集積回路モジュール
US20090187801A1 (en) * 2008-01-17 2009-07-23 Kamlesh Pandey Method and system to perform at-speed testing
JP2009216619A (ja) * 2008-03-12 2009-09-24 Texas Instr Japan Ltd 半導体集積回路装置
JP2010223808A (ja) * 2009-03-24 2010-10-07 Fujitsu Ltd 回路モジュール、半導体集積回路、および検査装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5390190A (en) 1992-05-29 1995-02-14 Sun Microsystems, Inc. Inter-domain latch for scan based design
US5477545A (en) * 1993-02-09 1995-12-19 Lsi Logic Corporation Method and apparatus for testing of core-cell based integrated circuits
EP0813151A4 (en) * 1995-12-27 1999-03-31 Koken Kk CONTROL DEVICE
US5909451A (en) 1996-11-21 1999-06-01 Sun Microsystems, Inc. System and method for providing scan chain for digital electronic device having multiple clock domains
EP1826579A1 (en) 2001-02-15 2007-08-29 Syntest Technologies, Inc. Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan test
US7032202B2 (en) 2002-11-19 2006-04-18 Broadcom Corporation System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chains
US7124342B2 (en) * 2004-05-21 2006-10-17 Syntest Technologies, Inc. Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits
JP2007518988A (ja) 2004-01-19 2007-07-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 複数のクロックドメインを備える回路のテスティング
US7418640B2 (en) * 2004-05-28 2008-08-26 Synopsys, Inc. Dynamically reconfigurable shared scan-in test architecture
WO2006064300A1 (en) 2004-12-13 2006-06-22 Infineon Technologies Ag Circuitry and method for an at-speed scan test
US7406639B2 (en) * 2004-12-13 2008-07-29 Lsi Corporation Scan chain partition for reducing power in shift mode
CN101156076B (zh) 2005-02-11 2011-04-27 Nxp股份有限公司 具有多个时钟域的测试准备集成电路及测试该集成电路的方法
US7129762B1 (en) * 2005-02-17 2006-10-31 Xilinx, Inc. Efficient implementation of a bypassable flip-flop with a clock enable
DE602006015084D1 (de) * 2005-11-02 2010-08-05 Nxp Bv Ic-testverfahren und vorrichtungen
US20080126898A1 (en) 2006-11-27 2008-05-29 Kamlesh Pandey System and method for generating on-chip individual clock domain based scan enable signal used for launch of last shift type of at-speed scan testing
US20080133989A1 (en) * 2006-12-05 2008-06-05 Sony Computer Entertainment Inc. Method And Apparatus For Scan Chain Circuit AC Test
ES2364506T3 (es) 2007-04-13 2011-09-05 Fundacio Privada Centre Tecnologic De Telecomunicacions De Catalunya Procedimiento y sistema para medir la calidad de nodos en red.
JP2008275480A (ja) 2007-04-27 2008-11-13 Nec Electronics Corp 半導体集積回路のテスト回路、テスト方法
US7831876B2 (en) * 2007-10-23 2010-11-09 Lsi Corporation Testing a circuit with compressed scan chain subsets
US8775857B2 (en) * 2010-12-28 2014-07-08 Stmicroelectronics International N.V. Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH095403A (ja) * 1995-06-23 1997-01-10 Nec Corp 半導体集積論理回路
JP2003058273A (ja) * 2001-08-13 2003-02-28 Oki Electric Ind Co Ltd ホールドタイム測定回路
JP2004077356A (ja) * 2002-08-21 2004-03-11 Nec Micro Systems Ltd スキャンチェーン回路、スキャンチェーン構築方法およびそのプログラム
JP2004170244A (ja) * 2002-11-20 2004-06-17 Matsushita Electric Ind Co Ltd 組み込み自己検査回路
US7373568B1 (en) * 2003-01-21 2008-05-13 Marvell Israel Ltd. Scan insertion
US20050055615A1 (en) * 2003-09-08 2005-03-10 Agashe Anupama Anlruddha At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform
US20060026473A1 (en) * 2004-07-29 2006-02-02 Teck Wee Patrick Tan Inversion of scan clock for scan cells
JP2008286553A (ja) * 2007-05-15 2008-11-27 Toshiba Corp 半導体集積回路モジュール
US20090187801A1 (en) * 2008-01-17 2009-07-23 Kamlesh Pandey Method and system to perform at-speed testing
JP2009216619A (ja) * 2008-03-12 2009-09-24 Texas Instr Japan Ltd 半導体集積回路装置
JP2010223808A (ja) * 2009-03-24 2010-10-07 Fujitsu Ltd 回路モジュール、半導体集積回路、および検査装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020518826A (ja) * 2017-05-08 2020-06-25 ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ 集積回路での動的スキャンチェーン再構成
JP7179765B2 (ja) 2017-05-08 2022-11-29 ザイリンクス インコーポレイテッド 集積回路での動的スキャンチェーン再構成

Also Published As

Publication number Publication date
TW201317596A (zh) 2013-05-01
CN103076558A (zh) 2013-05-01
EP2587273A1 (en) 2013-05-01
US8812921B2 (en) 2014-08-19
CN103076558B (zh) 2017-04-12
KR20130045158A (ko) 2013-05-03
US20130103994A1 (en) 2013-04-25

Similar Documents

Publication Publication Date Title
JP2013092517A (ja) スキャン・チェーン用動的クロック領域バイパス
JP4903365B2 (ja) スキャンベースの集積回路でスキャンパターンをブロードキャストする方法および装置
US8819508B2 (en) Scan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testing
US8726108B2 (en) Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain
US8671320B2 (en) Integrated circuit comprising scan test circuitry with controllable number of capture pulses
US8850280B2 (en) Scan enable timing control for testing of scan cells
US8924801B2 (en) At-speed scan testing of interface functional logic of an embedded memory or other circuit core
US20130275824A1 (en) Scan-based capture and shift of interface functional signal values in conjunction with built-in self-test
US20140149812A1 (en) Scan test circuitry with control circuitry configured to support a debug mode of operation
US8898527B2 (en) At-speed scan testing of clock divider logic in a clock module of an integrated circuit
US9689924B2 (en) Circuit for testing integrated circuits
US8700962B2 (en) Scan test circuitry configured to prevent capture of potentially non-deterministic values
WO2007140366A2 (en) Testing components of i/o paths of an integrated circuit
US20080005634A1 (en) Scan chain circuitry that enables scan testing at functional clock speed
US8738978B2 (en) Efficient wrapper cell design for scan testing of integrated
US20130111285A1 (en) Scan test circuitry comprising scan cells with functional output multiplexing
US8799731B2 (en) Clock control for reducing timing exceptions in scan testing of an integrated circuit
Xiang Test compression for launch-on-capture transition fault testing
US20140201584A1 (en) Scan test circuitry comprising at least one scan chain and associated reset multiplexing circuitry
US20060041806A1 (en) Testing method for semiconductor device and testing circuit for semiconductor device
JP2009530599A (ja) デバイスおよびデバイスを試験する方法
JP4272898B2 (ja) 半導体テスト回路及びそのテスト方法
Rabenalt et al. Highly efficient test response compaction using a hierarchical X-masking technique
JP2004117258A (ja) 半導体集積回路のテスト容易化回路
JP2002189063A (ja) 半導体装置

Legal Events

Date Code Title Description
RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20140729

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20140805

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20140805

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150623

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150623

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160426

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20160506

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160510

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160808

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170110

A045 Written measure of dismissal of application [lapsed due to lack of payment]

Free format text: JAPANESE INTERMEDIATE CODE: A045

Effective date: 20170530