TW201317596A - 用於掃描鏈之動態時脈域旁路 - Google Patents
用於掃描鏈之動態時脈域旁路 Download PDFInfo
- Publication number
- TW201317596A TW201317596A TW101118239A TW101118239A TW201317596A TW 201317596 A TW201317596 A TW 201317596A TW 101118239 A TW101118239 A TW 101118239A TW 101118239 A TW101118239 A TW 101118239A TW 201317596 A TW201317596 A TW 201317596A
- Authority
- TW
- Taiwan
- Prior art keywords
- scan
- bypass
- chains
- sub
- test
- Prior art date
Links
- 238000012360 testing method Methods 0.000 claims abstract description 182
- 238000000034 method Methods 0.000 claims description 7
- 230000004044 response Effects 0.000 claims description 7
- 238000004590 computer program Methods 0.000 claims description 4
- 238000012790 confirmation Methods 0.000 claims description 2
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 11
- 102100040858 Dual specificity protein kinase CLK4 Human genes 0.000 description 11
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 11
- 101000749298 Homo sapiens Dual specificity protein kinase CLK4 Proteins 0.000 description 11
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 10
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 10
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 10
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 10
- 230000006835 compression Effects 0.000 description 8
- 238000007906 compression Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000013598 vector Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000013481 data capture Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318594—Timing aspects
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/280,797 US8812921B2 (en) | 2011-10-25 | 2011-10-25 | Dynamic clock domain bypass for scan chains |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201317596A true TW201317596A (zh) | 2013-05-01 |
Family
ID=47263057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW101118239A TW201317596A (zh) | 2011-10-25 | 2012-05-22 | 用於掃描鏈之動態時脈域旁路 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8812921B2 (enExample) |
| EP (1) | EP2587273A1 (enExample) |
| JP (1) | JP2013092517A (enExample) |
| KR (1) | KR20130045158A (enExample) |
| CN (1) | CN103076558B (enExample) |
| TW (1) | TW201317596A (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI646845B (zh) * | 2016-05-19 | 2019-01-01 | 晨星半導體股份有限公司 | 條件式存取晶片、其內建自我測試電路及測試方法 |
| TWI689738B (zh) * | 2019-02-21 | 2020-04-01 | 瑞昱半導體股份有限公司 | 測試系統 |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8078898B2 (en) * | 2007-06-07 | 2011-12-13 | Texas Instruments Incorporated | Synchronizing TAP controllers with sequence on TMS lead |
| WO2009137727A1 (en) * | 2008-05-07 | 2009-11-12 | Mentor Graphics Corporation | Scan cell use with reduced power consumption |
| JP6232215B2 (ja) * | 2013-06-20 | 2017-11-15 | ラピスセミコンダクタ株式会社 | 半導体装置、表示装置、及び信号取込方法 |
| JP6130239B2 (ja) * | 2013-06-20 | 2017-05-17 | ラピスセミコンダクタ株式会社 | 半導体装置、表示装置、及び信号取込方法 |
| GB2520506B (en) * | 2013-11-21 | 2020-07-29 | Advanced Risc Mach Ltd | Partial Scan Cell |
| US20160061892A1 (en) * | 2014-08-29 | 2016-03-03 | Qualcomm Incorporated | Scan programmable register controlled clock architecture for testing asynchronous domains |
| CN104749515B (zh) * | 2015-03-31 | 2017-12-15 | 中国人民解放军国防科学技术大学 | 一种基于顺序等分分段式的低功耗扫描测试方法和装置 |
| US10436837B2 (en) * | 2015-10-19 | 2019-10-08 | Globalfoundries Inc. | Auto test grouping/clock sequencing for at-speed test |
| US10048315B2 (en) * | 2016-07-06 | 2018-08-14 | Stmicroelectronics International N.V. | Stuck-at fault detection on the clock tree buffers of a clock source |
| US10317464B2 (en) * | 2017-05-08 | 2019-06-11 | Xilinx, Inc. | Dynamic scan chain reconfiguration in an integrated circuit |
| CN110514981B (zh) * | 2018-05-22 | 2022-04-12 | 龙芯中科技术股份有限公司 | 集成电路的时钟控制方法、装置及集成电路 |
| CN113383242B (zh) * | 2019-01-30 | 2024-08-20 | 西门子工业软件有限公司 | 基于慢时钟信号的多重捕获全速扫描测试电路 |
| CN109857024B (zh) * | 2019-02-01 | 2021-11-12 | 京微齐力(北京)科技有限公司 | 人工智能模块的单元性能测试方法和系统芯片 |
| IT202000001636A1 (it) * | 2020-01-28 | 2021-07-28 | Stmicroelectronics Shenzhen R&D Co Ltd | Circuito elettronico e corrispondente procedimento per testare circuiti elettronici |
| JP7305583B2 (ja) * | 2020-03-05 | 2023-07-10 | 株式会社東芝 | 半導体集積回路 |
| US11342914B2 (en) * | 2020-06-19 | 2022-05-24 | Juniper Networks, Inc. | Integrated circuit having state machine-driven flops in wrapper chains for device testing |
| CN112183005B (zh) * | 2020-09-29 | 2022-11-11 | 飞腾信息技术有限公司 | 集成电路测试模式下的dft电路构建方法及应用 |
| CN112526328B (zh) * | 2020-10-28 | 2022-11-01 | 深圳市紫光同创电子有限公司 | 边界扫描测试方法 |
| US11454671B1 (en) * | 2021-06-30 | 2022-09-27 | Apple Inc. | Data gating using scan enable pin |
| US11680982B2 (en) * | 2021-10-26 | 2023-06-20 | Stmicroelectronics International N.V. | Automatic test pattern generation circuitry in multi power domain system on a chip |
| CN114091393B (zh) * | 2021-11-26 | 2025-09-26 | 芯盟科技有限公司 | 一种执行工程变更指令的方法、装置、设备和存储介质 |
| KR102670130B1 (ko) * | 2021-12-29 | 2024-05-27 | 연세대학교 산학협력단 | 스캔 체인의 다중 고장 진단장치 및 방법 |
| JP2024063970A (ja) * | 2022-10-27 | 2024-05-14 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置のスキャンテスト方法 |
| US12306246B2 (en) | 2023-08-21 | 2025-05-20 | Stmicroelectronics International N.V. | Partial chain reconfiguration for test time reduction |
| US12493076B2 (en) * | 2023-09-20 | 2025-12-09 | Apple Inc. | Scan data transfer circuits for multi-die chip testing |
| CN118332979B (zh) * | 2024-06-11 | 2024-08-20 | 奇捷科技(深圳)有限公司 | 一种在ECO中使用Scan DEF文件的方法 |
| CN120104412B (zh) * | 2025-05-07 | 2025-07-11 | 上海韬润半导体有限公司 | 一种用于集成电路调试的系统 |
Family Cites Families (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5390190A (en) | 1992-05-29 | 1995-02-14 | Sun Microsystems, Inc. | Inter-domain latch for scan based design |
| US5477545A (en) * | 1993-02-09 | 1995-12-19 | Lsi Logic Corporation | Method and apparatus for testing of core-cell based integrated circuits |
| JP2738351B2 (ja) * | 1995-06-23 | 1998-04-08 | 日本電気株式会社 | 半導体集積論理回路 |
| EP1632780A2 (en) * | 1995-12-27 | 2006-03-08 | Koken Co., Ltd. | Monitoring control apparatus |
| US5909451A (en) | 1996-11-21 | 1999-06-01 | Sun Microsystems, Inc. | System and method for providing scan chain for digital electronic device having multiple clock domains |
| EP1826579A1 (en) | 2001-02-15 | 2007-08-29 | Syntest Technologies, Inc. | Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan test |
| JP2003058273A (ja) * | 2001-08-13 | 2003-02-28 | Oki Electric Ind Co Ltd | ホールドタイム測定回路 |
| JP2004077356A (ja) * | 2002-08-21 | 2004-03-11 | Nec Micro Systems Ltd | スキャンチェーン回路、スキャンチェーン構築方法およびそのプログラム |
| US7032202B2 (en) | 2002-11-19 | 2006-04-18 | Broadcom Corporation | System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chains |
| JP2004170244A (ja) * | 2002-11-20 | 2004-06-17 | Matsushita Electric Ind Co Ltd | 組み込み自己検査回路 |
| US7373568B1 (en) * | 2003-01-21 | 2008-05-13 | Marvell Israel Ltd. | Scan insertion |
| US7124342B2 (en) * | 2004-05-21 | 2006-10-17 | Syntest Technologies, Inc. | Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits |
| US7134061B2 (en) * | 2003-09-08 | 2006-11-07 | Texas Instruments Incorporated | At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform |
| CN100554989C (zh) | 2004-01-19 | 2009-10-28 | Nxp股份有限公司 | 具有多个时钟域的电路的测试 |
| US7418640B2 (en) * | 2004-05-28 | 2008-08-26 | Synopsys, Inc. | Dynamically reconfigurable shared scan-in test architecture |
| US7447961B2 (en) * | 2004-07-29 | 2008-11-04 | Marvell International Ltd. | Inversion of scan clock for scan cells |
| US7406639B2 (en) * | 2004-12-13 | 2008-07-29 | Lsi Corporation | Scan chain partition for reducing power in shift mode |
| WO2006064300A1 (en) | 2004-12-13 | 2006-06-22 | Infineon Technologies Ag | Circuitry and method for an at-speed scan test |
| JP2008530549A (ja) | 2005-02-11 | 2008-08-07 | エヌエックスピー ビー ヴィ | 複数のクロック領域を有する集積回路のテスト方法 |
| US7129762B1 (en) * | 2005-02-17 | 2006-10-31 | Xilinx, Inc. | Efficient implementation of a bypassable flip-flop with a clock enable |
| WO2007069097A1 (en) * | 2005-11-02 | 2007-06-21 | Nxp B.V. | Ic testing methods and apparatus |
| US20080126898A1 (en) | 2006-11-27 | 2008-05-29 | Kamlesh Pandey | System and method for generating on-chip individual clock domain based scan enable signal used for launch of last shift type of at-speed scan testing |
| US20080133989A1 (en) * | 2006-12-05 | 2008-06-05 | Sony Computer Entertainment Inc. | Method And Apparatus For Scan Chain Circuit AC Test |
| DE602007013820D1 (de) | 2007-04-13 | 2011-05-19 | Fundacio Privada Ct Technologic De Telecomunicacions De Catalunya Castelldefels | Verfahren und system zur messung der qualität von vernetzungsknoten |
| JP2008275480A (ja) | 2007-04-27 | 2008-11-13 | Nec Electronics Corp | 半導体集積回路のテスト回路、テスト方法 |
| JP4802139B2 (ja) * | 2007-05-15 | 2011-10-26 | 株式会社東芝 | 半導体集積回路モジュール |
| US7831876B2 (en) * | 2007-10-23 | 2010-11-09 | Lsi Corporation | Testing a circuit with compressed scan chain subsets |
| US20090187801A1 (en) * | 2008-01-17 | 2009-07-23 | Kamlesh Pandey | Method and system to perform at-speed testing |
| JP2009216619A (ja) * | 2008-03-12 | 2009-09-24 | Texas Instr Japan Ltd | 半導体集積回路装置 |
| JP5625249B2 (ja) * | 2009-03-24 | 2014-11-19 | 富士通株式会社 | 回路モジュール、半導体集積回路、および検査装置 |
| US8775857B2 (en) * | 2010-12-28 | 2014-07-08 | Stmicroelectronics International N.V. | Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing |
-
2011
- 2011-10-25 US US13/280,797 patent/US8812921B2/en not_active Expired - Fee Related
-
2012
- 2012-05-22 TW TW101118239A patent/TW201317596A/zh unknown
- 2012-06-19 CN CN201210208775.9A patent/CN103076558B/zh not_active Expired - Fee Related
- 2012-06-20 KR KR1020120066278A patent/KR20130045158A/ko not_active Ceased
- 2012-07-04 JP JP2012150054A patent/JP2013092517A/ja not_active Ceased
- 2012-10-18 EP EP12188947.1A patent/EP2587273A1/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI646845B (zh) * | 2016-05-19 | 2019-01-01 | 晨星半導體股份有限公司 | 條件式存取晶片、其內建自我測試電路及測試方法 |
| TWI689738B (zh) * | 2019-02-21 | 2020-04-01 | 瑞昱半導體股份有限公司 | 測試系統 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20130103994A1 (en) | 2013-04-25 |
| CN103076558A (zh) | 2013-05-01 |
| CN103076558B (zh) | 2017-04-12 |
| EP2587273A1 (en) | 2013-05-01 |
| JP2013092517A (ja) | 2013-05-16 |
| KR20130045158A (ko) | 2013-05-03 |
| US8812921B2 (en) | 2014-08-19 |
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