CN100554989C - 具有多个时钟域的电路的测试 - Google Patents
具有多个时钟域的电路的测试 Download PDFInfo
- Publication number
- CN100554989C CN100554989C CNB2005800027060A CN200580002706A CN100554989C CN 100554989 C CN100554989 C CN 100554989C CN B2005800027060 A CNB2005800027060 A CN B2005800027060A CN 200580002706 A CN200580002706 A CN 200580002706A CN 100554989 C CN100554989 C CN 100554989C
- Authority
- CN
- China
- Prior art keywords
- test
- clock
- flip
- circuit
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318552—Clock circuits details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318594—Timing aspects
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Measurement Of Resistance Or Impedance (AREA)
- Radar Systems Or Details Thereof (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04100143.9 | 2004-01-19 | ||
EP04100143 | 2004-01-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1910465A CN1910465A (zh) | 2007-02-07 |
CN100554989C true CN100554989C (zh) | 2009-10-28 |
Family
ID=34802651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005800027060A Expired - Fee Related CN100554989C (zh) | 2004-01-19 | 2005-01-13 | 具有多个时钟域的电路的测试 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7565591B2 (zh) |
EP (1) | EP1709455B1 (zh) |
JP (1) | JP2007518988A (zh) |
CN (1) | CN100554989C (zh) |
AT (1) | ATE408152T1 (zh) |
DE (1) | DE602005009659D1 (zh) |
WO (1) | WO2005071426A1 (zh) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2897440A1 (fr) * | 2006-02-10 | 2007-08-17 | St Microelectronics Sa | Circuit electronique comprenant un mode de test securise par rupture d'une chaine de test, et procede associe. |
JP5160039B2 (ja) * | 2006-02-10 | 2013-03-13 | ルネサスエレクトロニクス株式会社 | 半導体装置及びそのテスト回路の追加方法 |
JP4091957B2 (ja) | 2006-02-17 | 2008-05-28 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 複数のクロック発生回路を含むテスト可能な集積回路 |
JP4845543B2 (ja) * | 2006-03-15 | 2011-12-28 | 富士通セミコンダクター株式会社 | 遅延故障試験回路 |
JP4815326B2 (ja) * | 2006-10-31 | 2011-11-16 | 富士通株式会社 | 集積回路のタイミング不良改善装置、並びに、集積回路のタイミング不良診断装置および方法、並びに、集積回路 |
US20090228751A1 (en) * | 2007-05-22 | 2009-09-10 | Tilman Gloekler | method for performing logic built-in-self-test cycles on a semiconductor chip and a corresponding semiconductor chip with a test engine |
JP2010261768A (ja) * | 2009-05-01 | 2010-11-18 | Sony Corp | 半導体集積回路、情報処理装置、および出力データ拡散方法、並びにプログラム |
JP2011007589A (ja) * | 2009-06-25 | 2011-01-13 | Renesas Electronics Corp | テスト方法、テスト制御プログラム及び半導体装置 |
CN102183721B (zh) * | 2010-12-14 | 2014-05-14 | 青岛海信信芯科技有限公司 | 多时钟域测试方法及测试电路 |
JP6054597B2 (ja) * | 2011-06-23 | 2016-12-27 | ラピスセミコンダクタ株式会社 | 半導体集積回路 |
US8812921B2 (en) | 2011-10-25 | 2014-08-19 | Lsi Corporation | Dynamic clock domain bypass for scan chains |
US8645778B2 (en) | 2011-12-31 | 2014-02-04 | Lsi Corporation | Scan test circuitry with delay defect bypass functionality |
US8726108B2 (en) | 2012-01-12 | 2014-05-13 | Lsi Corporation | Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain |
GB2507049A (en) | 2012-10-16 | 2014-04-23 | Ibm | Synchronizing Trace Data |
US9086457B2 (en) * | 2013-03-26 | 2015-07-21 | International Business Machines Corporation | Scan chain latch design that improves testability of integrated circuits |
FR3023027B1 (fr) * | 2014-06-27 | 2016-07-29 | St Microelectronics Crolles 2 Sas | Procede de gestion du fonctionnement d'un circuit redondant a vote majoritaire et dispositif associe |
KR102222643B1 (ko) | 2014-07-07 | 2021-03-04 | 삼성전자주식회사 | 스캔 체인 회로 및 이를 포함하는 집적 회로 |
CN106712922A (zh) * | 2015-11-12 | 2017-05-24 | 上海远景数字信息技术有限公司 | 一种高精度时钟信号测试系统及方法 |
US10649487B2 (en) * | 2018-07-05 | 2020-05-12 | Microchip Technology Incorporated | Fail-safe clock monitor with fault injection |
US10775435B1 (en) * | 2018-11-01 | 2020-09-15 | Cadence Design Systems, Inc. | Low-power shift with clock staggering |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2225879C (en) * | 1997-12-29 | 2001-05-01 | Jean-Francois Cote | Clock skew management method and apparatus |
US6966021B2 (en) * | 1998-06-16 | 2005-11-15 | Janusz Rajski | Method and apparatus for at-speed testing of digital circuits |
US6327684B1 (en) * | 1999-05-11 | 2001-12-04 | Logicvision, Inc. | Method of testing at-speed circuits having asynchronous clocks and controller for use therewith |
US6442722B1 (en) * | 1999-10-29 | 2002-08-27 | Logicvision, Inc. | Method and apparatus for testing circuits with multiple clocks |
DE10039001A1 (de) | 2000-08-10 | 2002-02-21 | Philips Corp Intellectual Pty | Anordnung zum Testen eines integrierten Schaltkreises |
US7191373B2 (en) * | 2001-03-01 | 2007-03-13 | Syntest Technologies, Inc. | Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques |
US6954887B2 (en) | 2001-03-22 | 2005-10-11 | Syntest Technologies, Inc. | Multiple-capture DFT system for scan-based integrated circuits |
US7134061B2 (en) * | 2003-09-08 | 2006-11-07 | Texas Instruments Incorporated | At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform |
-
2005
- 2005-01-13 AT AT05702664T patent/ATE408152T1/de not_active IP Right Cessation
- 2005-01-13 WO PCT/IB2005/050152 patent/WO2005071426A1/en active IP Right Grant
- 2005-01-13 DE DE602005009659T patent/DE602005009659D1/de active Active
- 2005-01-13 EP EP05702664A patent/EP1709455B1/en not_active Not-in-force
- 2005-01-13 CN CNB2005800027060A patent/CN100554989C/zh not_active Expired - Fee Related
- 2005-01-13 JP JP2006548560A patent/JP2007518988A/ja not_active Withdrawn
- 2005-01-13 US US10/586,217 patent/US7565591B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7565591B2 (en) | 2009-07-21 |
ATE408152T1 (de) | 2008-09-15 |
EP1709455B1 (en) | 2008-09-10 |
US20070186132A1 (en) | 2007-08-09 |
JP2007518988A (ja) | 2007-07-12 |
CN1910465A (zh) | 2007-02-07 |
WO2005071426A1 (en) | 2005-08-04 |
DE602005009659D1 (de) | 2008-10-23 |
EP1709455A1 (en) | 2006-10-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100554989C (zh) | 具有多个时钟域的电路的测试 | |
US7886207B1 (en) | Integrated circuit testing using segmented scan chains | |
JP3851782B2 (ja) | 半導体集積回路及びそのテスト方法 | |
US8499209B2 (en) | At-speed scan testing with controlled switching activity | |
Huang et al. | Statistical diagnosis for intermittent scan chain hold-time fault | |
CN1329833C (zh) | 用于容错和柔性测试签名生成器的方法和装置 | |
Yang et al. | Quick scan chain diagnosis using signal profiling | |
Geuzebroek et al. | Test point insertion for compact test sets | |
CN102221671B (zh) | 信号稳定性检测器及时延测试装置 | |
US20090319842A1 (en) | Generating device, generating method, program and recording medium | |
CN110514981B (zh) | 集成电路的时钟控制方法、装置及集成电路 | |
Wang et al. | Multiple fault diagnosis using n-detection tests | |
Wunderlich | The design of random-testable sequential circuits | |
US11699012B2 (en) | Coverage based microelectronic circuit, and method for providing a design of a microelectronic circuit | |
Pomeranz et al. | Test generation for synchronous sequential circuits using multiple observation times | |
US7240263B2 (en) | Apparatus for performing stuck fault testings within an integrated circuit | |
CN102663185A (zh) | 一种基于模糊处理的抗硬件木马电路设计方法 | |
Pomeranz et al. | Application of homing sequences to synchronous sequential circuit testing | |
CN101315412A (zh) | 一种扫描链故障诊断方法及系统 | |
CN110197069B (zh) | 一种兼容故障扫描测试实现a2木马检测的方法及装置 | |
Youssef et al. | Methodology for efficiently inserting and condensing test points | |
Liu et al. | On multiplexed signal tracing for post-silicon debug | |
Dalirsani et al. | Structural software-based self-test of network-on-chip | |
US7779375B2 (en) | Design structure for shutting off data capture across asynchronous clock domains during at-speed testing | |
El-Maleh et al. | A fast sequential learning technique for real circuits with application to enhancing ATPG performance |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: NXP CO., LTD. Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V. Effective date: 20071019 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20071019 Address after: Holland Ian Deho Finn Applicant after: Koninkl Philips Electronics NV Address before: Holland Ian Deho Finn Applicant before: Koninklijke Philips Electronics N.V. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091028 Termination date: 20140113 |