FR3023027B1 - Procede de gestion du fonctionnement d'un circuit redondant a vote majoritaire et dispositif associe - Google Patents
Procede de gestion du fonctionnement d'un circuit redondant a vote majoritaire et dispositif associeInfo
- Publication number
- FR3023027B1 FR3023027B1 FR1456023A FR1456023A FR3023027B1 FR 3023027 B1 FR3023027 B1 FR 3023027B1 FR 1456023 A FR1456023 A FR 1456023A FR 1456023 A FR1456023 A FR 1456023A FR 3023027 B1 FR3023027 B1 FR 3023027B1
- Authority
- FR
- France
- Prior art keywords
- resolved
- managing
- major
- associated device
- redundant circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318502—Test of Combinational circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Tests Of Electronic Circuits (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1456023A FR3023027B1 (fr) | 2014-06-27 | 2014-06-27 | Procede de gestion du fonctionnement d'un circuit redondant a vote majoritaire et dispositif associe |
US14/662,530 US9417282B2 (en) | 2014-06-27 | 2015-03-19 | Method for managing the operation of a circuit with triple modular redundancy and associated device |
DE112015002991.5T DE112015002991T5 (de) | 2014-06-27 | 2015-06-26 | Verfahren zum Managen des Betriebs einer redundanten Mehrheitsentscheidungsschaltung und zugehörige Vorrichtung |
CN201580034800.8A CN106662614B (zh) | 2014-06-27 | 2015-06-26 | 用于管理具有三模冗余的电路的操作的方法及相关装置 |
PCT/EP2015/064506 WO2015197813A1 (fr) | 2014-06-27 | 2015-06-26 | Procédé de gestion du fonctionnement d'un circuit redondant à vote majoritaire et dispositif associé |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1456023A FR3023027B1 (fr) | 2014-06-27 | 2014-06-27 | Procede de gestion du fonctionnement d'un circuit redondant a vote majoritaire et dispositif associe |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3023027A1 FR3023027A1 (fr) | 2016-01-01 |
FR3023027B1 true FR3023027B1 (fr) | 2016-07-29 |
Family
ID=51570626
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1456023A Expired - Fee Related FR3023027B1 (fr) | 2014-06-27 | 2014-06-27 | Procede de gestion du fonctionnement d'un circuit redondant a vote majoritaire et dispositif associe |
Country Status (5)
Country | Link |
---|---|
US (1) | US9417282B2 (fr) |
CN (1) | CN106662614B (fr) |
DE (1) | DE112015002991T5 (fr) |
FR (1) | FR3023027B1 (fr) |
WO (1) | WO2015197813A1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102018201710A1 (de) * | 2018-02-05 | 2019-08-08 | Robert Bosch Gmbh | Verfahren und Vorrichtung zum Überprüfen einer Funktion eines neuronalen Netzes |
EP3626561B1 (fr) * | 2018-09-18 | 2020-11-04 | KNORR-BREMSE Systeme für Nutzfahrzeuge GmbH | Système de freinage redondant pour un véhicule à commande autonome |
CN111142444A (zh) * | 2019-12-31 | 2020-05-12 | 华东计算技术研究所(中国电子科技集团公司第三十二研究所) | 基于dsp和cpld的三冗余运载火箭时序控制器 |
DE102020104595B3 (de) * | 2020-02-21 | 2021-05-12 | Infineon Technologies Ag | Integrierter Schaltkreis mit Selbsttestschaltung, Verfahren zum Betreiben eines integrierten Schaltkreises mit Selbsttestschaltung, Mehrkernprozessoreinrichtung und Verfahren zum Betreiben einer Mehrkernprozessoreinrichtung |
US11848672B2 (en) * | 2022-04-12 | 2023-12-19 | Stmicroelectronics International N.V. | Redundancy circuit |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6480019B2 (en) * | 2000-05-11 | 2002-11-12 | Goodrich Corporation | Multiple voted logic cell testable by a scan chain and system and method of testing the same |
US7565591B2 (en) * | 2004-01-19 | 2009-07-21 | Nxp B.V. | Testing of circuits with multiple clock domains |
CN101163978B (zh) * | 2005-02-01 | 2010-08-25 | Nxp股份有限公司 | 可测试电子电路及其测试方法和测试器 |
US7415645B2 (en) * | 2005-07-28 | 2008-08-19 | International Business Machines Corporation | Method and apparatus for soft-error immune and self-correcting latches |
US7482831B2 (en) * | 2006-05-10 | 2009-01-27 | Alcatel-Lucent Usa Inc. | Soft error tolerant flip flops |
US7673202B2 (en) * | 2006-09-28 | 2010-03-02 | Cisco Technology, Inc. | Single event upset test circuit and methodology |
US8402328B2 (en) * | 2009-07-24 | 2013-03-19 | StarDFX Technologies, Inc. | Apparatus and method for protecting soft errors |
-
2014
- 2014-06-27 FR FR1456023A patent/FR3023027B1/fr not_active Expired - Fee Related
-
2015
- 2015-03-19 US US14/662,530 patent/US9417282B2/en active Active
- 2015-06-26 DE DE112015002991.5T patent/DE112015002991T5/de active Pending
- 2015-06-26 CN CN201580034800.8A patent/CN106662614B/zh active Active
- 2015-06-26 WO PCT/EP2015/064506 patent/WO2015197813A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2015197813A1 (fr) | 2015-12-30 |
FR3023027A1 (fr) | 2016-01-01 |
CN106662614A (zh) | 2017-05-10 |
DE112015002991T5 (de) | 2017-04-20 |
CN106662614B (zh) | 2020-01-07 |
US9417282B2 (en) | 2016-08-16 |
US20150377962A1 (en) | 2015-12-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 2 |
|
PLSC | Publication of the preliminary search report |
Effective date: 20160101 |
|
PLFP | Fee payment |
Year of fee payment: 3 |
|
PLFP | Fee payment |
Year of fee payment: 4 |
|
PLFP | Fee payment |
Year of fee payment: 5 |
|
PLFP | Fee payment |
Year of fee payment: 6 |
|
PLFP | Fee payment |
Year of fee payment: 7 |
|
ST | Notification of lapse |
Effective date: 20220205 |