DE602005009659D1 - Prüfung von schaltungen mit mehreren taktdomänen - Google Patents

Prüfung von schaltungen mit mehreren taktdomänen

Info

Publication number
DE602005009659D1
DE602005009659D1 DE602005009659T DE602005009659T DE602005009659D1 DE 602005009659 D1 DE602005009659 D1 DE 602005009659D1 DE 602005009659 T DE602005009659 T DE 602005009659T DE 602005009659 T DE602005009659 T DE 602005009659T DE 602005009659 D1 DE602005009659 D1 DE 602005009659D1
Authority
DE
Germany
Prior art keywords
flop
flip
data
circuits
domains
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005009659T
Other languages
English (en)
Inventor
Johannes D Dingemanse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602005009659D1 publication Critical patent/DE602005009659D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Radar Systems Or Details Thereof (AREA)
DE602005009659T 2004-01-19 2005-01-13 Prüfung von schaltungen mit mehreren taktdomänen Active DE602005009659D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04100143 2004-01-19
PCT/IB2005/050152 WO2005071426A1 (en) 2004-01-19 2005-01-13 Testing of circuits with multiple clock domains

Publications (1)

Publication Number Publication Date
DE602005009659D1 true DE602005009659D1 (de) 2008-10-23

Family

ID=34802651

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005009659T Active DE602005009659D1 (de) 2004-01-19 2005-01-13 Prüfung von schaltungen mit mehreren taktdomänen

Country Status (7)

Country Link
US (1) US7565591B2 (de)
EP (1) EP1709455B1 (de)
JP (1) JP2007518988A (de)
CN (1) CN100554989C (de)
AT (1) ATE408152T1 (de)
DE (1) DE602005009659D1 (de)
WO (1) WO2005071426A1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2897440A1 (fr) * 2006-02-10 2007-08-17 St Microelectronics Sa Circuit electronique comprenant un mode de test securise par rupture d'une chaine de test, et procede associe.
JP5160039B2 (ja) * 2006-02-10 2013-03-13 ルネサスエレクトロニクス株式会社 半導体装置及びそのテスト回路の追加方法
JP4091957B2 (ja) 2006-02-17 2008-05-28 インターナショナル・ビジネス・マシーンズ・コーポレーション 複数のクロック発生回路を含むテスト可能な集積回路
JP4845543B2 (ja) * 2006-03-15 2011-12-28 富士通セミコンダクター株式会社 遅延故障試験回路
JP4815326B2 (ja) * 2006-10-31 2011-11-16 富士通株式会社 集積回路のタイミング不良改善装置、並びに、集積回路のタイミング不良診断装置および方法、並びに、集積回路
US20090228751A1 (en) * 2007-05-22 2009-09-10 Tilman Gloekler method for performing logic built-in-self-test cycles on a semiconductor chip and a corresponding semiconductor chip with a test engine
JP2010261768A (ja) * 2009-05-01 2010-11-18 Sony Corp 半導体集積回路、情報処理装置、および出力データ拡散方法、並びにプログラム
JP2011007589A (ja) * 2009-06-25 2011-01-13 Renesas Electronics Corp テスト方法、テスト制御プログラム及び半導体装置
CN102183721B (zh) * 2010-12-14 2014-05-14 青岛海信信芯科技有限公司 多时钟域测试方法及测试电路
JP6054597B2 (ja) * 2011-06-23 2016-12-27 ラピスセミコンダクタ株式会社 半導体集積回路
US8812921B2 (en) 2011-10-25 2014-08-19 Lsi Corporation Dynamic clock domain bypass for scan chains
US8645778B2 (en) 2011-12-31 2014-02-04 Lsi Corporation Scan test circuitry with delay defect bypass functionality
US8726108B2 (en) 2012-01-12 2014-05-13 Lsi Corporation Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain
GB2507049A (en) 2012-10-16 2014-04-23 Ibm Synchronizing Trace Data
US9086457B2 (en) * 2013-03-26 2015-07-21 International Business Machines Corporation Scan chain latch design that improves testability of integrated circuits
FR3023027B1 (fr) * 2014-06-27 2016-07-29 St Microelectronics Crolles 2 Sas Procede de gestion du fonctionnement d'un circuit redondant a vote majoritaire et dispositif associe
KR102222643B1 (ko) 2014-07-07 2021-03-04 삼성전자주식회사 스캔 체인 회로 및 이를 포함하는 집적 회로
CN106712922A (zh) * 2015-11-12 2017-05-24 上海远景数字信息技术有限公司 一种高精度时钟信号测试系统及方法
US10649487B2 (en) * 2018-07-05 2020-05-12 Microchip Technology Incorporated Fail-safe clock monitor with fault injection
US10775435B1 (en) * 2018-11-01 2020-09-15 Cadence Design Systems, Inc. Low-power shift with clock staggering

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2225879C (en) * 1997-12-29 2001-05-01 Jean-Francois Cote Clock skew management method and apparatus
US6966021B2 (en) * 1998-06-16 2005-11-15 Janusz Rajski Method and apparatus for at-speed testing of digital circuits
US6327684B1 (en) * 1999-05-11 2001-12-04 Logicvision, Inc. Method of testing at-speed circuits having asynchronous clocks and controller for use therewith
US6442722B1 (en) * 1999-10-29 2002-08-27 Logicvision, Inc. Method and apparatus for testing circuits with multiple clocks
DE10039001A1 (de) 2000-08-10 2002-02-21 Philips Corp Intellectual Pty Anordnung zum Testen eines integrierten Schaltkreises
US7191373B2 (en) * 2001-03-01 2007-03-13 Syntest Technologies, Inc. Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
US6954887B2 (en) 2001-03-22 2005-10-11 Syntest Technologies, Inc. Multiple-capture DFT system for scan-based integrated circuits
US7134061B2 (en) * 2003-09-08 2006-11-07 Texas Instruments Incorporated At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform

Also Published As

Publication number Publication date
US7565591B2 (en) 2009-07-21
ATE408152T1 (de) 2008-09-15
EP1709455B1 (de) 2008-09-10
US20070186132A1 (en) 2007-08-09
CN100554989C (zh) 2009-10-28
JP2007518988A (ja) 2007-07-12
CN1910465A (zh) 2007-02-07
WO2005071426A1 (en) 2005-08-04
EP1709455A1 (de) 2006-10-11

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Legal Events

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