CN103076558B - 用于扫描链的动态时钟域旁路 - Google Patents
用于扫描链的动态时钟域旁路 Download PDFInfo
- Publication number
- CN103076558B CN103076558B CN201210208775.9A CN201210208775A CN103076558B CN 103076558 B CN103076558 B CN 103076558B CN 201210208775 A CN201210208775 A CN 201210208775A CN 103076558 B CN103076558 B CN 103076558B
- Authority
- CN
- China
- Prior art keywords
- bypass
- subchain
- scan
- clock
- clock zone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318594—Timing aspects
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/280,797 | 2011-10-25 | ||
US13/280,797 US8812921B2 (en) | 2011-10-25 | 2011-10-25 | Dynamic clock domain bypass for scan chains |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103076558A CN103076558A (zh) | 2013-05-01 |
CN103076558B true CN103076558B (zh) | 2017-04-12 |
Family
ID=47263057
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210208775.9A Expired - Fee Related CN103076558B (zh) | 2011-10-25 | 2012-06-19 | 用于扫描链的动态时钟域旁路 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8812921B2 (zh) |
EP (1) | EP2587273A1 (zh) |
JP (1) | JP2013092517A (zh) |
KR (1) | KR20130045158A (zh) |
CN (1) | CN103076558B (zh) |
TW (1) | TW201317596A (zh) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8078898B2 (en) * | 2007-06-07 | 2011-12-13 | Texas Instruments Incorporated | Synchronizing TAP controllers with sequence on TMS lead |
US8890563B2 (en) * | 2008-05-07 | 2014-11-18 | Mentor Graphics Corporation | Scan cell use with reduced power consumption |
JP6130239B2 (ja) * | 2013-06-20 | 2017-05-17 | ラピスセミコンダクタ株式会社 | 半導体装置、表示装置、及び信号取込方法 |
JP6232215B2 (ja) * | 2013-06-20 | 2017-11-15 | ラピスセミコンダクタ株式会社 | 半導体装置、表示装置、及び信号取込方法 |
GB2520506B (en) * | 2013-11-21 | 2020-07-29 | Advanced Risc Mach Ltd | Partial Scan Cell |
US20160061892A1 (en) * | 2014-08-29 | 2016-03-03 | Qualcomm Incorporated | Scan programmable register controlled clock architecture for testing asynchronous domains |
CN104749515B (zh) * | 2015-03-31 | 2017-12-15 | 中国人民解放军国防科学技术大学 | 一种基于顺序等分分段式的低功耗扫描测试方法和装置 |
US10436837B2 (en) * | 2015-10-19 | 2019-10-08 | Globalfoundries Inc. | Auto test grouping/clock sequencing for at-speed test |
TWI646845B (zh) * | 2016-05-19 | 2019-01-01 | 晨星半導體股份有限公司 | 條件式存取晶片、其內建自我測試電路及測試方法 |
US10048315B2 (en) * | 2016-07-06 | 2018-08-14 | Stmicroelectronics International N.V. | Stuck-at fault detection on the clock tree buffers of a clock source |
US10317464B2 (en) * | 2017-05-08 | 2019-06-11 | Xilinx, Inc. | Dynamic scan chain reconfiguration in an integrated circuit |
CN110514981B (zh) * | 2018-05-22 | 2022-04-12 | 龙芯中科技术股份有限公司 | 集成电路的时钟控制方法、装置及集成电路 |
EP3903114B1 (en) * | 2019-01-30 | 2024-04-24 | Siemens Industry Software Inc. | Multi-capture at-speed scan test based on a slow clock signal |
CN109857024B (zh) * | 2019-02-01 | 2021-11-12 | 京微齐力(北京)科技有限公司 | 人工智能模块的单元性能测试方法和系统芯片 |
TWI689738B (zh) * | 2019-02-21 | 2020-04-01 | 瑞昱半導體股份有限公司 | 測試系統 |
JP7305583B2 (ja) * | 2020-03-05 | 2023-07-10 | 株式会社東芝 | 半導体集積回路 |
CN112183005B (zh) * | 2020-09-29 | 2022-11-11 | 飞腾信息技术有限公司 | 集成电路测试模式下的dft电路构建方法及应用 |
CN112526328B (zh) * | 2020-10-28 | 2022-11-01 | 深圳市紫光同创电子有限公司 | 边界扫描测试方法 |
US11680982B2 (en) * | 2021-10-26 | 2023-06-20 | Stmicroelectronics International N.V. | Automatic test pattern generation circuitry in multi power domain system on a chip |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7406639B2 (en) * | 2004-12-13 | 2008-07-29 | Lsi Corporation | Scan chain partition for reducing power in shift mode |
CN101300500A (zh) * | 2005-11-02 | 2008-11-05 | Nxp股份有限公司 | Ic测试方法及设备 |
US7831876B2 (en) * | 2007-10-23 | 2010-11-09 | Lsi Corporation | Testing a circuit with compressed scan chain subsets |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5390190A (en) | 1992-05-29 | 1995-02-14 | Sun Microsystems, Inc. | Inter-domain latch for scan based design |
US5477545A (en) * | 1993-02-09 | 1995-12-19 | Lsi Logic Corporation | Method and apparatus for testing of core-cell based integrated circuits |
JP2738351B2 (ja) * | 1995-06-23 | 1998-04-08 | 日本電気株式会社 | 半導体集積論理回路 |
EP0813151A4 (en) * | 1995-12-27 | 1999-03-31 | Koken Kk | CONTROL DEVICE |
US5909451A (en) | 1996-11-21 | 1999-06-01 | Sun Microsystems, Inc. | System and method for providing scan chain for digital electronic device having multiple clock domains |
EP1826579A1 (en) | 2001-02-15 | 2007-08-29 | Syntest Technologies, Inc. | Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan test |
JP2003058273A (ja) * | 2001-08-13 | 2003-02-28 | Oki Electric Ind Co Ltd | ホールドタイム測定回路 |
JP2004077356A (ja) * | 2002-08-21 | 2004-03-11 | Nec Micro Systems Ltd | スキャンチェーン回路、スキャンチェーン構築方法およびそのプログラム |
US7032202B2 (en) | 2002-11-19 | 2006-04-18 | Broadcom Corporation | System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chains |
JP2004170244A (ja) * | 2002-11-20 | 2004-06-17 | Matsushita Electric Ind Co Ltd | 組み込み自己検査回路 |
US7373568B1 (en) * | 2003-01-21 | 2008-05-13 | Marvell Israel Ltd. | Scan insertion |
US7124342B2 (en) * | 2004-05-21 | 2006-10-17 | Syntest Technologies, Inc. | Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits |
US7134061B2 (en) * | 2003-09-08 | 2006-11-07 | Texas Instruments Incorporated | At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform |
EP1709455B1 (en) | 2004-01-19 | 2008-09-10 | Nxp B.V. | Testing of circuits with multiple clock domains |
US7418640B2 (en) * | 2004-05-28 | 2008-08-26 | Synopsys, Inc. | Dynamically reconfigurable shared scan-in test architecture |
US7447961B2 (en) | 2004-07-29 | 2008-11-04 | Marvell International Ltd. | Inversion of scan clock for scan cells |
WO2006064300A1 (en) | 2004-12-13 | 2006-06-22 | Infineon Technologies Ag | Circuitry and method for an at-speed scan test |
WO2006085276A1 (en) | 2005-02-11 | 2006-08-17 | Nxp B.V. | Testing of an integrated circuit with a plurality of clock domains |
US7129762B1 (en) * | 2005-02-17 | 2006-10-31 | Xilinx, Inc. | Efficient implementation of a bypassable flip-flop with a clock enable |
US20080126898A1 (en) | 2006-11-27 | 2008-05-29 | Kamlesh Pandey | System and method for generating on-chip individual clock domain based scan enable signal used for launch of last shift type of at-speed scan testing |
US20080133989A1 (en) * | 2006-12-05 | 2008-06-05 | Sony Computer Entertainment Inc. | Method And Apparatus For Scan Chain Circuit AC Test |
ATE504998T1 (de) | 2007-04-13 | 2011-04-15 | Fundacio Privada Ct Tecnologic De Telecomunicacions De Catalunya | Verfahren und system zur messung der qualität von vernetzungsknoten |
JP2008275480A (ja) | 2007-04-27 | 2008-11-13 | Nec Electronics Corp | 半導体集積回路のテスト回路、テスト方法 |
JP4802139B2 (ja) * | 2007-05-15 | 2011-10-26 | 株式会社東芝 | 半導体集積回路モジュール |
US20090187801A1 (en) * | 2008-01-17 | 2009-07-23 | Kamlesh Pandey | Method and system to perform at-speed testing |
JP2009216619A (ja) * | 2008-03-12 | 2009-09-24 | Texas Instr Japan Ltd | 半導体集積回路装置 |
JP5625249B2 (ja) * | 2009-03-24 | 2014-11-19 | 富士通株式会社 | 回路モジュール、半導体集積回路、および検査装置 |
US8775857B2 (en) * | 2010-12-28 | 2014-07-08 | Stmicroelectronics International N.V. | Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing |
-
2011
- 2011-10-25 US US13/280,797 patent/US8812921B2/en not_active Expired - Fee Related
-
2012
- 2012-05-22 TW TW101118239A patent/TW201317596A/zh unknown
- 2012-06-19 CN CN201210208775.9A patent/CN103076558B/zh not_active Expired - Fee Related
- 2012-06-20 KR KR1020120066278A patent/KR20130045158A/ko not_active Application Discontinuation
- 2012-07-04 JP JP2012150054A patent/JP2013092517A/ja not_active Ceased
- 2012-10-18 EP EP12188947.1A patent/EP2587273A1/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7406639B2 (en) * | 2004-12-13 | 2008-07-29 | Lsi Corporation | Scan chain partition for reducing power in shift mode |
CN101300500A (zh) * | 2005-11-02 | 2008-11-05 | Nxp股份有限公司 | Ic测试方法及设备 |
US7831876B2 (en) * | 2007-10-23 | 2010-11-09 | Lsi Corporation | Testing a circuit with compressed scan chain subsets |
Also Published As
Publication number | Publication date |
---|---|
JP2013092517A (ja) | 2013-05-16 |
CN103076558A (zh) | 2013-05-01 |
EP2587273A1 (en) | 2013-05-01 |
TW201317596A (zh) | 2013-05-01 |
US20130103994A1 (en) | 2013-04-25 |
KR20130045158A (ko) | 2013-05-03 |
US8812921B2 (en) | 2014-08-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103076558B (zh) | 用于扫描链的动态时钟域旁路 | |
Wang et al. | VirtualScan: A new compressed scan technology for test cost reduction | |
KR101643776B1 (ko) | 스캔 테스트 시스템 및 방법 | |
US20160349320A1 (en) | Remote bus wrapper for testing remote cores using automatic test pattern generation and other techniques | |
US7352169B2 (en) | Testing components of I/O paths of an integrated circuit | |
EP1113279B1 (en) | Lbist controller circuits, systems, and methods with automated maximum scan channel lentgh determination | |
US8671320B2 (en) | Integrated circuit comprising scan test circuitry with controllable number of capture pulses | |
US8726108B2 (en) | Scan test circuitry configured for bypassing selected segments of a multi-segment scan chain | |
US9903913B2 (en) | Scan or JTAG controllable capture clock generation | |
US8819508B2 (en) | Scan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testing | |
US8700962B2 (en) | Scan test circuitry configured to prevent capture of potentially non-deterministic values | |
Zoellin et al. | BIST power reduction using scan-chain disable in the Cell processor | |
US20130111286A1 (en) | Scan enable timing control for testing of scan cells | |
EP0469238A2 (en) | Reduced delay circuits for shift register latch scan strings | |
US20110175638A1 (en) | Semiconductor integrated circuit and core test circuit | |
Cho et al. | California scan architecture for high quality and low power testing | |
US20060041806A1 (en) | Testing method for semiconductor device and testing circuit for semiconductor device | |
Chandra et al. | Multimode Illinois scan architecture for test application time and test data volume reduction | |
CN100442072C (zh) | 用以测试数字逻辑电路的测试电路 | |
US7702979B2 (en) | Semiconductor integrated circuit incorporating test configuration and test method for the same | |
Wang et al. | UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction | |
Sinanoglu | Scan architecture with align-encode | |
Chloupek et al. | Test pattern compression based on pattern overlapping and broadcasting | |
EP1357388A2 (en) | Input/output characterization register (chain) for an integrated circuit | |
Wang et al. | A Low Overhead High Test Compression Technique Using Pattern Clustering With $ n $-Detection Test Support |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20160721 Address after: Singapore Singapore Applicant after: Avago Technologies General IP (Singapore) Pte. Ltd. Address before: California, USA Applicant before: LSI Corp. |
|
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20181018 Address after: Singapore Singapore Patentee after: Avago Technologies General IP (Singapore) Pte. Ltd. Address before: Singapore Singapore Patentee before: Avago Technologies General IP (Singapore) Pte. Ltd. |
|
TR01 | Transfer of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170412 Termination date: 20190619 |
|
CF01 | Termination of patent right due to non-payment of annual fee |