DE602006015084D1 - Ic-testverfahren und vorrichtungen - Google Patents

Ic-testverfahren und vorrichtungen

Info

Publication number
DE602006015084D1
DE602006015084D1 DE602006015084T DE602006015084T DE602006015084D1 DE 602006015084 D1 DE602006015084 D1 DE 602006015084D1 DE 602006015084 T DE602006015084 T DE 602006015084T DE 602006015084 T DE602006015084 T DE 602006015084T DE 602006015084 D1 DE602006015084 D1 DE 602006015084D1
Authority
DE
Germany
Prior art keywords
scan chain
testing
shift register
wpo
wpi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006015084T
Other languages
English (en)
Inventor
Tom Waayers
Richard Morren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602006015084D1 publication Critical patent/DE602006015084D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
DE602006015084T 2005-11-02 2006-10-18 Ic-testverfahren und vorrichtungen Active DE602006015084D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05110277 2005-11-02
PCT/IB2006/053838 WO2007069097A1 (en) 2005-11-02 2006-10-18 Ic testing methods and apparatus

Publications (1)

Publication Number Publication Date
DE602006015084D1 true DE602006015084D1 (de) 2010-08-05

Family

ID=37913605

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006015084T Active DE602006015084D1 (de) 2005-11-02 2006-10-18 Ic-testverfahren und vorrichtungen

Country Status (8)

Country Link
US (1) US7945834B2 (de)
EP (1) EP1946131B1 (de)
JP (1) JP2009515160A (de)
CN (1) CN101300500B (de)
AT (1) ATE472107T1 (de)
DE (1) DE602006015084D1 (de)
TW (1) TW200730851A (de)
WO (1) WO2007069097A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8856601B2 (en) * 2009-08-25 2014-10-07 Texas Instruments Incorporated Scan compression architecture with bypassable scan chains for low test mode power
US8566656B2 (en) * 2009-12-22 2013-10-22 Nxp B.V. Testing circuit and method
CN102034556B (zh) * 2010-09-30 2012-11-21 福州瑞芯微电子有限公司 一种基于扫描链的存储器测试方法
US8627159B2 (en) * 2010-11-11 2014-01-07 Qualcomm Incorporated Feedback scan isolation and scan bypass architecture
TW201225529A (en) * 2010-12-03 2012-06-16 Fortune Semiconductor Corp Test mode controller and electronic apparatus with self-testing thereof
US8812921B2 (en) * 2011-10-25 2014-08-19 Lsi Corporation Dynamic clock domain bypass for scan chains
US8301947B1 (en) 2011-10-31 2012-10-30 Apple Inc. Dynamic scan chain grouping
US8645778B2 (en) 2011-12-31 2014-02-04 Lsi Corporation Scan test circuitry with delay defect bypass functionality
US8839063B2 (en) * 2013-01-24 2014-09-16 Texas Instruments Incorporated Circuits and methods for dynamic allocation of scan test resources
US8732632B1 (en) * 2013-03-15 2014-05-20 Cadence Design Systems, Inc. Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect test
US9575120B2 (en) * 2013-03-29 2017-02-21 International Business Machines Corporation Scan chain processing in a partially functional chip
CN103884981B (zh) * 2014-04-16 2016-11-02 威盛电子股份有限公司 隔离电路
US10578672B2 (en) 2015-12-31 2020-03-03 Stmicroelectronics (Grenoble 2) Sas Method, device and article to test digital circuits
US10069497B2 (en) * 2016-06-23 2018-09-04 Xilinx, Inc. Circuit for and method of implementing a scan chain in programmable resources of an integrated circuit
US9864005B1 (en) * 2016-08-31 2018-01-09 Northrop Grumman Systems Corporation Wave-pipelined logic circuit scanning system
US10747690B2 (en) * 2018-04-03 2020-08-18 Xilinx, Inc. Device with data processing engine array
US10866753B2 (en) 2018-04-03 2020-12-15 Xilinx, Inc. Data processing engine arrangement in a device
TWI689738B (zh) * 2019-02-21 2020-04-01 瑞昱半導體股份有限公司 測試系統
US11901006B2 (en) * 2019-05-16 2024-02-13 Xenergic Ab Shiftable memory and method of operating a shiftable memory
TWI722972B (zh) * 2020-10-19 2021-03-21 瑞昱半導體股份有限公司 具有測試機制的隔離電路及其測試方法
US11442106B2 (en) 2020-12-14 2022-09-13 Western Digital Technologies, Inc. Method and apparatus for debugging integrated circuit systems using scan chain
US11320485B1 (en) * 2020-12-31 2022-05-03 Nxp Usa, Inc. Scan wrapper architecture for system-on-chip
TWI819520B (zh) * 2022-03-10 2023-10-21 瑞昱半導體股份有限公司 測試電路與測試方法

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US6304987B1 (en) * 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
CN1073020A (zh) * 1991-12-04 1993-06-09 福建师范大学 数码转换时钟控制接口电路
WO1996041205A1 (en) * 1995-06-07 1996-12-19 Samsung Electronics Co., Ltd. Method and apparatus for testing a megacell in an asic using jtag
US6658615B2 (en) * 1998-06-30 2003-12-02 Texas Instruments Incorporated IC with IP core and user-added scan register
US6242269B1 (en) * 1997-11-03 2001-06-05 Texas Instruments Incorporated Parallel scan distributors and collectors and process of testing integrated circuits
JP3092704B2 (ja) * 1998-02-17 2000-09-25 日本電気株式会社 大規模集積回路およびそのボードテスト方法
US6560734B1 (en) * 1998-06-19 2003-05-06 Texas Instruments Incorporated IC with addressable test port
JP2001141784A (ja) * 1999-11-10 2001-05-25 Fujitsu Ltd 半導体素子テスト回路
US6615380B1 (en) * 1999-12-21 2003-09-02 Synopsys Inc. Dynamic scan chains and test pattern generation methodologies therefor
KR100896538B1 (ko) * 2001-09-20 2009-05-07 엔엑스피 비 브이 전자 장치
US6925583B1 (en) * 2002-01-09 2005-08-02 Xilinx, Inc. Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device
US7464311B2 (en) * 2002-08-05 2008-12-09 Mitsubishi Denki Kabushiki Kaisha Apparatus and method for device selective scans in data streaming test environment for a processing unit having multiple cores
US7539915B1 (en) * 2003-01-07 2009-05-26 Marvell Israel (Misl) Ltd. Integrated circuit testing using segmented scan chains
JP4274806B2 (ja) * 2003-01-28 2009-06-10 株式会社リコー 半導体集積回路およびスキャンテスト法
ATE347112T1 (de) * 2003-02-10 2006-12-15 Koninkl Philips Electronics Nv Testen von integrierten schaltungen
US20050010832A1 (en) * 2003-07-10 2005-01-13 International Business Machines Corporation Method and apparatus of reducing scan power in the process of unloading and restoring processor content by scan chain partition and disable
DE602005008552D1 (de) * 2004-01-19 2008-09-11 Nxp Bv Testarchitektur und -verfahren
US7725784B2 (en) * 2004-02-17 2010-05-25 Institut National Polytechnique De Grenoble Integrated circuit chip with communication means enabling remote control of testing means of IP cores of the integrated circuit
TWI263058B (en) * 2004-12-29 2006-10-01 Ind Tech Res Inst Wrapper testing circuits and method thereof for system-on-a-chip

Also Published As

Publication number Publication date
US20080288842A1 (en) 2008-11-20
JP2009515160A (ja) 2009-04-09
CN101300500B (zh) 2011-07-27
TW200730851A (en) 2007-08-16
CN101300500A (zh) 2008-11-05
EP1946131B1 (de) 2010-06-23
WO2007069097A1 (en) 2007-06-21
US7945834B2 (en) 2011-05-17
EP1946131A1 (de) 2008-07-23
ATE472107T1 (de) 2010-07-15

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