JP2012514318A5 - - Google Patents

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Publication number
JP2012514318A5
JP2012514318A5 JP2011542725A JP2011542725A JP2012514318A5 JP 2012514318 A5 JP2012514318 A5 JP 2012514318A5 JP 2011542725 A JP2011542725 A JP 2011542725A JP 2011542725 A JP2011542725 A JP 2011542725A JP 2012514318 A5 JP2012514318 A5 JP 2012514318A5
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JP
Japan
Prior art keywords
silicon
semiconductor
forming
layer
alloy
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JP2011542725A
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English (en)
Japanese (ja)
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JP5669752B2 (ja
JP2012514318A (ja
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Priority claimed from DE102008063402A external-priority patent/DE102008063402B4/de
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Publication of JP2012514318A5 publication Critical patent/JP2012514318A5/ja
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JP2011542725A 2008-12-31 2009-12-29 チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減 Active JP5669752B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102008063402A DE102008063402B4 (de) 2008-12-31 2008-12-31 Verringerung der Schwellwertspannungsfluktuation in Transistoren mit einer Kanalhalbleiterlegierung durch Verringern der Abscheideungleichmäßigkeiten
DE102008063402.6 2008-12-31
US12/637,112 2009-12-14
US12/637,112 US8236654B2 (en) 2008-12-31 2009-12-14 Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities
PCT/EP2009/009307 WO2010076018A1 (en) 2008-12-31 2009-12-29 Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities

Publications (3)

Publication Number Publication Date
JP2012514318A JP2012514318A (ja) 2012-06-21
JP2012514318A5 true JP2012514318A5 (enExample) 2013-02-07
JP5669752B2 JP5669752B2 (ja) 2015-02-18

Family

ID=42234616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011542725A Active JP5669752B2 (ja) 2008-12-31 2009-12-29 チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減

Country Status (6)

Country Link
US (1) US8236654B2 (enExample)
JP (1) JP5669752B2 (enExample)
KR (1) KR101539416B1 (enExample)
CN (1) CN102341906B (enExample)
DE (1) DE102008063402B4 (enExample)
WO (1) WO2010076018A1 (enExample)

Families Citing this family (8)

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Publication number Priority date Publication date Assignee Title
DE102009006886B4 (de) * 2009-01-30 2012-12-06 Advanced Micro Devices, Inc. Verringerung von Dickenschwankungen einer schwellwerteinstellenden Halbleiterlegierung durch Verringern der Strukturierungsungleichmäßigkeiten vor dem Abscheiden der Halbleiterlegierung
JP5605134B2 (ja) * 2010-09-30 2014-10-15 富士通セミコンダクター株式会社 半導体装置及びその製造方法
DE102010063296B4 (de) * 2010-12-16 2012-08-16 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Herstellungsverfahren mit reduzierter STI-Topograpie für Halbleiterbauelemente mit einer Kanalhalbleiterlegierung
US8609509B2 (en) 2011-09-22 2013-12-17 Globalfoundries Inc. Superior integrity of high-k metal gate stacks by forming STI regions after gate metals
US8377773B1 (en) * 2011-10-31 2013-02-19 Globalfoundries Inc. Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask
US8541281B1 (en) 2012-08-17 2013-09-24 Globalfoundries Inc. Replacement gate process flow for highly scaled semiconductor devices
US8969190B2 (en) 2012-08-24 2015-03-03 Globalfoundries Inc. Methods of forming a layer of silicon on a layer of silicon/germanium
US9029919B2 (en) 2013-02-01 2015-05-12 Globalfoundries Inc. Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer

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