CN205177853U - 鳍式场效应晶体管 - Google Patents

鳍式场效应晶体管 Download PDF

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CN205177853U
CN205177853U CN201520749088.7U CN201520749088U CN205177853U CN 205177853 U CN205177853 U CN 205177853U CN 201520749088 U CN201520749088 U CN 201520749088U CN 205177853 U CN205177853 U CN 205177853U
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柳青
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STMicroelectronics lnc USA
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Abstract

本实用新型涉及鳍式场效应晶体管。公开了一种双宽度的SOI？FinFET，其中应变的鳍的不同部分具有不同的宽度。一种制造这种双宽度的FinFET的方法包括利用湿化学蚀刻工艺对在源极区域和漏极区域中的应变的鳍进行横向凹陷化，从而保持鳍中的高度应变而同时将在源极区域和漏极区域中的鳍的宽度修剪到小于5nm。所得到的FinFET的特征在于在栅极下面的沟道区域中的鳍的较宽部分以及在源极区域和漏极区域中的鳍的较窄部分。较窄的鳍的优势在于在外延的升高的源极区域和漏极区域的生长期间其可以更为容易地被掺杂。

Description

鳍式场效应晶体管
技术领域
本公开内容大体上涉及用于使用在集成电路中的先进的晶体管结构。
背景技术
先进的集成电路典型地以应变沟道器件、绝缘体上硅衬底、FinFET(鳍式场效应晶体管)结构或其组合为特征，以便继续将晶体管栅极长度缩小到20nm以下。这种技术允许晶体管的沟道长度收缩而同时使得例如电流泄漏以及其他短沟道效应的不良结果最小化。
FinFET是一种电子开关器件，其特征在于形式为从衬底表面向外延伸的半导体鳍的导电沟道。在这种器件中，控制鳍中的电流的栅极包裹围绕着鳍的三侧从而影响来自三个表面而不是一个表面的电流流动。通过FinFET设计所达到的先进的控制较之在传统的平面器件中可能的而言在“开”状态产生了更快的开关性能并且在“关”状态产生了更少的电流泄漏。
将应变合并到半导体器件的沟道中拉伸了晶体的晶格，由此增加了沟道中的电荷载流子迁移率，从而使得器件变为更具响应性的开关。将压缩应变引入PFET晶体管中倾向于增加沟道中的空穴迁移率，导致针对施加到晶体管栅极的电压的变化的更快开关响应。类似地，将拉伸应变引入NFET晶体管中倾向于增加沟道中的电子迁移率，同样导致更快的开关响应。
有很多方法将应变引入FinFET的沟道区域中。用于引入应变的技术典型地包括将具有与硅衬底的晶体晶格尺寸或几何形状稍微不同的晶体晶格尺寸或几何形状的一个或多个材料的外延层并入到器件中。所述外延层例如可以用掺杂硅或硅锗(SiGe)制成。这种外延层伸可以并入源极区域和漏极区域，或者并入用来对沟道中的电流流动进行调节的晶体管栅极，或者并入作为鳍的沟道本身。可代替地，通过利用各种类型的绝缘体上硅(SOI)衬底可以从器件的下方在鳍中诱发应变。SOI衬底的特征在于掩埋绝缘体，典型地为在有源区域下面的掩埋氧化物层(BOX)。SOIFinFET器件已经在转让给本受让人的专利申请中有所公开，例如名称为“SOIFinFETTransistorwithStrainedChannel”的美国专利申请No.14/231,466、名称为“SiliconGermanium-on-insulatorFinFET”的美国专利申请No.14/588,116以及名称为“Defect-FreeStrain-RelaxedBufferLayer”的美国专利申请No.14/588,221，所有这些申请通过参考被全部并入于此。
实用新型内容
本申请的目的在于提供一种具有应变的沟道以及升高的源极区域和漏极区域的双宽度SOIFinFET。在制造应变的FinFET器件中，特别是这些具有长度小于约20nm的短沟道的FinFET器件，出现的一个挑战在于形成非常窄的半导体鳍而有意地减轻在鳍材料中的应变。使得鳍经受例如反应离子蚀刻(RIE)的负过程(subtractiveprocess)通过机械机制和化学机制的组合来去除材料，其中机械方面将破坏性的动能传递给了鳍的晶体晶格。本发明人已经观察到这种过程倾向于使晶体晶格中的应变松弛，而湿蚀刻为纯化学过程，其更为温和地改变晶格，由此具有保持应变的可能性。然而，湿蚀刻具有的限制在于其为各向同性的过程，缺乏方向上的控制。
根据本申请的一个方面，提供一种鳍式场效应晶体管，其特征在于，包括：硅衬底，具有掩埋在其中的氧化物层；升高的外延硅源极区域，位于所述硅衬底上方；升高的外延硅漏极区域，位于所述硅衬底上方；应变的硅鳍，具有：作为第一部分的沟道区域，所述沟道区域在升高的源极区域和漏极区域之间延伸，所述沟道区域具有第一鳍宽度；在所述源极区域中的第二鳍部分，所述第二鳍部分具有第二鳍宽度；以及在所述漏极区域中的第三鳍部分，所述第三鳍部分具有第三鳍宽度；以及金属栅极结构，包裹围绕着所述应变的硅鳍的至少三侧，以控制在所述沟道区域中的电流流动。
在一个实施例中，所述第三鳍部分在宽度上基本上等于所述第二鳍部分并且所述第二鳍部分小于所述沟道区域。
在一个实施例中，所述沟道区域具有在6nm-12nm的范围内的宽度，并且第二部分具有小于5nm的宽度。
在一个实施例中，在所述升高的源极区域和漏极区域中，所述应变的硅鳍具有在5-10的范围中的纵横比。
在一个实施例中，所述应变的硅鳍包括硅、硅锗或碳化硅中的一种或多种。
在一个实施例中，所述应变的硅鳍包括砷、硼以及磷中的一种或多种作为掺杂剂。
在一个实施例中，所述金属栅极结构包括由氮化硅或硅硼碳氮化物中的一种或多种制成的侧壁间隔物。
根据本申请的另一方面，提供一种鳍式场效应晶体管，其特征在于，包括：升高的源极区域；升高的漏极区域；鳍，从所述升高的源极区域延伸到所述升高的漏极区域，所述鳍具有沿着所述鳍的长度而变化的非均匀的鳍宽度；以及栅极，包裹围绕着所述鳍的沟道区域的三侧，所述栅极被配置为控制在所述升高的源极区域和所述升高的漏极区域之间的所述沟道区域之内的电流流动。
在一个实施例中，所述鳍的沟道区域大致是所述鳍的在所述沟道区域之外的部分的两倍厚。
在一个实施例中，所述鳍的沟道区域为应变的沟道区域。
在一个实施例中，所述鳍的在所述沟道区域之外的部分呈现基本上均匀的掺杂剂分布。
在一个实施例中，所述升高的源极区域和所述升高的漏极区域具有钻石形状轮廓。
根据本申请的方案，所得到的FinFET的特征在于在栅极下方的较宽的鳍以及在源极区域和漏极区域中的较窄的鳍。较窄的鳍的优势在于其可以在对于升高的源极区域和漏极区域的外延生长期间被更容易地掺杂。
附图说明
在附图中，相同的参考标号标识相似的元素或动作。在附图中的元素的尺寸和相对位置并非必须按照比例描绘。
图1为示出了根据这里所描述的一个实施例的在制造如图2A-图6D中所描述的双宽度FinFET的方法中的步骤的流程图。
图2A、图3A、图4A、图5A、图6A为在利用图1所示的方法的制造期间在连续步骤中的双宽度FinFET的顶平面视图，其中为了清楚起见省略了侧壁间隔物。
图2B、图3B、图4B、图5B、图6B为在利用图1所示的方法的制造期间在连续步骤中的沿着通过双宽度FinFET的源极区域/漏极区域的切割线的横截面视图。
图3C、图4C、图5C、图6C为在利用图1所示的方法的制造期间在连续步骤中的沿着通过双宽度FinFET的鳍并且跨越栅极的切割线的横截面视图。
图3D、图4D、图5D、图6D为在利用图1所示的方法的制造期间在连续步骤中的沿着通过双宽度FinFET的栅极并且跨越鳍的切割线的横截面视图。
具体实施方式
在下面的描述中，列举了特定的具体细节以便提供对于所公开的主题的各个方面的全面理解。然而，所公开的主题可以无需这些特定的具体细节来实施。在一些例子中，对于包括这里所公开的主题的实施例的半导体处理的已知结构和方法没有进行详细的描述，以便避免对于本公开的其他方面的描述的模糊化。
除非上下文另有要求，否则贯穿说明书和随附的权利要求，用语“包括”以及其变形例如“包含”以及“具有”应当被解释为开放式的囊括性意义，也就是“包括但不限于”。
贯穿说明书提到“一个实施例”或者“一实施例”意味着与实施例相关联地描述的特定特征、结构或特性被包括在至少一个实施例中。如此，贯穿说明书在各个地方出现的短语“在一个实施例中”或“在一实施例中”并不必然全部指代相同的方面。进一步，特定的特征、结构或特性可以以任何适合的方式组合在本公开的一个或多个方面中。
贯穿说明书提到集成电路通常意在于包括建立在半导体衬底上的集成电路组件，无论所述组件是否一起耦接成电路或者是否能够被互连。贯穿说明书，术语“层”在其最广泛的意义上被使用，从而包括膜、盖层或类似，并且一个层可以包括多个子层。
贯穿说明书提到传统的用于沉积氮化硅、二氧化硅、金属或类似材料的薄膜沉积技术包括例如化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、金属有机化学气相沉积(MOCVD)、等离子体增强的化学气相沉积(PECVD)、等离子体气相沉积(PVD)、原子层沉积(ALD)、分子束外延(MBE)、电镀、化学镀以及类似工艺。这里参照这种工艺的例子来描述特定的实施例。然而，本公开以及对于特定沉积技术的参考不应当被限于这些所描述的。例如，在一些环境中，一种参照CVD的描述可代替地利用PVD来完成，或者指定了电镀的描述可以可代替地利用化学镀来完成。此外，提及薄膜形成的传统技术可以包括原位生长膜。例如，在一些实施例中，可以通过将硅表面暴露在氧气中或者暴露在加热的腔室的湿气中来获得氧化物到希望的厚度的受控的生长。
贯穿说明书提及传统的光刻技术，在半导体制造领域中已知为用于对各种薄膜进行图案化，包括典型地跟随有蚀刻工艺的旋转-曝光-显影工艺序列。可代替地或者附加地，还可以使用光致抗蚀剂来对硬掩膜(例如，氮化硅硬掩膜)进行图案化，而该硬掩膜反过来可以被用来对底层膜进行图案化。
贯穿说明书提及用于选择性地去除多晶硅、氮化硅、二氧化硅、金属、光致抗蚀剂、聚酰亚胺或类似材料的半导体制造领域中已知的传统蚀刻技术包括例如湿化学蚀刻、反应离子(等离子体)蚀刻(RIE)、洗涤、湿清洗、预清洗、喷淋清洗、化学机械平面化(CMP)以及类似的工艺。这里参照这种工艺的例子对特定的实施例进行描述。然而，本公开以及对于特定沉积技术的参照不应当限于所描述的。在一些例子中，两种这样的技术可以互换。例如，剥离光致抗蚀剂可以包括将样本浸泡在湿化学浴中或可代替地将湿化学品直接喷涂在样本上。
特定的实施例在这里参照着已经生产的双宽度FinFET来描述，然而，本公开以及对于特定材料、尺度以及细节和处理步骤的顺序的参照为示例性的并且不应当限于所示出的这些。
回到附图，图1示出了根据一个实施例的在制造用于高性能集成电路的双宽度FinFET的方法中的步骤。用于在绝缘体上硅(SOI)上构造双宽度FinFET的方法100中的步骤进一步由图2A-图6D来描述，并且在下面进行阐释。在图中的每一个中，A为示出了用于其他视图的切割线的在制造期间的当前步骤处的器件的顶视平面图。B为沿着通过栅极的切割线的横截面视图；C为沿着跨越栅极与鳍对准的切割线的横截面视图；并且D为沿着跨越在源极区域/漏极区域中的鳍的切割线的横截面视图。
在102，根据一个实施例，在SOI晶片上形成应变的鳍122，所述应变的鳍122具有基本上均匀的鳍宽度126。所述SOI晶片包括硅衬底、掩埋氧化物(BOX)层118以及具有在约35nm-50nm的范围中的厚度的顶部硅层120。注意到为了简化，所述硅衬底从图中省略。可代替地，可以使用应变的SOI(sSOI)晶片，其被提供有已经赋予顶部硅层120的应变。SOI晶片以及sSOI晶片为通常在半导体行业中使用的标准起始材料。可代替地，体硅晶片可以用作起始材料，其中可以形成BOX层118和应变的顶部硅层120二者作为当前的制造工艺的初始步骤。如果希望应变的硅锗(SiGe)鳍，例如针对PFET器件，则可以利用在本领域中已知的方法将锗原子并入顶部硅层120中从而形成张力应变的SiGe膜。本领域中已知的应变松弛的缓冲(SRB)层可选地可以包括在衬底中，从而使具有高锗浓度的顶部硅层120稳定化。可代替地，可以将碳原子并入顶部硅层120中从而创建应变的碳化硅(SiC)鳍。
可以利用传统的针对较宽鳍的远紫外线(EUV)直接光刻工艺或者例如针对较窄鳍的自对准侧壁图像转移(SIT)工艺，对顶部硅层120进行图案化以形成在图2A、图2B中所示的鳍122。在这里所描述的实施例中，鳍宽度126为狭窄的，希望在约6nm-12nm的范围中，这可以利用SIT技术达到。SIT技术是本领域已知的并且因此在此不做详细解释。SIT工艺能够将SiN侧壁间隔物用作鳍硬掩膜来限定非常高的纵横比的鳍122。根据SIT技术，首先在顶部硅层120的顶部上形成芯轴或者临时结构。接着在芯轴上方保形地沉积氮化硅膜并且将其平坦化从而形成在芯轴的侧上的侧壁间隔物。接着去除芯轴，留下一对狭窄的侧壁间隔物用作用于限定鳍122的硬掩膜。一旦硬掩膜被图案化，鳍122被蚀刻到顶部硅层120中向下一直到BOX118。由此形成的所述鳍122将用作FinFET的沟道区域。
在形成鳍122之后，从硅表面生长厚栅极氧化物124，如图2B所示。接着对鳍122进行图案化，从而在被保持在栅极区域中的同时，从将要位于FinFET的源极区域和漏极区域中的鳍的部分中去除栅极氧化物124。
在104，形成包裹围绕着每个鳍122的三个侧的栅极结构128，如图3A-图3D所示。栅极结构128于是描画了每个鳍122的三个部分。在栅极结构下面的第一中心部分为FinFET的沟道区域。第二部分从栅极结构128延伸出进入到FinFET的源极区域。鳍的第三部分从栅极结构128延伸出进入到FinFET的漏极区域。
用于形成这种栅极结构的处理步骤在本领域内为已知的，并因此不需在此进行详细描述。在一个实施例中，栅极结构128包括多晶硅栅极130,、氮化硅(SiN)盖层132以及由SiN或例如硅硼碳氮化物(SiBCN)的低k材料制成的侧壁间隔物134。注意到，栅极结构未出现在图3B中，因为切割线在栅极区域之外与鳍交叉。
在106，二氧化硅(SiO2)膜140被定向沉积在鳍122的顶部上以及在SiN盖层132的顶部上，如图4A-图4D所示。定向沉积可以利用例如气体团离子束(GCIB)工艺来完成。所述GCIB工艺在本领域内为已知的并且已经在美国专利公开No.2014/0239401中被描述用于带角度的注入。采用了GCIB的定向沉积工艺可以例如作为连同由AppliedMaterials公司所提供的薄膜沉积装置一同提供的专有工艺而获得。所述定向沉积工艺优先在水平表面上沉积氧化膜140，而在鳍122的侧壁或者侧壁间隔物134上有最少的沉积。在一个实施例中，氧化膜140具有在约10nm-15nm的范围中的厚度。在定向沉积步骤之后，可以执行短暂的氢氟酸(HF)酸浸从而接触到侧壁，而不会从水平表面去除氧化膜140的显著部分。
在108，对鳍122进行修剪从而将在栅极区域之外的鳍的第二部分和第三部分的鳍宽度126降低到较窄的鳍宽度142，如图5A-图5D中所示。同时，在栅极结构128下面的鳍的沟道区域保持其最初的鳍宽度126，由此创建了双宽度鳍。第一鳍宽度124和第二鳍宽度126在图5A中指示出。在一个实施例中，较窄的鳍宽度142约为4nm，而原始的鳍宽度126其目标定为约为8nm。可以利用例如SCI湿蚀刻工艺对硅或SiGe鳍进行横向的破坏而同时氧化膜140保护鳍122的顶部来对鳍宽度进行修剪，如图5B所示。蚀刻剂还将修剪最远离栅极结构128的鳍122的端部，导致鳍的整体长度稍微变短。然而，在栅极结构128之下，鳍122由氧化物124以及多晶硅栅极130和SiN盖层132保护，其与鳍的侧壁和顶部相接触，如图5D所示。在盖层的顶部上的氧化膜140，如图5C所示，实际上并不需要，但是其也无害。
在源极区域和漏极区域中具有较窄鳍宽度142的鳍部分的一个优势在于较窄的鳍可以更为容易地被掺杂。例如，当掺杂剂被引入进入鳍的较薄部分时，所述掺杂剂更为均匀地分布，其有助于更为尖锐的源极结和漏极结。然而不利地，蚀刻鳍122倾向于使应变松弛。然而，利用双宽度鳍122，鳍的沟道区域即在栅极结构128下面的区域保持为未蚀刻，因此在沟道区域中的应变没有受损。因此，在沟道区域中的电荷载流子迁移率保持增强，保留了应变沟道器件的性能优益。
在110，利用例如短暂氢氟酸(HF)酸浸的传统的预清洗来去除氧化膜140。BOX的顶部部分可以在预清洗步骤中被去除，然而BOX将基本上不受影响，由于其远远厚于氧化膜140。在氧化膜140被去除之后，升高的源极和漏极(RSD)区域144从鳍122的侧表面和顶表面外延地生长，如图6A-图6D所示，形成具有拉长的钻石状轮廓的电荷储存库。RSD区域144可以在外延工艺期间被原位掺杂，其中砷(As)或磷(P)用于NFET器件，或者硼(B)用于PFET器件。鳍122对于掺杂剂物种的暴露还将掺杂剂引入到鳍中，掺杂剂贯穿狭窄的鳍宽度142而非均匀地分布。在FinFET的操作期间，RSD区域144提供电荷载流子来支持鳍122的沟道部分之内的电流流动。所述RSD区域144仅仅在鳍122暴露的栅极结构128之外生长。因此，RSD区域144没有示出在图6D的横截面视图中。
在112，可以去除多晶硅栅极130并且利用本领域内已知的取代金属栅极(RMG)工艺来用金属栅极取代多晶硅栅极130。在RMG工艺中，多晶硅栅极130被暴露于对于SiN具有选择性的消耗多晶硅的蚀刻剂，从而使得侧壁间隔物基本上无损。所述侧壁间隔物结构接着被填充有金属。所述金属栅极可以包括多层，诸如例如氮化钛(TiN)或碳化钛(TiC)的功函数金属，并且栅极电极典型地由钨(W)制成。
最终，利用例如包括沉积层间电介质(ILD)、在ILD中蚀刻接触孔并且利用金属填充所述接触孔的传统的大马士革工艺来针对完成的双宽度FinFET器件制作接触。
应当理解的是，虽然在此出于说明的目的对本公开的特定实施例进行了描述，然而可以做出各种修改而不会背离本公开的精神和范围。相应地，除了由所附的权利要求限制之外，本公开并不受限。
鉴于前面详细的描述，可以对实施例作出这些以及其他的改变。大体上，在随后的权利要求中，使用的术语不应当被解释为将权利要求限制于在说明书和权利要求中所公开的特定的实施例，而是应当被解释为随着权利要求所囊括的等同物的整体范围而包括所有可能的实施例。相应地，权利要求不受本公开内容的限制。
上面所描述的各个实施例可以被组合从而提供进一步的实施例。所有在本说明书中提及以及/或列入申请数据表格中的美国专利、美国专利申请公开、美国专利申请、外国专利、外国专利申请和非专利公开整体通过参考而并入于此。如果需要可以对实施例的方面进行修改以采用各种专利、申请和公开的概念来提供进一步的实施例。

Claims (12)

1.一种鳍式场效应晶体管，其特征在于，包括：
硅衬底，具有掩埋在其中的氧化物层；
升高的外延硅源极区域，位于所述硅衬底上方；
升高的外延硅漏极区域，位于所述硅衬底上方；
应变的硅鳍，具有：作为第一部分的沟道区域，所述沟道区域在升高的源极区域和漏极区域之间延伸，所述沟道区域具有第一鳍宽度；在所述源极区域中的第二鳍部分，所述第二鳍部分具有第二鳍宽度；以及在所述漏极区域中的第三鳍部分，所述第三鳍部分具有第三鳍宽度；以及
金属栅极结构，包裹围绕着所述应变的硅鳍的至少三侧，以控制在所述沟道区域中的电流流动。
2.根据权利要求1的鳍式场效应晶体管，其特征在于，所述第三鳍部分在宽度上基本上等于所述第二鳍部分并且所述第二鳍部分小于所述沟道区域。
3.根据权利要求2的鳍式场效应晶体管，其特征在于，所述沟道区域具有在6nm-12nm的范围内的宽度，并且第二部分具有小于5nm的宽度。
4.根据权利要求1的鳍式场效应晶体管，其特征在于，在所述升高的源极区域和漏极区域中，所述应变的硅鳍具有在5-10的范围中的纵横比。
5.根据权利要求1的鳍式场效应晶体管，其特征在于，所述应变的硅鳍包括硅、硅锗或碳化硅中的一种或多种。
6.根据权利要求1的鳍式场效应晶体管，其特征在于，所述应变的硅鳍包括砷、硼以及磷中的一种或多种作为掺杂剂。
7.根据权利要求1的鳍式场效应晶体管，其特征在于，所述金属栅极结构包括由氮化硅或硅硼碳氮化物中的一种或多种制成的侧壁间隔物。
8.一种鳍式场效应晶体管，其特征在于，包括：
升高的源极区域；
升高的漏极区域；
鳍，从所述升高的源极区域延伸到所述升高的漏极区域，所述鳍具有沿着所述鳍的长度而变化的非均匀的鳍宽度；以及
栅极，包裹围绕着所述鳍的沟道区域的三侧，所述栅极被配置为控制在所述升高的源极区域和所述升高的漏极区域之间的所述沟道区域之内的电流流动。
9.根据权利要求8的鳍式场效应晶体管，其特征在于，所述鳍的沟道区域大致是所述鳍的在所述沟道区域之外的部分的两倍厚。
10.根据权利要求8的鳍式场效应晶体管，其特征在于，所述鳍的沟道区域为应变的沟道区域。
11.根据权利要求8的鳍式场效应晶体管，其特征在于，所述鳍的在所述沟道区域之外的部分呈现基本上均匀的掺杂剂分布。
12.根据权利要求8的鳍式场效应晶体管，其特征在于，所述升高的源极区域和所述升高的漏极区域具有钻石形状轮廓。
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