CN106328538B - 自对准硅锗鳍式fet - Google Patents

自对准硅锗鳍式fet Download PDF

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CN106328538B
CN106328538B CN201511001598.7A CN201511001598A CN106328538B CN 106328538 B CN106328538 B CN 106328538B CN 201511001598 A CN201511001598 A CN 201511001598A CN 106328538 B CN106328538 B CN 106328538B
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CN106328538A (zh
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N·卢贝
P·莫林
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STMicroelectronics lnc USA
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Abstract

本披露涉及自对准硅锗鳍式FET。一种自对准SiGe鳍式FET器件的特征在于经弛豫的具有高锗浓度的沟道区。初始地形成经弛豫的沟道以接受锗，而不是首先将锗引入该沟道然后尝试使所产生的应变膜弛豫。以此方式，可以在没有应变或损坏晶格的情况下确立锗的存在。在将锗引入到鳍晶格结构中之前，相对于多个本征硅鳍使栅极结构图案化，以确保栅极适当地对准。对准栅极结构之后，硅鳍被分段以使硅晶格弹性地弛豫。然后，将锗引入到经弛豫的硅晶格中，以产生基本上无应力并且也无缺陷的SiGe沟道。使用所描述的方法，在结构稳定的膜中得到的锗浓度可以增加到大于85％的水平。

Description

自对准硅锗鳍式FET
技术领域
本披露总体上涉及用于制造高性能鳍式FET器件的阵列的技术。
背景技术
先进的集成电路的特征经常在于应变沟道晶体管、绝缘体上硅(SOI)衬底、鳍式FET结构或其组合，以便继续按比例决定低于20nm的晶体管栅极长度。这类技术允许晶体管的沟道长度缩小同时最小化有害结果如电流泄漏和其他短沟道效应。
鳍式FET是电子切换器件，其中，常规的平坦半导体沟道被从衬底表面向外延伸的半导体鳍替代。在这种器件中，控制鳍中的电流流动的栅极环绕该鳍的三侧以影响来自三个表面而不是一个表面的电流流动。用鳍式FET设计实现的改进控制带来更快的切换性能并且然后有可能用平坦晶体管减少电流泄漏。在转让给与本专利申请相同的受让人的美国专利8,759,874和美国专利申请公开US2014/0175554中进一步详细地描述了鳍式FET。
应变硅晶体管已经被开发以增加穿过半导体晶格的载流子(即，电子或空穴)的迁移率。将应变结合到半导体器件的沟道中拉伸了晶体晶格，由此增加了沟道中的载流子迁移率，从而使得该器件变为更具有响应性的开关。将压缩应变引入到PFET晶体管中倾向于增加沟道中的空穴迁移率，导致了对施加到晶体管栅极的电压的变化的更快的切换响应。类似地，将拉伸应变引入到NFET晶体管中倾向于增加沟道中的电子迁移率，也导致了更快的切换响应。
针对平坦器件和鳍式FET两者，存在多种方式来将拉伸应变或压缩应变引入到晶体管中。此类技术通常需要将一种或多种材料的多个外延层结合到该器件中，这些材料具有稍微不同于硅衬底的晶体晶格尺寸或几何形状。这些外延层可以由例如掺杂硅或硅锗(SiGe)制成。此类外延层可以被结合到源极区和栅极区中、被结合到被用于调制沟道中的电流流动的晶体管栅极中、或者被结合到作为鳍的一部分的沟道自身中。例如，引入应变的一种方式为用硅化合物(如硅锗)来替换来自源极区和漏极区或者来自沟道的体硅。因为Si-Ge键合比Si-Si键合更长，在SiGe晶格中存在更多的开放空间。因此，相比于穿过包含较短的Si-Si键合的晶格，穿过包含狭长的Si-Ge键合和Ge-Ge键合的晶格的电子移动得更加自由。存在具有更长键合的锗原子倾向于拉伸晶格，导致内部应变。例如，在外延晶体生长的受控过程中，其中，新的SiGe晶体层从体硅晶体的表面中生长，可以完成用SiGe原子替换硅原子同时维持下面的体硅晶体的相同的晶体结构。替代性地，通过使用各种类型的SOI衬底，可以在从器件下方的鳍中引起应变。SOI衬底的特征在于掩埋绝缘体，通常为在有源区下面的掩埋氧化物层(BOX)。已经在转让给本受让人的多个专利申请(例如，标题为“具有应变沟道的SOI鳍式FET晶体管(SOI FinFET Transistor with Strained Channel)”的美国专利申请号No.14/231,466)中披露了SOI鳍式FET器件，其通过引用以其整体结合于此。
发明内容
可以通过控制鳍的大小和元素组成来调谐在鳍式FET的沟道中的应变效应和迁移效应。针对SiGe膜而言，包含高浓度的锗(例如，在至少25％-40％的范围中)是有利的，以提供相比于较低浓度SiGe膜的增强的电子迁移率。在沟道区中的载流子迁移率确定了总体晶体管性能。因此，令人期望的是SiGe鳍式FET的鳍中的锗原子百分比浓度增加到尽可能高的水平。
虽然应变硅晶格是有益的，通过使用现有方法结合锗原子来创造应变倾向于损坏晶体晶格。结果，富锗膜的晶格结构倾向于为机械上不稳定的，尤其如果其包含高数量的结构缺陷，如故障或错位。此外，这种机械上不稳定的鳍可以是关于其纵横比或高宽比在结构上受限制的。此限制是不令人期望的，因为鳍式FET的一个优点是竖直结构的鳍具有小的占用面积。
通过创造经弛豫的富锗膜作为应变膜的替代方案可以避免导致这种不稳定性的错位缺陷。在此描述的自对准SiGe鳍式FET器件的特征在于经弛豫的具有高锗浓度的沟道区。初始地形成经弛豫的沟道以接受锗，而不是首先将锗引入该沟道并然后尝试使所产生的应变膜弛豫。因此，可以不用应变或损坏晶格而确立锗的存在。在此描述的CMOS鳍式FET制造方法中，在将锗引入到鳍晶格结构中之前，相对于多个本征硅鳍使栅极结构图案化，以确保栅极被适当地对准。对准栅极结构之后，硅鳍被分段以使硅晶格弹性地弛豫。然后，将锗引入到经弛豫的硅晶格中，以产生基本上无应力并且也无缺陷的SiGe沟道。因为在具有小体积的区段鳍中不能增强应力，当引入锗时简单地不显现晶格缺陷。以此方式，在结构上稳定的膜中实现的锗浓度可以增加到大于85％的水平，产生几乎纯锗膜。
附图说明
在附图中，完全相同的参考号标识类似的元件或操作。附图中元件的大小和相对位置不一定成比例地绘制。
图1是根据在此描述的一个实施例概述了一种方法中的处理步骤序列的流程图，该方法可以被用于制造自对准的具有多个SiGe沟道的鳍式FET，这些SiGe沟道基本上没有晶体结构缺陷。
图2A至图10C是完成图1中展示的方法的每个处理步骤之后的鳍式FET阵列的不同视图。图2B、图3B、图4B、图5B、图6B、图8B、图9B和图10B是鳍式FET阵列的俯视图。图2A、图3A、图4A、图5A、图6A、图8A、图9A和图10A对应于跨鳍切割的鳍式FET阵列的横截面视图。图2C、图3C、图4C、图5C、图6C、图8C、图9C和图10C对应于沿着鳍切割的鳍式FET阵列的横截面视图。
图2A至图2C根据在此描述的一个实施例示出了在形成三个鳍之后的鳍式FET阵列。
图3A至图3C根据在此描述的一个实施例示出了在形成环绕每个鳍的三侧的四个栅极结构之后的鳍式FET阵列。
图4A至图4C根据在此描述的一个实施例示出了在将这些鳍分段以创造具有经弛豫的晶格的多个沟道区之后的鳍式FET阵列。
图5A至图5C根据在此描述的一个实施例示出了在用氧化物填充这些栅极结构之间的空间之后的鳍式FET阵列。
图6A至图6C根据在此描述的一个实施例示出了在将牺牲多晶硅栅极从这些栅极结构中去除之后的鳍式FET阵列。
图7A是根据在此描述的一个实施例在形成包含锗的覆盖膜之后跨鳍切割的鳍式FET阵列的横截面视图。
图7B是根据在此描述的一个实施例在将锗结合到鳍区段之后跨鳍切割的鳍式FET阵列的横截面视图。
图8A至图8C示出了在用多个金属栅极替换这些多晶硅栅极之后的鳍式FET阵列。
图9A至图9C示出了在形成包括外延延伸部的源极区和漏极区之后的鳍式FET阵列。
图10A至图10C示出了在形成源极接触和漏极接触之后的鳍式FET阵列。
具体实施方式
在以下说明中，陈述了某些具体细节以便提供对所披露的主题的不同方面的全面理解。然而，所披露的主题可以在没有这些具体细节的情况下实施。在一些实例中，尚未具体描述包括在此披露的主题的实施例的公知结构和半导体处理方法以免模糊本披露的其它方面的描述。
除非上下文另有要求，否则贯穿说明书和所附权利要求书，“包括(comprise)”一词及其多种变体(诸如，“包括(comprises)”和“包括(comprising)”)将以一种开放式的和包含性的意义来进行解释，也就是作为“包括，但不限于(including,but not limitedto)”。
贯穿本说明书对“一个实施例”或“一种实施例”的引用意味着关于实施例所描述的特定的特征、结构、或特性是包括在至少一个实施例中的。因此，在贯穿本说明书的各种地方出现的短语“在一个实施例中”或“在一种实施例中”不一定都是指相同的方面。此外，可以将这些特定的特征、结构、或特性以任何适当的方式在本披露的一个或多个方面中进行组合。
贯穿本说明书对集成电路的引用一般旨在于包括在半导体衬底上构建的集成电路部件，无论部件是否被一起耦接到电路中或者能够被互连。贯穿本说明书，以最广泛的意义使用术语“层”以包括薄膜、罩盖等，并且一个层可以由多个子层组成。
贯穿说明书对用于沉积氮化硅、二氧化硅、金属或者相似材料的常规薄膜沉积技术的引用包括诸如化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、金属有机化学气相沉积(MOCVD)、等离子体增强化学气相沉积(PECVD)、等离子体气相沉积(PVD)、原子层沉积(ALD)、分子束外延(MBE)、电镀、无电镀等这样的工艺。在此参考这类工艺的示例描述特定的实施例。然而，本披露和对某些沉积技术的引用不应当被限制于所描述的这些。例如，在一些境况中，可以替代性地使用PVD来完成引用CVD的描述，或者可以替代性地使用无电镀来实现指定电镀的描述。此外，对薄膜形成的常规技术的引用可以包括原位生长膜。例如，在一些实施例中，可以通过在受热室中使硅表面暴露于氧气或者潮气来实现控制氧化物生长至所期望的厚度。
贯穿本说明书对在半导体制造领域中已知的用于图案化各种薄膜的常规光刻技术的引用包括旋涂-曝光-显影工艺序列，通常接着是刻蚀工艺。替代性地或者附加地，光刻胶也可以用于图案化硬掩模(例如，氮化硅硬掩模)，其中，硬掩模又可以反过来用于图案化下面的膜。
贯穿本说明书对在半导体制造领域中已知的用于选择性去除多晶硅、氮化硅、二氧化硅、金属、光刻胶、聚酰亚胺或者类似材料的常规刻蚀技术的引用包括比如湿法化学刻蚀、反应离子(等离子体)刻蚀(RIE)、洗涤、湿法清洗、预清洗、喷洗、化学机械平坦化(CMP)等这样的工艺。在此参考这类工艺的示例描述特定的实施例。然而，本披露和对某些沉积技术的引用不应当被限制于所描述的这些。在一些实例中，两种这样的技术可以是可互换的。例如，剥离光刻胶可能需要在湿法化学浴器中浸渍样本或者替代性地向样本上直接喷射湿化学剂。
在此参照已经产生的自对准SiGe鳍式FET器件描述了具体的实施例；然而，本披露以及对某些材料、尺寸的引用、以及处理步骤的细节和顺序是示例性的并且不应局限于所示出的那些。
现在转向附图，图1根据一个实施例示出了制造自对准SiGe鳍式FET的方法200中的示例性步骤序列。方法200中的步骤202至步骤218在图2A至图10C中被展示并在以下被描述。在每个图集中，如由在俯视图中示出的切割线所指示的，B是俯视图，A是沿着鳍的横截面视图，以及C是跨鳍的横截面视图。
在202处，根据如在图2A至图2C中示出的一个实施例，在绝缘体上硅衬底上形成鳍304。SOI衬底包括在硅衬底300上的掩埋氧化物(BOX)层302之上的有源层。该有源层的厚度可以是在大约5nm至500nm宽度范围之内的任何地方。SOI晶片是通常在半导体行业中使用的标准原材料。替代性地，如在本领域中公知的，可以通过在扩散炉中生长厚的氧化物(通常80nm至120nm)而在体硅晶片上形成BOX层302。或者，衬底原材料可以是预应变SOI(sSOI)衬底或者绝缘体上SiGe(SGOI)衬底，其中，有源层是SiGe而不是硅。
可以使用具有SiN硬掩模的直接光刻和蚀刻以常规方式从有源层将鳍304图案化。替代性地，如在转让给与本专利申请相同的受让人的美国专利申请公开号2014/0175554中更详细描述的，可以使用例如侧壁图像转移(SIT)工艺形成鳍304。
侧壁图像转移工艺能够使用氮化硅(SiN)侧壁间隔物作为硬掩模限定极高纵横比的鳍304，而不是使用光刻掩模图案化鳍304。根据该侧壁图像转移技术，首先形成心轴或临时的结构，并且然后氮化硅被共形地沉积于该心轴之上并且被平坦化以在该心轴的这些侧上形成侧壁间隔物。然后去除该心轴，留下一对窄侧壁间隔物充当掩模以创造一对硅鳍304。通过任一方法，如在图2C中所示的，鳍304从衬底的顶表面竖直地向外延伸。鳍304的高度令人期望地在大约20nm至200nm的范围中。在一个实施例中，在SOI晶片上形成的鳍高50nm。在另一个实施例中，在体硅晶片上形成的鳍高100nm。鳍304的宽度令人期望地在大约5nm至20nm的范围中。相应地，鳍的相应的纵横比在大约4至10的范围中。在图2A、图2B、和图2C中示出了所产生的高纵横比的鳍304。
在204处，根据如在图3A至图3C中示出的一个实施例，在相对于鳍304的横向方向上形成假栅极结构316。形成假栅极结构316是半导体加工领域中公知的替换金属栅极(RMG)工艺的一部分。在RMG工艺中，由多晶硅制成的假栅极结构316随后被永久金属栅极结构替换。在美国专利申请公开号2014/0175554中更详细地描述了RMG工艺。
假栅极结构316包括薄栅极氧化物308、牺牲栅极310、硬掩模帽盖312以及一对侧壁间隔物314。首先，共形地沉积栅极氧化物308以覆盖鳍304。栅极氧化物308令人期望地由3nm至5nm厚的高k栅极材料(如，例如，在本领域公知的SiO2或HfO2)制成。接下来，使用氮化硅硬掩模沉积并图案化非晶硅或多晶硅层以形成牺牲栅极310。如果在牺牲栅极310中使用了非晶硅，可以通过在随后步骤处的退火将非晶硅材料转换成多晶硅。如在图3C中所示的，假栅极结构316然后与鳍304对准，从而使得假栅极结构316与鳍的三侧相接触。牺牲栅极310具有在大约50nm至100nm范围中的高度以及在大约15nm至25nm范围(令人期望地约20nm)中的宽度。用于将牺牲栅极310图案化的硬掩模在20nm至100nm厚度范围中。在图3A、图3B和图3C中示出的假栅极结构316被硬掩模帽盖312和多个侧壁间隔物314所覆盖。
通过沉积和图案化电介质材料层(例如，二氧化硅(SiO2)、氮化硅(SiN)、SiBCN、氮氧化硅(SiON)、SiOCN、碳酸硅(SiOC)等等)，在牺牲栅极310上形成侧壁间隔物314。在一个实施例中，通过原子层沉积(ALD)在牺牲栅极310的这些侧上形成SiN侧壁间隔物314。ALD工艺在牺牲栅极310之上以及在鳍304的顶部上共形地沉积SiN。在沉积之后，可以以惯例方式使用RIE工艺各向异性地蚀刻SiN以去除在这些栅极结构316之间的水平表面上的SiN，而留下牺牲栅极310的顶部上的SiN帽盖312和牺牲栅极310的这些侧壁上的SiN。SiN侧壁间隔物厚度令人期望地在大约5nm至20nm的范围中。
在206处，根据如在图4A至图4C中示出的一个实施例，将鳍304区段。可以通过具有蚀刻化学性质的对电介质侧壁间隔物314是选择性的常规蚀刻或者替代性地通过如上所描述的SIT工艺完成鳍304的区段。如在图4A、图4B和图4C中示出的，鳍区段313被切割以便以规则的间隔被间隔开，从而使得假栅极结构316在鳍区段313上居中。鳍区段长度在大约20nm至100nm的范围中，并且鳍区段313被大约10nm的间隙315间隔开来。相应地，鳍区段313的占用面积在大约100nm2至2000nm2的范围中。所产生的鳍区段313具有弹性地弛豫的硅晶格，其中，错位缺陷将不易于累积。即使鳍是由应变硅或SiGe制成的，在区段之后该鳍可以是完全弛豫的。无应变硅鳍将倾向于保持为完全弛豫的。
在208处，根据如在图5A至图5C中示出的一个实施例，用氧化物318填充将鳍区段313分离开的间隙315。使用常规的CMP工艺将氧化物318平坦化，该CMP工艺在牺牲栅极310上停止，由此去除硬掩模帽盖312。
在210处，根据如在图6A至图6C中示出的一个实施例，去除牺牲栅极310。可以使用常规的湿化学蚀刻剂(如，例如，热氨)完成去除牺牲栅极310，接着是HF处理以同样去除栅极氧化物308。
在212处，根据如在图7A和图7B中示出的一个实施例，使用氧化聚合工艺将区段313中的硅转换成富SiGe的鳍区段322。首先，如在图7A中示出的，在硅鳍区段313之上沉积覆层320。替代性地，覆层320可以从鳍区段313的顶部和这些侧外延地向外生长。覆层320可以是例如SiGe的晶体或非晶体形式，该SiGe将充当锗源用于创造富SiGe的鳍区段322。接下来，覆层320被暴露于富氧环境中，该环境在硅鳍区段313的表面处形成GeO2。然而，GeO2的化学键合倾向于是不稳定的，允许在鳍区段313中的下面的硅与GeO2反应以形成SiGe和SiO2。如在图7B中所示，此氧化反应有效地致使锗聚合到硅鳍区段313中，产生富含SiGe且被氧化物324包围的SiGe鳍区段322。所产生的富SiGe的鳍区段322具有基本上均匀的结构，其中，具有超过85％的浓度的锗原子被结合贯穿硅晶体晶格。
替代性地，覆层320可以由纯锗或者III-V材料(如，例如，磷化铟(InP)、砷化铟镓(InGaAs)等等)制成。
更一般地，通过其他工艺(如，外延生长、外延和以上描述的聚合工艺的组合、或者外延和扩散的组合)可以产生结合了第二半导体材料的鳍区段322。无论用于将新材料引入到沟道中的技术如何，因为在小占用面积、高纵横比的鳍的小体积之内不能累积应变，所产生的鳍区段322保持为完全弛豫的。
在214处，根据如在图8A至图8C中示出的一个实施例，在新的鳍区段322上形成薄的低K电介质材料(如，例如，HfO2)和金属栅极326。在自对准过程中在这些对侧壁间隔物314之间沉积金属栅极326。栅叠层金属可以包括通常在金属栅极工艺中使用的那些，例如，钨(W)、钛(Ti)、氮化钛(TiN)、功函数材料等等。在金属栅极326之上形成硬掩模帽盖328。在随后的接触形成过程中，将这些栅极分离开的氧化物318向下凹陷到鳍区段322的基部。注意到，每个金属栅极326基本上在鳍区段322之上居中。直接位于金属栅极326的下面的鳍区段322的多个部分将充当多个晶体管沟道，而在金属栅极326的影响之外的鳍区段322的多个部分将充当器件的源极区和漏极区。
在216处，在鳍区段322的侧壁上外延地生长源极延伸部和漏极延伸部330。首先，使用湿法化学工艺(如，例如，磷酸(H3PO4))修整SiN侧壁间隔物314，这将选择性地将SiN迁移到氧化物和硅。替代性地，可以使用HF-EG湿法蚀刻工艺，其中，组合氢氟酸(HF)与乙二醇(EG)以形成以基本上相等的速率去除SiN和SiO2两者的化学混合物。HF-EG制剂是有利的，因为其相比于仅仅HF具有较慢的蚀刻速率，当蚀刻或SiN或SiO2时，这种较慢的蚀刻速率提供了优越的工艺过程控制。如果使用HF-EG，可能侵蚀小量的BOX(大约5nm)，而不对器件完整性造成实质影响。
然后，通过SiGe、碳化硅(SiC)或者V族材料的选择性外延从鳍区段322的侧壁形成源极延伸部和漏极延伸部330。如在图10A中示出的，源极延伸部和漏极延伸部330从每个鳍区段322的末端向外延伸，在相对于鳍区段322的竖直轴线以锐角扩展鳍区段以产生菱形结构。以惯例方式，源极延伸部和漏极延伸部330可以用硼(B)、磷(P)或砷(As)原位掺杂以分别产生p型器件或n型器件。
在218处，根据如在图10A至图10C中示出的一个实施例形成到源极区和漏极区以及到源极延伸部和漏极延伸部330的多个金属接触332。形成这些金属接触332使用了常规的方法，其中，首先沉积金属内衬并且使其与硅反应以形成金属硅化物。然后，以惯例方式沉积体接触金属并将其平坦化以在硬掩模帽盖328上停止。
将理解的是，尽管出于说明的目的在此描述了本披露的多个具体实施例，在不背离本披露的精神和范围的情况下可以进行各种修改。相应地，除所附权利要求书之外，本披露不受限制。
鉴于以上详细的描述，可以对这些实施例做出这些和其他改变。总之，在以下权利要求书中，所使用的术语不应当被解释为将权利要求书局限于本说明书和权利要求书中所披露的特定实施例，而是应当被解释为包括所有可能的实施例、连同这些权利要求有权获得的等效物的整个范围。相应地，权利要求书不受本披露的限制。
以上所描述的各个实施例可以被组合以提供进一步的实施例。在本说明书中引用的和/或在申请数据表中列举的所有美国专利、美国专利申请公开、美国专利申请、外国专利、外国专利申请和非专利公开通过引用而完全并入于此。如果有必要，可以对实施例的各方面进行修改，以采用各专利、申请和公开的概念来提供更进一步的实施例。

Claims (20)

1.一种制造FinFET的方法，包括：
形成多个鳍，所述多个鳍从由第一半导体材料制成的衬底的表面竖直地向外延伸；
形成与所述多个鳍中的每个鳍的三侧接触的多个栅极结构，每个栅极结构包括牺牲栅极部件；
通过将所述多个鳍中的每个鳍分段为相应的多个鳍区段，使所述多个鳍弹性地弛豫；
从所述多个栅极结构中去除多个牺牲栅极部件；
将第二半导体材料结合到所述多个鳍区段中；
在所述多个栅极结构中形成多个金属栅极；并且
形成源极区和漏极区。
2.如权利要求1所述的方法，其中，形成所述源极区和所述漏极区包括：在所述多个栅极结构外侧的所述多个鳍的多个部分上形成多个外延延伸部。
3.如权利要求2所述的方法，进一步包括经由所述多个外延延伸部形成到所述源极区和所述漏极区的多个接触。
4.如权利要求1所述的方法，其中，所述衬底包括掩埋氧化物层。
5.如权利要求1所述的方法，其中，在所述多个鳍区段中的所述第二半导体材料的浓度超过了85％。
6.如权利要求1所述的方法，其中，所述多个鳍区段基本上没有晶体结构缺陷。
7.如权利要求1所述的方法，其中，所述多个牺牲栅极部件由多晶硅制成。
8.如权利要求1所述的方法，其中，使用选择性外延、非选择性外延、氧化工艺、聚合工艺和扩散工艺中的一项或多项来完成将所述第二半导体材料结合到所述多个鳍区段中。
9.如权利要求1所述的方法，其中，所述第二半导体材料包括锗、铟、磷、镓和砷中的一项或多项。
10.如权利要求1所述的方法，其中，使所述多个鳍弹性地弛豫包括：切割所述多个鳍以形成与所述多个栅极结构对准的多个鳍区段，所述多个鳍区段由多个鳍间间隙间隔开；并且
用绝缘体填充所述多个鳍间间隙。
11.一种制造FinFET的方法，包括：
从硅衬底形成多个硅鳍；
将多个栅极结构与所述多个硅鳍对准，每个栅极结构包括栅极电介质、牺牲多晶硅栅极和一对侧壁间隔物；
将所述多个硅鳍切割成多个硅鳍区段；
从所述多个栅极结构中去除多个牺牲多晶硅栅极；
使用氧化聚合工艺将所述多个硅鳍区段转换成多个富锗的SiGe鳍区段；
在每对侧壁间隔物的侧壁间隔物之间沉积多个金属栅极；并且
形成源极区和漏极区。
12.如权利要求11所述的方法，其中，所述形成所述源极区和所述漏极区包括选择性地生长多个外延延伸部。
13.如权利要求12所述的方法，其中，所述多个外延延伸部基本上是菱形形状的。
14.如权利要求12所述的方法，其中，所述多个外延延伸部包括硅、锗、碳、镓、砷、铟、磷及其组合中的一项或多项。
15.如权利要求11所述的方法，其中，所述硅衬底是绝缘体上硅(SOI)衬底、绝缘体上硅锗(SiGe-O-I)衬底和应变绝缘体上硅(sSOI)衬底中的一项。
16.一种鳍式FET阵列，包括：
在硅衬底的表面上以规则的间隔间隔开的多个鳍区段，所述多个鳍区段包括具有超过85％的浓度的锗；
相对于所述多个鳍区段以横向方向安排的多个栅极结构，每个栅极结构包括基本上在所述多个鳍区段中的一个鳍区段之上居中的金属栅极；以及
外延源极延伸部和外延漏极延伸部，所述外延源极延伸部和所述外延漏极延伸部相对于所述多个鳍区段的竖直轴线以锐角扩展所述多个鳍区段。
17.如权利要求16所述的鳍式FET阵列，其中，所述多个鳍区段在掩埋氧化物层的顶部上。
18.如权利要求16所述的鳍式FET阵列，其中，所述多个鳍区段具有大于5.0的纵横比。
19.如权利要求16所述的鳍式FET阵列，其中，所述多个鳍区段具有小于1000nm2的占用面积。
20.如权利要求16所述的鳍式FET阵列，其中，所述多个鳍区段基本上没有晶格缺陷。
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