JP5669752B2 - チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減 - Google Patents
チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減 Download PDFInfo
- Publication number
- JP5669752B2 JP5669752B2 JP2011542725A JP2011542725A JP5669752B2 JP 5669752 B2 JP5669752 B2 JP 5669752B2 JP 2011542725 A JP2011542725 A JP 2011542725A JP 2011542725 A JP2011542725 A JP 2011542725A JP 5669752 B2 JP5669752 B2 JP 5669752B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- forming
- semiconductor
- layer
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 194
- 229910045601 alloy Inorganic materials 0.000 title claims description 74
- 239000000956 alloy Substances 0.000 title claims description 74
- 230000008021 deposition Effects 0.000 title claims description 34
- 238000000034 method Methods 0.000 claims description 100
- 239000000463 material Substances 0.000 claims description 87
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 80
- 239000010703 silicon Substances 0.000 claims description 80
- 230000008569 process Effects 0.000 claims description 62
- 229910052710 silicon Inorganic materials 0.000 claims description 62
- 238000005530 etching Methods 0.000 claims description 34
- 238000002955 isolation Methods 0.000 claims description 31
- 239000002019 doping agent Substances 0.000 claims description 23
- 238000002513 implantation Methods 0.000 claims description 23
- 239000007772 electrode material Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 229910000927 Ge alloy Inorganic materials 0.000 claims description 16
- 229910000676 Si alloy Inorganic materials 0.000 claims description 16
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 14
- 239000003989 dielectric material Substances 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 11
- 238000003631 wet chemical etching Methods 0.000 claims description 8
- 238000000926 separation method Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 50
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 48
- 238000000151 deposition Methods 0.000 description 36
- 239000000377 silicon dioxide Substances 0.000 description 24
- 235000012239 silicon dioxide Nutrition 0.000 description 24
- 238000012545 processing Methods 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 239000000758 substrate Substances 0.000 description 10
- 239000000203 mixture Substances 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229910052732 germanium Inorganic materials 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000002210 silicon-based material Substances 0.000 description 6
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- PWYYWQHXAPXYMF-UHFFFAOYSA-N strontium(2+) Chemical compound [Sr+2] PWYYWQHXAPXYMF-UHFFFAOYSA-N 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0128—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0135—Manufacturing their gate conductors
- H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
- H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102008063402.6 | 2008-12-31 | ||
| DE102008063402A DE102008063402B4 (de) | 2008-12-31 | 2008-12-31 | Verringerung der Schwellwertspannungsfluktuation in Transistoren mit einer Kanalhalbleiterlegierung durch Verringern der Abscheideungleichmäßigkeiten |
| US12/637,112 | 2009-12-14 | ||
| US12/637,112 US8236654B2 (en) | 2008-12-31 | 2009-12-14 | Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities |
| PCT/EP2009/009307 WO2010076018A1 (en) | 2008-12-31 | 2009-12-29 | Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012514318A JP2012514318A (ja) | 2012-06-21 |
| JP2012514318A5 JP2012514318A5 (enExample) | 2013-02-07 |
| JP5669752B2 true JP5669752B2 (ja) | 2015-02-18 |
Family
ID=42234616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011542725A Active JP5669752B2 (ja) | 2008-12-31 | 2009-12-29 | チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8236654B2 (enExample) |
| JP (1) | JP5669752B2 (enExample) |
| KR (1) | KR101539416B1 (enExample) |
| CN (1) | CN102341906B (enExample) |
| DE (1) | DE102008063402B4 (enExample) |
| WO (1) | WO2010076018A1 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102009006886B4 (de) | 2009-01-30 | 2012-12-06 | Advanced Micro Devices, Inc. | Verringerung von Dickenschwankungen einer schwellwerteinstellenden Halbleiterlegierung durch Verringern der Strukturierungsungleichmäßigkeiten vor dem Abscheiden der Halbleiterlegierung |
| JP5605134B2 (ja) * | 2010-09-30 | 2014-10-15 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
| DE102010063296B4 (de) * | 2010-12-16 | 2012-08-16 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Herstellungsverfahren mit reduzierter STI-Topograpie für Halbleiterbauelemente mit einer Kanalhalbleiterlegierung |
| US8609509B2 (en) * | 2011-09-22 | 2013-12-17 | Globalfoundries Inc. | Superior integrity of high-k metal gate stacks by forming STI regions after gate metals |
| US8377773B1 (en) * | 2011-10-31 | 2013-02-19 | Globalfoundries Inc. | Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask |
| US8541281B1 (en) | 2012-08-17 | 2013-09-24 | Globalfoundries Inc. | Replacement gate process flow for highly scaled semiconductor devices |
| US8969190B2 (en) | 2012-08-24 | 2015-03-03 | Globalfoundries Inc. | Methods of forming a layer of silicon on a layer of silicon/germanium |
| US9029919B2 (en) | 2013-02-01 | 2015-05-12 | Globalfoundries Inc. | Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer |
Family Cites Families (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0809865B1 (en) * | 1995-12-15 | 2000-07-12 | Koninklijke Philips Electronics N.V. | SEMICONDUCTOR FIELD EFFECT DEVICE COMPRISING A SiGe LAYER |
| JP2000353753A (ja) * | 1999-06-14 | 2000-12-19 | Hitachi Ltd | 半導体装置の製造方法 |
| JP4866534B2 (ja) * | 2001-02-12 | 2012-02-01 | エーエスエム アメリカ インコーポレイテッド | 半導体膜の改良された堆積方法 |
| US6940089B2 (en) * | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
| JP2004006959A (ja) * | 2001-04-12 | 2004-01-08 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
| US6794252B2 (en) * | 2001-09-28 | 2004-09-21 | Texas Instruments Incorporated | Method and system for forming dual work function gate electrodes in a semiconductor device |
| US6600170B1 (en) * | 2001-12-17 | 2003-07-29 | Advanced Micro Devices, Inc. | CMOS with strained silicon channel NMOS and silicon germanium channel PMOS |
| CN100399576C (zh) * | 2002-03-28 | 2008-07-02 | 先进微装置公司 | 于沟道区域中具有退化掺杂分布的半导体组件及用于制造该半导体组件的方法 |
| KR100487525B1 (ko) * | 2002-04-25 | 2005-05-03 | 삼성전자주식회사 | 실리콘게르마늄 게이트를 이용한 반도체 소자 및 그 제조방법 |
| JP2003332458A (ja) * | 2002-05-09 | 2003-11-21 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| KR20030090411A (ko) * | 2002-05-23 | 2003-11-28 | 삼성전자주식회사 | 선택적 성장을 이용한 씨모스 게이트 및 그 제조방법 |
| CN100483666C (zh) * | 2003-01-07 | 2009-04-29 | S.O.I.Tec绝缘体上硅技术公司 | 施主晶片以及重复利用晶片的方法和剥离有用层的方法 |
| US6828181B2 (en) * | 2003-05-08 | 2004-12-07 | International Business Machines Corporation | Dual gate material process for CMOS technologies |
| CN100536167C (zh) * | 2003-08-05 | 2009-09-02 | 富士通微电子株式会社 | 半导体装置及其制造方法 |
| US7223679B2 (en) * | 2003-12-24 | 2007-05-29 | Intel Corporation | Transistor gate electrode having conductor material layer |
| WO2005106949A1 (ja) * | 2004-04-30 | 2005-11-10 | Matsushita Electric Industrial Co., Ltd. | 半導体の製造方法及び半導体装置 |
| JP2008513979A (ja) * | 2004-09-14 | 2008-05-01 | アリゾナ ボード オブ リージェンツ ア ボディー コーポレート アクティング オン ビハーフ オブ アリゾナ ステイト ユニバーシティ | 基板上でのSi−Ge半導体材料およびデバイスの成長方法 |
| JP2006108251A (ja) * | 2004-10-01 | 2006-04-20 | Rohm Co Ltd | 半導体装置の製造方法 |
| JP2006202928A (ja) * | 2005-01-19 | 2006-08-03 | Nec Electronics Corp | 半導体装置の製造方法 |
| US7132322B1 (en) * | 2005-05-11 | 2006-11-07 | International Business Machines Corporation | Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET device |
| TWI267926B (en) * | 2005-09-23 | 2006-12-01 | Ind Tech Res Inst | A new method for high mobility enhancement strained channel CMOS with single workfunction metal-gate |
| JP4795817B2 (ja) * | 2006-03-02 | 2011-10-19 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| JP2006332687A (ja) * | 2006-07-10 | 2006-12-07 | Fujitsu Ltd | Cmos半導体装置 |
| KR100809327B1 (ko) * | 2006-08-10 | 2008-03-05 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
| US7750374B2 (en) * | 2006-11-14 | 2010-07-06 | Freescale Semiconductor, Inc | Process for forming an electronic device including a transistor having a metal gate electrode |
| KR100773359B1 (ko) * | 2006-11-20 | 2007-11-05 | 삼성전자주식회사 | 높은 이동도를 갖는 트랜지스터들의 제조방법 및 그에 의해제조된 트랜지스터들 |
| US7598142B2 (en) * | 2007-03-15 | 2009-10-06 | Pushkar Ranade | CMOS device with dual-epi channels and self-aligned contacts |
| JP4898517B2 (ja) * | 2007-03-27 | 2012-03-14 | シャープ株式会社 | 半導体装置の製造方法 |
| US7709331B2 (en) * | 2007-09-07 | 2010-05-04 | Freescale Semiconductor, Inc. | Dual gate oxide device integration |
| US20090108294A1 (en) * | 2007-10-30 | 2009-04-30 | International Business Machines Corporation | Scalable high-k dielectric gate stack |
| US7718496B2 (en) * | 2007-10-30 | 2010-05-18 | International Business Machines Corporation | Techniques for enabling multiple Vt devices using high-K metal gate stacks |
| US8053306B2 (en) * | 2007-12-13 | 2011-11-08 | International Business Machines Corporation | PFET with tailored dielectric and related methods and integrated circuit |
| JP2010157570A (ja) * | 2008-12-26 | 2010-07-15 | Toshiba Corp | 半導体装置の製造方法 |
-
2008
- 2008-12-31 DE DE102008063402A patent/DE102008063402B4/de active Active
-
2009
- 2009-12-14 US US12/637,112 patent/US8236654B2/en active Active
- 2009-12-29 CN CN200980157723.XA patent/CN102341906B/zh active Active
- 2009-12-29 KR KR1020117018048A patent/KR101539416B1/ko not_active Expired - Fee Related
- 2009-12-29 WO PCT/EP2009/009307 patent/WO2010076018A1/en not_active Ceased
- 2009-12-29 JP JP2011542725A patent/JP5669752B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| WO2010076018A1 (en) | 2010-07-08 |
| CN102341906A (zh) | 2012-02-01 |
| CN102341906B (zh) | 2014-10-15 |
| JP2012514318A (ja) | 2012-06-21 |
| DE102008063402A1 (de) | 2010-07-08 |
| US8236654B2 (en) | 2012-08-07 |
| US20100164014A1 (en) | 2010-07-01 |
| DE102008063402B4 (de) | 2013-10-17 |
| KR101539416B1 (ko) | 2015-07-27 |
| KR20120067973A (ko) | 2012-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5781944B2 (ja) | スレッショルド調節半導体合金を堆積させるのに先立ちパターニング不均一性を低減することによる前記半導体合金の厚みばらつきの低減 | |
| TWI438867B (zh) | 具不同型式與厚度的閘極絕緣層之cmos裝置及其形成方法 | |
| US8343837B2 (en) | Work function adjustment in a high-k gate electrode structure after transistor fabrication by using lanthanum | |
| US8329549B2 (en) | Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure | |
| US20100244141A1 (en) | Threshold adjustment of transistors including high-k metal gate electrode structures comprising an intermediate etch stop layer | |
| US8349694B2 (en) | Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy | |
| US8378432B2 (en) | Maintaining integrity of a high-K gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy | |
| CN102446729B (zh) | 用湿式化学方法形成受控底切而有优异完整性的高介电系数栅极堆栈 | |
| JP5669752B2 (ja) | チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減 | |
| US20100330757A1 (en) | Enhanced cap layer integrity in a high-k metal gate stack by using a hard mask for offset spacer patterning | |
| US20120211838A1 (en) | Complementary Transistors Comprising High-K Metal Gate Electrode Structures and Epitaxially Formed Semiconductor Materials in the Drain and Source Areas | |
| US20130115773A1 (en) | Prevention of ILD Loss in Replacement Gate Technologies by Surface Treatmen | |
| US20110049585A1 (en) | Maintaining integrity of a high-k gate stack by passivation using an oxygen plasma | |
| US8324091B2 (en) | Enhancing integrity of a high-k gate stack by confining a metal cap layer after deposition | |
| US8513080B2 (en) | Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device | |
| US8377773B1 (en) | Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask | |
| WO2010086152A1 (en) | Reduction of thickness variations of a threshold adjusting semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121212 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20121212 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140226 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140228 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140526 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140813 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141105 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20141202 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141216 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5669752 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |