CN102341906B - 通过减少非均匀性沉积的包括沟道半导体合金的晶体管中的阈值电压变异的减少 - Google Patents
通过减少非均匀性沉积的包括沟道半导体合金的晶体管中的阈值电压变异的减少 Download PDFInfo
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- CN102341906B CN102341906B CN200980157723.XA CN200980157723A CN102341906B CN 102341906 B CN102341906 B CN 102341906B CN 200980157723 A CN200980157723 A CN 200980157723A CN 102341906 B CN102341906 B CN 102341906B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0128—Manufacturing their channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0135—Manufacturing their gate conductors
- H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
- H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102008063402.6 | 2008-12-31 | ||
| DE102008063402A DE102008063402B4 (de) | 2008-12-31 | 2008-12-31 | Verringerung der Schwellwertspannungsfluktuation in Transistoren mit einer Kanalhalbleiterlegierung durch Verringern der Abscheideungleichmäßigkeiten |
| US12/637,112 | 2009-12-14 | ||
| US12/637,112 US8236654B2 (en) | 2008-12-31 | 2009-12-14 | Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities |
| PCT/EP2009/009307 WO2010076018A1 (en) | 2008-12-31 | 2009-12-29 | Reduction of threshold voltage variation in transistors comprising a channel semiconductor alloy by reducing deposition non-uniformities |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102341906A CN102341906A (zh) | 2012-02-01 |
| CN102341906B true CN102341906B (zh) | 2014-10-15 |
Family
ID=42234616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200980157723.XA Active CN102341906B (zh) | 2008-12-31 | 2009-12-29 | 通过减少非均匀性沉积的包括沟道半导体合金的晶体管中的阈值电压变异的减少 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8236654B2 (enExample) |
| JP (1) | JP5669752B2 (enExample) |
| KR (1) | KR101539416B1 (enExample) |
| CN (1) | CN102341906B (enExample) |
| DE (1) | DE102008063402B4 (enExample) |
| WO (1) | WO2010076018A1 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102009006886B4 (de) | 2009-01-30 | 2012-12-06 | Advanced Micro Devices, Inc. | Verringerung von Dickenschwankungen einer schwellwerteinstellenden Halbleiterlegierung durch Verringern der Strukturierungsungleichmäßigkeiten vor dem Abscheiden der Halbleiterlegierung |
| JP5605134B2 (ja) * | 2010-09-30 | 2014-10-15 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
| DE102010063296B4 (de) * | 2010-12-16 | 2012-08-16 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Herstellungsverfahren mit reduzierter STI-Topograpie für Halbleiterbauelemente mit einer Kanalhalbleiterlegierung |
| US8609509B2 (en) * | 2011-09-22 | 2013-12-17 | Globalfoundries Inc. | Superior integrity of high-k metal gate stacks by forming STI regions after gate metals |
| US8377773B1 (en) * | 2011-10-31 | 2013-02-19 | Globalfoundries Inc. | Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask |
| US8541281B1 (en) | 2012-08-17 | 2013-09-24 | Globalfoundries Inc. | Replacement gate process flow for highly scaled semiconductor devices |
| US8969190B2 (en) | 2012-08-24 | 2015-03-03 | Globalfoundries Inc. | Methods of forming a layer of silicon on a layer of silicon/germanium |
| US9029919B2 (en) | 2013-02-01 | 2015-05-12 | Globalfoundries Inc. | Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030203560A1 (en) * | 2002-04-25 | 2003-10-30 | Samsung Electronics Co., Ltd. | CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof |
| CN1623234A (zh) * | 2002-03-28 | 2005-06-01 | 先进微装置公司 | 于沟道区域中具有退化掺杂分布的半导体组件及用于制造该半导体组件的方法 |
| US20080111155A1 (en) * | 2006-11-14 | 2008-05-15 | Freescale Semiconductor, Inc. | Electronic device including a transistor having a metal gate electrode and a process for forming the electronic device |
| US20080227250A1 (en) * | 2007-03-15 | 2008-09-18 | Pushkar Ranade | CMOS device with dual-EPI channels and self-aligned contacts |
Family Cites Families (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0809865B1 (en) * | 1995-12-15 | 2000-07-12 | Koninklijke Philips Electronics N.V. | SEMICONDUCTOR FIELD EFFECT DEVICE COMPRISING A SiGe LAYER |
| JP2000353753A (ja) * | 1999-06-14 | 2000-12-19 | Hitachi Ltd | 半導体装置の製造方法 |
| JP4866534B2 (ja) * | 2001-02-12 | 2012-02-01 | エーエスエム アメリカ インコーポレイテッド | 半導体膜の改良された堆積方法 |
| US6940089B2 (en) * | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
| JP2004006959A (ja) * | 2001-04-12 | 2004-01-08 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
| US6794252B2 (en) * | 2001-09-28 | 2004-09-21 | Texas Instruments Incorporated | Method and system for forming dual work function gate electrodes in a semiconductor device |
| US6600170B1 (en) * | 2001-12-17 | 2003-07-29 | Advanced Micro Devices, Inc. | CMOS with strained silicon channel NMOS and silicon germanium channel PMOS |
| JP2003332458A (ja) * | 2002-05-09 | 2003-11-21 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| KR20030090411A (ko) * | 2002-05-23 | 2003-11-28 | 삼성전자주식회사 | 선택적 성장을 이용한 씨모스 게이트 및 그 제조방법 |
| CN100483666C (zh) * | 2003-01-07 | 2009-04-29 | S.O.I.Tec绝缘体上硅技术公司 | 施主晶片以及重复利用晶片的方法和剥离有用层的方法 |
| US6828181B2 (en) * | 2003-05-08 | 2004-12-07 | International Business Machines Corporation | Dual gate material process for CMOS technologies |
| CN100536167C (zh) * | 2003-08-05 | 2009-09-02 | 富士通微电子株式会社 | 半导体装置及其制造方法 |
| US7223679B2 (en) * | 2003-12-24 | 2007-05-29 | Intel Corporation | Transistor gate electrode having conductor material layer |
| WO2005106949A1 (ja) * | 2004-04-30 | 2005-11-10 | Matsushita Electric Industrial Co., Ltd. | 半導体の製造方法及び半導体装置 |
| JP2008513979A (ja) * | 2004-09-14 | 2008-05-01 | アリゾナ ボード オブ リージェンツ ア ボディー コーポレート アクティング オン ビハーフ オブ アリゾナ ステイト ユニバーシティ | 基板上でのSi−Ge半導体材料およびデバイスの成長方法 |
| JP2006108251A (ja) * | 2004-10-01 | 2006-04-20 | Rohm Co Ltd | 半導体装置の製造方法 |
| JP2006202928A (ja) * | 2005-01-19 | 2006-08-03 | Nec Electronics Corp | 半導体装置の製造方法 |
| US7132322B1 (en) * | 2005-05-11 | 2006-11-07 | International Business Machines Corporation | Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET device |
| TWI267926B (en) * | 2005-09-23 | 2006-12-01 | Ind Tech Res Inst | A new method for high mobility enhancement strained channel CMOS with single workfunction metal-gate |
| JP4795817B2 (ja) * | 2006-03-02 | 2011-10-19 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| JP2006332687A (ja) * | 2006-07-10 | 2006-12-07 | Fujitsu Ltd | Cmos半導体装置 |
| KR100809327B1 (ko) * | 2006-08-10 | 2008-03-05 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
| KR100773359B1 (ko) * | 2006-11-20 | 2007-11-05 | 삼성전자주식회사 | 높은 이동도를 갖는 트랜지스터들의 제조방법 및 그에 의해제조된 트랜지스터들 |
| JP4898517B2 (ja) * | 2007-03-27 | 2012-03-14 | シャープ株式会社 | 半導体装置の製造方法 |
| US7709331B2 (en) * | 2007-09-07 | 2010-05-04 | Freescale Semiconductor, Inc. | Dual gate oxide device integration |
| US20090108294A1 (en) * | 2007-10-30 | 2009-04-30 | International Business Machines Corporation | Scalable high-k dielectric gate stack |
| US7718496B2 (en) * | 2007-10-30 | 2010-05-18 | International Business Machines Corporation | Techniques for enabling multiple Vt devices using high-K metal gate stacks |
| US8053306B2 (en) * | 2007-12-13 | 2011-11-08 | International Business Machines Corporation | PFET with tailored dielectric and related methods and integrated circuit |
| JP2010157570A (ja) * | 2008-12-26 | 2010-07-15 | Toshiba Corp | 半導体装置の製造方法 |
-
2008
- 2008-12-31 DE DE102008063402A patent/DE102008063402B4/de active Active
-
2009
- 2009-12-14 US US12/637,112 patent/US8236654B2/en active Active
- 2009-12-29 CN CN200980157723.XA patent/CN102341906B/zh active Active
- 2009-12-29 KR KR1020117018048A patent/KR101539416B1/ko not_active Expired - Fee Related
- 2009-12-29 WO PCT/EP2009/009307 patent/WO2010076018A1/en not_active Ceased
- 2009-12-29 JP JP2011542725A patent/JP5669752B2/ja active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1623234A (zh) * | 2002-03-28 | 2005-06-01 | 先进微装置公司 | 于沟道区域中具有退化掺杂分布的半导体组件及用于制造该半导体组件的方法 |
| US20030203560A1 (en) * | 2002-04-25 | 2003-10-30 | Samsung Electronics Co., Ltd. | CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof |
| US20080111155A1 (en) * | 2006-11-14 | 2008-05-15 | Freescale Semiconductor, Inc. | Electronic device including a transistor having a metal gate electrode and a process for forming the electronic device |
| US20080227250A1 (en) * | 2007-03-15 | 2008-09-18 | Pushkar Ranade | CMOS device with dual-EPI channels and self-aligned contacts |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2010076018A1 (en) | 2010-07-08 |
| CN102341906A (zh) | 2012-02-01 |
| JP5669752B2 (ja) | 2015-02-18 |
| JP2012514318A (ja) | 2012-06-21 |
| DE102008063402A1 (de) | 2010-07-08 |
| US8236654B2 (en) | 2012-08-07 |
| US20100164014A1 (en) | 2010-07-01 |
| DE102008063402B4 (de) | 2013-10-17 |
| KR101539416B1 (ko) | 2015-07-27 |
| KR20120067973A (ko) | 2012-06-26 |
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Legal Events
| Date | Code | Title | Description |
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| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Free format text: FORMER OWNER: AMD FAB 36 LIMITED LIABILITY COMPANY + CO. KG Effective date: 20120207 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20120207 Address after: American California Applicant after: Advanced Micro Devices Inc. Address before: American California Applicant before: Advanced Micro Devices Inc. Co-applicant before: AMD FAB 36 limited liability company |
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| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |